KR20160146363A - Method for compensating line voltage of multi-phase inverter - Google Patents

Method for compensating line voltage of multi-phase inverter Download PDF

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Publication number
KR20160146363A
KR20160146363A KR1020150083540A KR20150083540A KR20160146363A KR 20160146363 A KR20160146363 A KR 20160146363A KR 1020150083540 A KR1020150083540 A KR 1020150083540A KR 20150083540 A KR20150083540 A KR 20150083540A KR 20160146363 A KR20160146363 A KR 20160146363A
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South Korea
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voltage
pwm
phase
voltage command
carrier
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KR1020150083540A
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Korean (ko)
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김명호
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삼성중공업 주식회사
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/497—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode sinusoidal output voltages being obtained by combination of several voltages being out of phase
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/505—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means
    • H02M7/515—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only
    • H02M7/525—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only with automatic control of output waveform or frequency
    • H02M7/527—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only with automatic control of output waveform or frequency by pulse width modulation

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Inverter Devices (AREA)

Abstract

The present invention relates to a method of compensating an inter-line voltage error of a polyphase inverter device in which an inter-line voltage between two phases is ideally outputted by subtracting from a PWM voltage command of another phase by an error occurring in one phase. The method for compensating a line voltage error of a polyphase inverter device includes the steps of (a) comparing a first voltage command with a carrier wave to output a first phase actual PWM voltage modulated by a PWM method, (B) comparing a command and a carrier wave to extract a modulation error value of the first phase actual PWM voltage, (c) outputting a compensated second compensation voltage command by inverting the modulation error value to a second voltage command, And (d) comparing the second compensation voltage command with a carrier wave to output a second compensated PWM voltage modulated by a PWM method.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of compensating a line voltage error of a polyphase inverter device,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of compensating a line voltage error of a polyphase inverter device, and more particularly, to a method of subtracting a voltage command of a phase different from an error occurring in one phase to output an ideal line voltage between two phases.

In general, loads such as three-phase induction motors used in wind turbines and ships are driven in connection with power converters. Such a power conversion apparatus includes a digital controller such as a DSP (Digital Signal Processor) or an MCU (Micro Controller Unit) for controlling a plurality of semiconductor switches and semiconductor switches, and can convert DC to AC.

The power converter can synthesize the voltage of a phase, b phase and c phase output with a phase difference of 120 degrees with carrier of a certain frequency to a desired size and frequency by PWM method through a digital controller and supply it to the load.

At this time, the voltage supplied to the load may be a line-to-line voltage such as a-phase and b-phase, b-phase and c-phase, or c-phase and a-phase. However, this line voltage includes some errors according to the inverter control scheme. Line-to-line voltage without error compensation can be a factor that impedes performance degradation of the overall system and smooth control of the load.

Therefore, current research is actively conducted on methods for compensating for errors caused by voltage modulation. However, most of the progress has been made on the voltage drop of the switching element or the PWM error due to the switching delay, but the problem of the error generated in the digital controller controlling the inverter has not been done yet.

Korean Registered Patent No. 10-0724498 (2007.06.04)

SUMMARY OF THE INVENTION The present invention has been made in an effort to solve the above problems, and it is an object of the present invention to solve the above problems by providing a method of controlling a voltage Method.

The problems to be solved by the present invention are not limited to the above-mentioned problems, and other problems not mentioned can be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided a method of compensating a line voltage error of a polyphase inverter device, comprising: receiving a plurality of voltage commands having different phases and modulating an applied voltage command at a point in contact with a carrier wave, (A) of outputting a first phase actual PWM voltage modulated by a PWM method at a point where the first voltage command is in contact with a carrier wave, (B) comparing the first voltage command and the carrier to extract a modulation error value of the first phase actual PWM voltage, comparing the modulation error value with a second voltage command, (C) outputting a second compensation voltage command, comparing the second compensation voltage command with the carrier wave, and outputting a second compensated PWM voltage modulated in a PWM manner.

The polyphase inverter device may have three or more levels of multi-level, and the carrier wave may include a first carrier wave and a second carrier wave having the same size and the same period.

The step (b) may include comparing the first phase actual PMM voltage with the first carrier voltage after the first voltage command passes through the minimum value of the first carrier to extract the modulation error value have.

The voltage command is formed in such a manner that positive and negative values are alternated as in a sinusoidal wave such that the first carrier appears in a positive interval of the voltage command and the second carrier appears in a negative interval of the voltage command .

The method for compensating a line voltage error of a polyphase inverter apparatus according to the present invention is a method for compensating a line voltage error by inverting a modulation error extracted from a PWM voltage modulated by a PWM method to a voltage command of another phase, So that it is possible to output an inter-line voltage having the same average value as the ideal inter-line voltage and the PWM period.

1 is a flowchart of a method of compensating a line voltage error of a polyphase inverter according to an embodiment of the present invention.
2 is a circuit diagram of a polyphase inverter device according to an embodiment of the present invention.
3 is a diagram showing voltage commands of a-phase, b-phase and c-phase and waveforms of carrier waves.
FIG. 4 is a diagram showing a theoretical PWM voltage that is momentarily output at a point where a voltage command of the phase a and phase b of FIG. 3 is in contact with a carrier wave.
Fig. 5 is a diagram showing the theoretical line voltage output by the difference between the a-phase and b-phase theoretical PWM voltages of Fig. 4; Fig.
FIG. 6 is a diagram showing a section in which the switch of the inverter of the polyphase inverter apparatus of FIG. 2 is in the voltage command and the carrier is actually turned on and off.
FIG. 7 is a graph showing an ideal PWM voltage outputted according to a section where a digital voltage command and a carrier wave are in contact with each other in FIG.
Fig. 8 is a diagram showing this ideal line-to-line voltage output by the difference between the a-phase and b-phase ideal PWM voltages in Fig.
FIG. 9 is a diagram showing an actual PWM voltage outputted according to a voltage command of a and b phases of FIG. 6 and a waveform section of a carrier wave.
10 is a diagram showing a second compensating voltage command which is inversely related to the b-phase voltage command and a second compensating PWM voltage which is outputted according to a section in which the carrier wave is in contact with the second compensating voltage command in Fig.
11 is a diagram showing the corrected line voltage calculated through the a-phase actual PWM voltage and the b-phase compensated PWM voltage.

Brief Description of the Drawings The advantages and features of the present invention and methods of achieving them can be made clear with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. To fully disclose the scope of invention to a person skilled in the art, and the invention is only defined by the claims. Like reference numerals refer to like elements throughout the specification.

1 is a flowchart illustrating a method of compensating a line voltage error of a polyphase inverter according to an embodiment of the present invention.

The method of compensating the line-to-line voltage error of a polyphase inverter device is a method of outputting an average line-to-line voltage that is equal to the average voltage of an ideal line-to-line voltage by subtracting the error extracted from the PWM method of any phase from the voltage command of the other phase.

The method of compensating the line voltage error of a polyphase inverter device includes receiving a plurality of voltage commands having different phases and comparing a first voltage command among the applied voltage commands with a carrier wave to output a first phase actual PWM voltage modulated by the PWM method (S100), comparing the output first phase actual PWM voltage with the first voltage command and the carrier wave to extract a modulation error value of the first phase actual PWM voltage (S110), comparing the modulation error value with a second voltage command (S120), comparing the second compensation voltage command with a carrier wave, and outputting a second compensated PWM voltage modulated by a PWM method (S130) The average voltage of the ideal line-to-line voltage from the compensated PWM voltage and the first PWM voltage and the line-to-line voltage that is the same on the average in the PWM period can be output.

As a result, the load can always receive the ideal line voltage from the polyphase inverter device that has undergone this step.

Hereinafter, a polyphase inverter device for outputting a voltage command, a PWM voltage, and a line-to-line voltage will be described in detail with reference to Fig.

2 is a block diagram showing a configuration of a polyphase inverter device according to an embodiment of the present invention.

First, in the present specification, the polyphase inverter device 1 will be described with reference to a three-level inverter as an example for convenience of explanation. However, the polyphase inverter device 1 is not necessarily limited to three levels, Level or more.

The polyphase inverter device 1 is constituted by a plurality of inverters 20 and is capable of applying an ideal line voltage to one load 40. [ This multiphase inverter device 1 generally includes an AC power supply (not shown), a rectifying part for rectifying an AC current supplied from an AC power supply, a capacitor part 10 connected in parallel with a rectifying part, And a controller 30 for controlling the switching operation of the inverter unit 20 and the like.

The AC power source is a three-phase power source capable of outputting voltages on a-phase, b-phase, and c-phase having different phases, that is, each phase difference is 120 degrees. Sized alternating current is formed. One side of the AC power source is provided with a rectifying section for rectifying alternating current output from the AC power source to a pulsating current, and a capacitor section 10 may be provided at an output end of the rectifying section.

The capacitor portion 10 includes a first capacitor 11 and a second capacitor 12 which are polarized and exhibit the same electrical characteristics. The capacitor unit 10 stores the electric energy corresponding to the pulsating current rectified in the rectification unit in the first capacitor 11 and the second capacitor 12 or the electric energy stored in the first capacitor 11 and the second capacitor 12 To the inverter unit (20). When the charged electricity is discharged, the capacitor unit 10 converts it into a waveform close to DC and outputs it, so that a constant voltage can be applied to the inverter unit 20.

The inverter unit 20 is connected in parallel with the capacitor unit 10, and synthesizes the electric power with the desired size and frequency by using the electric energy stored in the capacitor unit 10, and outputs the combined AC voltage. The inverter unit 20 includes a inverter leg 20a for controlling the voltage on a plurality of inverters, that is, a voltage in the middle of the three phases, a inverter leg 20b for controlling the voltage on the b phase, The inverter legs 20c for controlling the inverter legs 20c are connected in parallel so that the line voltage between a phase and b phase or the line voltage between a phase and c phase or the line voltage between b phase and c phase required by the load 40, An arbitrary line-to-line voltage can be applied.

The inverter 20 includes power semiconductors S1 to S12 for controlling the flow of signals by voltage or current and diodes connected in anti-parallel to the power semiconductors S1 to S12, And a clamp diode connected to a connection point between the neutral point due to the connection of the capacitor 12 and the power semiconductors S1 to S12.

Here, the first power semiconductor S1 to the twelfth power semiconductor S12 may be elements having the same electrical characteristics, and the first power semiconductor S1 to the twelfth power semiconductor S12 may be current paths IGT, MOSFET, ICGT, GCT, SGCT, and GTO, which form a current path.

However, in this specification, an IGBT which is simple to drive and has high efficiency at high voltage and large current will be described as an example of the power semiconductors S1 to S12.

The IGBT has a gate, an emitter and a collector terminal, and a gate terminal may be provided with a controller 30.

The controller 30 can control the switching of the power semiconductors S1 to S12 so that a modulation error value that may be generated in the PWM synthesis is inverted to the voltage command of the other phase so that the error-compensated line-to-line voltage is output. The controller 30 includes an ideal PWM voltage generating unit 31, a realistic PWM voltage generating unit 32, an error extracting unit 33, a compensation voltage instruction unit 34, a compensated PWM voltage generating unit 35, Element.

Here, the ideal PWM voltage generator 31 calculates the ideal PWM voltage when the voltage command (V ra , V rb , see FIG. 6) in the IGBT is sampled at regular intervals and when it comes in contact with the carrier wave V c And performs the step of outputting the ideal PWM voltage by allowing the semiconductors S1 to S12 to be switched.

The actual PWM voltage generator 32 switches the power semiconductors S1 to S12 using the voltage command sampled every predetermined period and the carrier wave V c (see FIG. 6), so that the actual PWM voltage, that is, .

The error extracting unit 33 compares the ideal PWM voltage, the voltage command, and the carrier wave to extract a modulation error value. In other words, the step of extracting the difference value formed between the ideal PWM voltage and the actual PWM voltage is performed.

The compensation voltage command unit 34 performs the step of inverting the extracted modulation error value to the voltage command of the other phase to output the compensation voltage command. The compensated PWM voltage generator 35 performs inverse operation on the modulation error value (error) to a voltage command that becomes another phase voltage, and then compares the error with a carrier wave to output a compensated PWM voltage.

The controller 30 controls the switching of the power semiconductors S1 to S12 through the operation of each of these components so that the average voltage of the ideal line-to-line voltage in the polyphase inverter device 1 is substantially equal to the line- .

Hereinafter, with reference to Figures 3 and 4, a a, b a voltage command of the phase and the sine wave which correspond to phase c (V ra, V rb, V rc) and the carrier (V c) and the theoretical for the PWM voltage The waveform will be described.

3, V ra denotes a voltage command corresponding to a phase of the AC power source, V rb denotes a voltage command corresponding to the b phase of the AC power source, V rc denotes a voltage command corresponding to the C phase of the AC power source, V and c represents a carrier wave.

Voltage command (V ra, V rb, V rc) of each phase is formed of a sine wave, the phase of V rb is 120 degrees slower than the phase of the V ra phase V rc has a 120-degree fast characteristics than phase V ra . The carrier wave V c is a triangle wave and may be represented by a plurality of carriers, that is, a first carrier wave V c1 and a second carrier wave V c2 in an inverter device formed at three or more levels of multilevel. Here, the first carrier (V c1 ) appears in the positive section of the voltage command, and the second carrier (V c2 ) appears in the negative section.

At this time, the amplitude of each phase voltage command (V ra, V rb, V rc) is can be set to not more than the amplitude of the carrier (V c), the amplitude modulation index (m a: Amplitude modulation index) are each on the Can be calculated as the ratio of the amplitude of the voltage command (V ra , V rb , V rc ) to the amplitude of the carrier (V c ), and can be 2 or less.

Meanwhile, the frequency modulation index (m f ) is adjusted to various values through the controller 20. Since the frequency modulation index (m f ) is calculated by the ratio of the frequency of the voltage command to the frequency of the carrier wave, it can be output as various values.

FIG. 4 is a diagram showing a theoretical PWM voltage that is momentarily output at a point where a voltage command of the phase a and phase b of FIG. 3 is in contact with a carrier wave.

Fig. 4 (a) shows a voltage command (V ra ) of a phase, a voltage command (V rb ) of phase b, and a voltage command (V rb ) of a phase in the voltage commands V ra , V rb and V rc of each phase in a dotted- A part of one carrier V c1 and a part of the second carrier V c2 are shown in an enlarged scale.

FIG voltage command on a in (a) (V ra) and the first carrier (V c1) and a second carrier (V c2) the magnitude comparison to the voltage command (V ra) the first carrier on a in contact with the point ( V c1 ), the first power semiconductor S1 is turned on and the third power semiconductor S3 is turned off. Conversely, if the voltage command (V ra) on a carrier is less than the first (V c1), the first electric power is turned off and the semiconductor (S1), the third turns on the power semiconductor (S3). a voltage command on the (V ra) is greater than the second carrier (V c2), the second power semiconductor (S2) is turned off, the fourth power semiconductor (S4). Conversely, when the voltage command (V ra ) on the a phase is smaller than the second carrier (V c1 ), the second power semiconductor (S2) is turned off and the fourth power semiconductor (S4) is turned on.

Thus the turn of the power semiconductor-on and turn-off process to be the output of the theoretical (theoretical) PWM voltage (V SP _at) on a as shown in Figure 4 (b).

The b-phase voltage command V rb is compared with the voltage command V rb at the point where the first carrier V c1 and the second carrier V c2 are in contact with each other, If it is larger than the carrier wave V c1 , the fifth power semiconductor S5 is turned on and the seventh power semiconductor S7 is turned off. Conversely, if the b-phase voltage command V ra is smaller than the first carrier V c1 , the fifth power semiconductor S5 is turned off and the seventh power semiconductor S7 is turned on. When the voltage command (V rb ) on the b phase is larger than the second carrier (V c2 ), the sixth power semiconductor S6 is turned on and the eighth power semiconductor S8 is turned off. Conversely, when the b-phase voltage command V rb is smaller than the second carrier voltage V c1 , the sixth power semiconductor S6 is turned off and the eighth power semiconductor S8 is turned on.

Thus, the theoretical b-phase PWM voltage (V SP - bt ) can be output as shown in FIG. 4 (c) in the turn-on and turn-off modes of the power semiconductor.

Theoretical PWM voltage on the output a in this manner (V SP _at) and theoretical PWM voltage (V SP_bt) on the b is the theoretical PWM voltage (V SP _at) on a as shown in Figure 5 with the theoretical on the b the difference between the PWM voltage (V SP_bt), i.e., V SP _at - is calculated as V SP _bt, it is supplied to the load 40. At this time, the difference voltage of the theoretical PWM voltage on the a-phase and the b-phase becomes the theoretical line-to-line voltage (V SP - abt ).

Hereinafter, with reference to Fig. 6, the semiconductor switch of the polyphase inverter device of Fig. 2 is switched in detail.

FIG. 6 is a diagram showing a section in which the switch of the inverter of the polyphase inverter apparatus of FIG. 2 is actually turned on and off within a waveform section of a voltage command and a carrier wave.

The controller 30 controls the switching operation of the first power semiconductor S1 to the twelfth power semiconductor S12 at a point where the voltage command and the carrier wave are in contact with each other to synthesize the PWM voltage. However, the plurality of first power semiconductors S1 through the twelfth power semiconductors S12 controlled by the controller 30 are controlled by the first carrier V c1 and the second carrier V c2 in real time and the voltage command V ra, rb V) That is, the fundamental wave (which is switched by the magnitude comparison between reference wave) command value of the sampled reference wave in approximately regular intervals, rather than being switched by the magnitude comparison between a carrier wave (V c).

The switching pattern is composed of a single edge method in which the command value is compared with a carrier wave (V c ) of one cycle at once, and a double edge method in which the command value is compared with a carrier wave (Vc) of one cycle twice .

Among the switching pattern methods, the present specification defines sampling points as [N-1], [N], [N + 1], and [N + 2] on the basis of the double edge method, The command value at the start of the operation is sampled and output.

When the voltage command V ra is in a period (on period) during which the first carrier V c1 falls, the real PWM voltage generator 32 outputs the first, fifth, and ninth power semiconductors S1, S5, and S9 are turned on only and the third, seventh, and eleventh power semiconductors S3, S7, and S11 are controlled to operate only in a turn-off state and the voltage command is applied to the first carrier V c1 The first, fifth and ninth power semiconductors S1, S5 and S9 are operated only in the turn-off state and the third, seventh and eleventh power semiconductors S3, S7 and S11 ) Is controlled to be turned on only. The second, sixth, and tenth power semiconductors S2, S6, and S10 are turned on only when the voltage command is in a section (on section) in which the second carrier voltage V c2 falls, 4 and 8 and the twelfth power semiconductors S4, S8 and S12 are operated only in a turn-off state. When the voltage command is in a section (off section) in which the second carrier V c2 rises, Sixth, and tenth power semiconductors S2, S6, and S10 are turned on only and the fourth, eighth, and twelfth power semiconductors S4, S8, and S12 are turned on only.

That is, the realistic PWM voltage generator 32 operates the first, fifth, and ninth power semiconductors complementarily with the third, seventh, and eleventh power semiconductors, and the second, Fourth, eighth, and twelfth power semiconductors to output the actual PWM voltage.

Hereinafter, with reference to FIGS. 7 and 8, an ideal PWM voltage to be outputted in a section in which a part of the digital voltage command and the part of the carrier wave in the a-phase and the b-phase are outputted will be described in detail.

FIG. 7 is a diagram showing an ideal PWM voltage output according to a section in which a voltage command and a carrier wave are in contact with a phase a and phase b of FIG. 6, and FIG. And the ideal line-to-line voltage output.

First, FIG. 7 (a) is a voltage command (V ra) on a the voltage command of each phase in the rectangular display area of the dashed line (V ra, V rb, V rc) shown in Figure 6, the voltage command (V rb) on the b And a part of the first carrier V c1 and the second carrier V c2 are enlargedly shown.

In FIG. 7 (a), the voltage command (V ra ) on phase a and the phase command voltage (v rb ) on phase b are implemented in a digital device and can be represented by a digital voltage command. In other words, the voltage command (V ra ) on a can appear as a digital voltage command (V ra_do ) on a, and the voltage command (V rb ) on b can appear as a b-phase digital voltage command (V rb _do ).

The ideal PWM voltage generator 31 described above is configured such that the digital voltage command V ra of a phase is divided into a period in which the first carrier V c1 falls, that is, [N-1] to [N], [N + [N + 2] when hayeoteul in contact with the first carrier (V c1), the power semiconductor switching sikimyeo such that the output voltage is 0.5Vdc, the first carrier (V c1) the interval [N] ~ to increase [N + 1 ], The power semiconductor can be switched so that the output voltage becomes zero. Thus, as shown in FIG. 7 (b), an ideal PWM voltage (V SP - ai ) on a phase can be output.

The ideal PWM voltage generating unit 31 generates the ideal PWM voltage V b by setting the digital voltage command V rb of the b phase to a period in which the second carrier V c2 falls, that is, [N-1] to [N], [N + [N + 2] in when in contact with the second carrier (V c2), the output voltage and the power semiconductor is switched to zero, the second carrier (V c2) is in the up section [N] ~ [N + 1 ] to The power semiconductor can be switched so that the output voltage becomes -0.5 Vdc. Thus, as shown in Fig. 7 (c), the ideal PWM voltage (V SP - bi ) on the b phase can be output.

Is thus an ideal PWM voltage on the output a can be output (V SP _ai) and an ideal line-to-line voltage (V SP _ abi) as shown by the difference between the ideal PWM voltage (V SP _bi), in Fig. 8 on the b .

Hereinafter, with reference to FIG. 9, a practical PWM voltage outputted in a section where a part of the digital voltage command and the part of the carrier wave are in contact with each other will be described in detail.

FIG. 9 is a diagram showing a real PWM voltage output according to a voltage command of a and b phases of FIG. 6 and a waveform section of a carrier wave.

In reality digital voltage command is ideal PWM voltage is not modulated in the PWM voltage ideally by the generation section 32, set real PWM voltage generation unit of the digital voltage command sampled at the sampling interval and for outputting in accordance with the contact points of the carrier (V c) Is modulated to the actual PWM voltage by the inverter 32.

Realistic PWM voltage generation unit 32 has the carrier (V c) is turned to the falling-in-on period that is, [N-1] ~ [ N], [N + 1] ~ [N + 2] interval the first and 2, the fifth, sixth, ninth, tenth power semiconductors (S1, S2, S5, S6, S9, S10) for controlling so that only work on, the carrier (V c) is raised turned to-off period that is , And control to turn off the first, second, fifth, sixth, ninth, tenth power semiconductors S1, S2, S5, S6, S9, S10 only in the [N] do. That is, the real PWM voltage generator 32 generates the first, second, fifth, sixth, ninth, and tenth power semiconductors S1, S2, and S5 when the digital voltage command is in contact with the carrier wave in the turn- The first, second, fifth, sixth, ninth, and tenth power semiconductors are turned on when the digital voltage command is touched between the carrier wave and turn-off. (S1, S2, S5, S6, S9, S10).

Accordingly, according to the turn-on and turn-off sections of the power semiconductor, the digital voltage command (b rb_do ) of the b phase can be smoothly converted into an actual PWM Can be modulated and output. However, after a digital voltage control value is out of the minimum value of the carrier (V c), back carrier (V c) and when in contact, that is, the turn-on period and the turn-the-carrier digital voltage instruction from the boundary point of the off-period (V c , The power semiconductor is not switched to the on state in the section ahead of this section, and thus the power semiconductor is maintained in the off state.

Accordingly, FIG. 9, as shown in (b), a digital voltage control value on a (V ra _do) is [N] ~ [N + 1 ] when the interval hayeoteul contact with the first carrier (V c1), the output voltage 0.5 Vdc is not modulated with the modulation with a zero voltage, is modulated with the actual voltage on a PWM modulation has the error value (error) (V SP _ar) . Furthermore, the actual PWM voltage (V SP - ar ) on a phase having such a modulation error value causes a problem of generating an error in the line voltage with another phase.

Hereinafter, with reference to FIG. 10 and FIG. 11, it is assumed that the corrected PWM voltage output by inversely multiplying the modulation error value by the other voltage command, and the corrected line voltage output from the difference between the line voltage having the modulation error value and the compensated PWM voltage The voltage will be described.

10 is a diagram showing a second compensating voltage command which is inversely added to the b-phase voltage command in Fig. 9 and a second compensating PWM voltage which is outputted in accordance with a section in which the carrier wave is in contact with the second compensating voltage command, Is a diagram showing the corrected line voltage calculated through the first and second compensation PWM voltages.

The modulation error value (error) is measured in the above-described compensation voltage command section 34, and the modulation error is subtracted from the voltage command which is different from the measured voltage command. In other words, the a-phase modulation error value (error) caused by the difference between the ideal PWM voltage (V SP_ai ) on a phase and the actual PWM voltage (V SP_ar ) on phase a is given by the voltage command (b rb ) It is inversed.

Accordingly, the b-phase voltage command (V rb _do ) as shown by a dotted rectangle in FIG. 10 (a) can be represented as a compensated b-phase compensation voltage command (V rb _dm ) .

Compensation voltage command (V rb _dm) on these b may be modulated by a second carrier wave (V c2) with the compensation PWM voltage (V SP _bm) on b from the region in contact by the above-described compensation PWM voltage generation unit 35 . In this case, the compensation PWM voltage (V SP _bm) on the modulated waveform b is represented by the modulated value of the error (error) produced by the voltage command (V _do ra) and the first carrier (V c1) on a reflected.

Accordingly, the cost between the actual PWM voltage (V SP _ar) and modulation error is reflected compensated PWM voltage (V SP_bm) on the b line voltage on a modulation error occurs, as shown in Figure 11 is the average of the ideal line voltage cycle It becomes possible to output the waveform with the same period as the voltage.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, You can understand that you can. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

1: Multiphase inverter device 10: Capacitor part
20: Three-phase inverter 20a: a Inverter leg
20b: b Inverter leg 20c: c Inverter leg
30: Controller 31: Ideal PWM Voltage Generator
32: realistic PWM voltage generator 33: error extractor
34: compensation voltage command section 35: compensation PWM voltage generation section
40: Load V ra , V rb , V rb : Voltage command
V c : carrier wave V c1 : first carrier
V c2 : Second carrier V ra _do , V rb _do : Digital voltage command
V SP _ai , V SP _bi : Ideal PWM phase voltage
V SP _ abi: ideal line voltage on ab
V ra _dm: compensation on the command voltage V b _ar SP, SP V _br: actual PWM voltage
V SP _ abr : Actual line voltage on the ab

Claims (4)

A method of compensating a line voltage error of a polyphase inverter device which receives a plurality of voltage commands having different phases and modulates an applied voltage command at a point in contact with a carrier wave to output a plurality of PWM voltages modulated by a PWM method,
(A) outputting a first phase actual PWM voltage modulated by a PWM method at a point where the first voltage command is in contact with a carrier wave;
(B) comparing the first phase actual PWM voltage, the first voltage command and the carrier wave to extract a modulation error value of the real first phase actual PWM voltage;
(C) outputting a compensated second compensation voltage command by inverting the modulation error value to a second voltage command;
And (d) comparing the second compensation voltage command with the carrier to output a second compensated PWM voltage modulated by a PWM method. The method as claimed in claim 1, wherein the polyphase inverter device comprises three levels or more of multilevels, and the carrier wave includes a first carrier wave and a second carrier wave having the same size and the same period. 3. The method according to claim 2, wherein the step (b) comprises comparing the first phase actual PWM voltage with the first phase actual PWM voltage when the first voltage command passes through the minimum value of the first carrier, A method for compensating a line voltage error of a polyphase inverter device for extracting an error value. The voltage command generator according to claim 2, wherein the voltage command is formed in such a manner that positive and negative values are alternated as in a sine wave, the first carrier appears in a positive interval of the voltage command, A method for compensating a line voltage error of a polyphase inverter device in a period of.
KR1020150083540A 2015-06-12 2015-06-12 Method for compensating line voltage of multi-phase inverter KR20160146363A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102141713B1 (en) 2019-12-12 2020-08-06 주식회사 모피어스시큐리티 Golf assistant apparatus capable of measuring putting distance and direction
KR20220011396A (en) 2020-07-21 2022-01-28 주식회사 모피어스시큐리티 Golf assistant apparatus integrating putting measurement with distance measurement

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100724498B1 (en) 2006-02-16 2007-06-04 엘에스산전 주식회사 Method for compensating voltage of matrix converter and apparatus thereof

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100724498B1 (en) 2006-02-16 2007-06-04 엘에스산전 주식회사 Method for compensating voltage of matrix converter and apparatus thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102141713B1 (en) 2019-12-12 2020-08-06 주식회사 모피어스시큐리티 Golf assistant apparatus capable of measuring putting distance and direction
KR20220011396A (en) 2020-07-21 2022-01-28 주식회사 모피어스시큐리티 Golf assistant apparatus integrating putting measurement with distance measurement

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