JP5247282B2 - Power converter - Google Patents

Description

  The present invention relates to a power conversion device formed by connecting in series each AC side of first and second power converters that perform power conversion between DC and AC by controlling on / off of a switching element. The present invention relates to a technique for improving a voltage waveform at the time of voltage switching.

  A conventional power converter includes, for example, a three-phase inverter as a first power converter, and a single-phase inverter as a second power converter connected in series to each phase output of the three-phase inverter. The power converter is composed of a single-phase inverter that supplies a difference in which the output voltage waveform of the three-phase inverter deviates from the sine wave, and as a whole, a sine wave output voltage waveform is obtained (for example, a patent) Reference 1).

JP 2000-50643 A

  As an example of a conventional power conversion device, a so-called two-level inverter will be described. The switching elements of the upper arm and the lower arm are alternately turned on. However, for example, even if the drive signal for switching off the switching element of the upper arm and the drive signal for switching on the switching element of the lower arm are simultaneously output from the control device, there is a delay in the gate drive circuit and the switching element, Since the amount of delay differs between when the signal is on and when it is off, the switching element of the upper arm and the switching element of the lower arm are not switched simultaneously.

  Therefore, for example, when a drive signal is sent simultaneously to both inverters to decrease the output voltage of the single-phase inverter at the timing of increasing the output voltage of the three-phase inverter, the timing at which the output voltage of the three-phase inverter actually increases There may be a difference depending on various conditions on the timing when the output voltage of the single-phase inverter drops. Thus, when a deviation occurs in the voltage change timing of the output voltage of both inverters, the voltage that is added to both outputs and supplied to the load generates a surge-like voltage at this voltage switching timing. Electromagnetic noise is generated, which adversely affects surrounding equipment and causes various adverse effects such as increasing the iron loss of the load.

  The present invention was made to solve the above-described problems, and in a power conversion device in which a plurality of inverters are connected in series in each phase, the timing at which the voltages of the inverters connected in series are switched. An object is to provide a power converter that suppresses surge voltage.

A power converter according to the present invention is formed by connecting in series each AC side of first and second power converters that perform power conversion between DC and AC by controlling on / off of switching elements. Because
In a power converter including a drive signal generation circuit that generates a first drive signal for driving a switching element of a first power converter and a second drive signal for driving a switching element of a second power converter ,
In order to decrease or increase the AC output voltage of the second power converter at the timing of increasing or decreasing the AC output voltage of the first power converter, the first and second drive signals created as the first and second drive signals are used. Voltage change timing at which the AC output voltage of the first power converter actually rises or falls with respect to the command drive signal of 2, and voltage change timing at which the AC output voltage of the second power converter actually falls or rises. Drive signal correction means for correcting the first and second command drive signals to output the first and second corrected drive signals so as to have the same synchronous voltage change timing,
The drive signal generation circuit generates a first drive signal by PWM (pulse width modulation) control based on the AC voltage command, and generates a deviation command that is a deviation between the AC voltage command and the AC output voltage of the first power converter. Based on this, the second drive signal is created by PWM control.
A lead time setting circuit is provided to advance the AC voltage command for a predetermined time,
The drive signal correcting means includes a short-circuit prevention time set in the first and second power converters, and an on / off state from the on / off drive signal input to the on / off operation output in the switching elements of the first and second power converters. Based on the delay time and the direction of the AC side current of the first and second power converters, the first and second voltage drive timings based on the first and second command drive signals are matched with the synchronous voltage change timing. The second correction drive signal is obtained by delaying the first and second command drive signals by a predetermined correction time amount .

As described above, in the power conversion device according to the present invention, the drive signal correction means is provided to correct the first and second command drive signals and output the first and second corrected drive signals. Therefore, the voltage change timing at which the AC output voltage of the first power converter actually rises or falls and the voltage change timing at which the AC output voltage of the second power converter actually falls or rises are the same synchronous voltage change The surge voltage that occurs at the time of voltage switching is suppressed.
Furthermore, the voltage output from the first and second power converters matches the phase and timing of the voltage to be output.

Embodiment 1 FIG.
1 is a diagram showing an overall configuration of a power conversion device according to Embodiment 1 of the present invention. As shown in the figure, the main circuit configuration of the power converter is that a single-phase inverter 2 that is a second power converter is connected to each phase output line on the AC side of the three-phase inverter 1 that is a first power converter. Are connected in series. The AC side of the single-phase inverter 2 is connected to the three-phase inverter 1 on one side and to the load 3 on the other side. Although omitted in FIG. 1, the three-phase inverter 1 is provided with a DC voltage source from which power is supplied. The single-phase inverter 2 has a direct-current voltage source on the direct-current side and receives power supply from the direct-current voltage source, or has a structure in which power is supplied from the three-phase inverter 1 and maintained by controlling the direct-current voltage of the single-phase inverter 2. Good.

The three-phase inverter 1 is a two-level inverter including diodes 13a to 13f connected in antiparallel with switching elements 12a to 12f as shown in FIG. 2 and a capacitor 11 as a DC circuit.
The single-phase inverter 2 is a single-phase full-bridge two-level inverter composed of switching elements 18a to 18d, diodes 19a to 19d, and a capacitor 20 as shown in FIG.

  Next, the control operation in the power conversion device according to the first embodiment will be described. To facilitate the understanding, first, the control operation in the conventional device and the problem in the conventional device already described in the problem column are described. The point will be described in detail.

FIG. 4 shows the overall configuration of the conventional power converter, and the main circuit configuration is the same as that shown in FIG. 1 of the present invention.
The load control circuit 4 in FIG. 4 is a circuit for controlling the load 3 and outputs a voltage command (AC voltage command) output from the power converter. This is input to the drive signal generation circuit 5.

The inside of the drive signal generation circuit 5 is shown in FIG. If the AC voltage command from the load control circuit 4 is shown in FIG. 6A, the three-phase inverter PWM circuit 30 calculates and subtracts the PWM (pulse width modulation) voltage as shown in FIG. 6B. Output to.
The subtractor 31 subtracts the AC voltage command output from the load control circuit 4 and the PWM voltage waveform output from the PWM circuit 30 of the three-phase inverter 1 to create a deviation command. The waveform obtained as a result is as shown in FIG. Since this waveform is obtained by subtracting the voltage actually output from the AC voltage command, which is an ideal voltage of the three-phase inverter 1, the surplus harmonics among the voltages output by the three-phase inverter 1 The wave voltage is inverted between positive and negative. Therefore, when a voltage is output from the single-phase inverter 2 using this voltage waveform as a command, the single-phase inverter 2 operates so as to cancel the surplus harmonic voltage output from the three-phase inverter 1. Can be reduced.

The waveform in FIG. 6B is a voltage waveform when viewed from the virtual neutral point of the DC voltage of the three-phase inverter 1, and the zero-phase voltage included in this voltage waveform affects the line voltage. It is known that it does not affect the voltage of the load 3 because it does not exist. The waveform of FIG. 6C calculated from the waveform of FIG. 6B including the zero phase voltage also includes the zero phase voltage, and even if this zero phase voltage is changed, the load 3 is not affected. Therefore, for example, when the zero-phase voltage is set to 0 from the waveform of FIG. 6C, the waveform of FIG. 6D is obtained. By manipulating the zero-phase voltage in this way, the amplitude of the voltage command of the single-phase inverter 2 can be reduced.
When PWM is applied to FIG. 6D, a waveform as shown in FIG. 6E is obtained. The phase voltage of the load 3 is obtained by adding the voltages of the three-phase inverter 1 and the single-phase inverter 2 and excluding the zero-phase voltage, and has a waveform shown in FIG.

  Here, as an example, the zero-phase voltage operation circuit 32 sets the zero-phase voltage to 0, but other methods such as a method of reducing the amplitude of the voltage command by using the zero-phase voltage as, for example, the third harmonic voltage may be used. Alternatively, even if the zero phase voltage operation circuit 32 is omitted and the zero phase voltage is not manipulated, the present invention is not affected. Therefore, it can be applied to a power conversion apparatus that does not operate a zero-phase voltage as in Patent Document 1, as will be described later. Further, even when the three-phase inverter 1 is a single-phase inverter and the power conversion device is connected to a single-phase load, the zero-phase voltage operation circuit 32 can be omitted and applied to a single-phase power conversion device.

  Here, as apparent from a comparison between FIG. 6B and FIG. 6C or FIG. 6D, when the three-phase inverter 1 is switched, the voltage command of the single-phase inverter 2 varies greatly. That is, when the output voltage of the three-phase inverter 1 is switched to cancel the harmonic voltage output from the three-phase inverter 1, the single-phase inverter 2 also switches the output voltage in the opposite direction to the three-phase inverter 1. In this case, the output voltage of the single-phase inverter 2 is decreased at the timing when the output voltage of the three-phase inverter 1 is increased, or the output voltage of the single-phase inverter 2 is increased at the timing when the output voltage of the three-phase inverter 1 is decreased. It means that there is a need.

Here, the operation at the time of switching in a general two-level inverter will be described.
In the case of a two-level inverter, the switching elements of the upper arm and the lower arm are turned on alternately. However, for example, even if the drive signal for switching off the switching element of the upper arm and the drive signal for switching on the switching element of the lower arm are simultaneously output from the control device, there is a delay in the gate drive circuit and the switching element, Since the amount of delay differs between when the signal is on and when it is off, the switching element of the upper arm and the switching element of the lower arm are not switched simultaneously. At this time, if both switching elements are turned on at the same time, the DC circuit is short-circuited. Therefore, a period in which both the upper arm and lower arm switching elements are turned off by delaying the normally on signal by several microseconds. create. This is called a short circuit prevention time.

  FIG. 7 shows the relationship between the drive signal output by the control circuit with a general two-level inverter and the actual output voltage in consideration of the delay such as the short-circuit prevention time. In the following, the short-circuit prevention time is Td, the delay time from when the drive signal generating circuit 5 turns on the drive signal to when the switching element is actually turned on is T1, and actually after the drive signal generating circuit 5 turns off the drive signal. The delay time until the element is turned off is T2.

The drive signal output from the drive signal generation circuit 5 outputs a signal for switching the switching element of the upper arm from on to off, and then turns on the switching element of the lower arm with a delay of Td set as shown in FIG. Is output. Here, while the upper arm switching element is on, the voltage between the collector and emitter of the switching element is a voltage of several volts determined by the characteristics of the element. Here, since this may be regarded as 0 volts, in the following, the voltage when the switching element is on is treated as 0 volts.
While the upper arm switching element is on, the collector-emitter voltage V _CE of the switching element is zero. When the drive signal output from the control circuit is switched off, the switching element is turned off with a delay of T2. Further, there is a delay of Td from when the drive signal for turning off the switching element of the upper arm is output until the drive signal for turning on the switching element of the lower arm is output, and further, T1 until the switching element of the lower arm is turned on. Therefore, the switch is turned on with a delay of (Td + T1) after the drive signal for turning off the switching element of the upper arm is output.

Further, when the switching element is turned off, the operation is different depending on which of the switching element and the diode a current flows. If the current is flowing through the switching element, the current is commutated to the diode on the opposite arm as soon as the switching element is turned off. Therefore, when the switching element is turned off, V _CE becomes the DC voltage of the two-level inverter. If the current is flowing through the diode when the switching element is turned off, the current continues to flow through the diode even when the switching element is turned off, and does not commutate until the opposite switching element is turned on. Therefore, even if the switching element is turned off, V _CE of the upper arm switching element remains 0 until the lower arm switching element is turned on. Therefore, even if the drive signal is the same, the _{VCE of} each switching element differs depending on the direction of the current. If the direction of the current is a positive direction toward the load, a solid line in FIGS. V _CE becomes indicated, in the negative direction current toward the load, the V _CE shown by a broken line. That is, the phase voltage of the inverter also changes depending on the direction of the current. If the current is positive toward the load, the voltage waveform is a solid line in FIG. 7D. If the current is negative toward the load, the voltage waveform is a broken line. Become.
As described above, since the actual voltage waveform includes Td, T1, and T2, the timing differs from the on / off timing of the drive signal, and the voltage further varies depending on the current direction.

In a conventional power converter, a plurality of inverters are connected in series. First, the operation of each inverter during switching will be described.
FIG. 8 shows a one-phase current path when the three-phase inverter 1 is the circuit of FIG. When the DC voltage of the circuit of FIG. 2 is Em, and the voltage output from the virtual neutral point of the DC circuit to the AC side by the three-phase inverter 1 is seen, the output voltage is either Em / 2 or −Em / 2. Become.
If the current output from the three-phase inverter 1 is in the positive direction toward the load, when the output voltage of the three-phase inverter 1 is Em / 2, the path indicated by the thick line in FIG. Current flows in the direction. That is, a current flows through the switching element 12a of the upper arm. On the other hand, when switching is performed from FIG. 8A and the switching element 12a is turned off and 12b is turned on, the output voltage of the three-phase inverter 1 is switched to -Em / 2, and the current flows along the path indicated by the bold line in FIG. Since current flows, a current flows through the diode 13b of the lower arm.

  FIG. 9 shows a current path when the single-phase inverter 2 has the circuit configuration of FIG. 3 and a current flows in the positive direction from the three-phase inverter 1 toward the load 3. The current path in this case is as shown in FIG. 9A, in which current flows from the diode 19a to the load 3 via the capacitor 20 and diode 19d, and in FIG. 9 where current flows from the switching element 18b to the load 3 via the capacitor 20 and switching element 18c. There are four current paths, (b), FIG. 9 (c) in which current flows to the load 3 through the diode 19a and the switching element 18c, and FIG. 9 (d) in which current flows through the switching element 18b and the diode 19d. Further, the voltage direction is positive in the direction from the three-phase inverter 1 to the load 3, and the direct-current voltage of the single-phase inverter 2 is Es. The voltage output by the single-phase inverter 2 is Es, 0, and -Es. One. In FIG. 9, (b) when the output voltage is Es, (c) and (d) when the output voltage is 0, and (a) when the output voltage is -Es.

When the current is flowing in the positive direction toward the load 3, the three-phase inverter 1 is switched and the output voltage is switched from Em / 2 to -Em / 2. Switch to (b). At this time, as described above, the single-phase inverter 2 of the same phase is switched in the direction in which the voltage increases, contrary to the three-phase inverter 1. That is, the output voltage may be switched from -Es to 0 or Es, or may be switched from 0 to Es. When the output voltage is switched from -Es to 0, it is switched from FIG. 9A to (c) or (d), and when the output voltage is switched from -Es to Es, from FIG. Switch to b). The output voltage is switched from 0 to Es in two cases, ie, when switching from (c) to (b) in FIG. 9 and when switching from (d) to (b).
Therefore, when the current commutates from the switching element 12a to the diode 13b in the three-phase inverter 1, the current commutates from one of the diodes 19a to 19d to the switching element 18a to 18d on the opposite arm in the single-phase inverter 2. .

A shift in timing at which the voltage generated at this time is switched will be described.
The short-circuit prevention time of the three-phase inverter 1 is Tdm, the delay time from when the drive signal generation circuit 5 turns on the drive signal to when the switching element is actually turned on is T1m, and the drive signal generation circuit 5 turns off the drive signal. T2m is a delay time from when the device is actually turned off to when the device is turned off. For the single-phase inverter 2, the short-circuit prevention time is Tds, the delay time from when the drive signal generation circuit 5 turns on the drive signal to when the switching element is actually turned on is T1s, and the drive signal generation circuit 5 drives. A delay time from when the signal is turned off to when the element is actually turned off is defined as T2s.

As an example, consider a case where the three-phase inverter 1 is switched from FIG. 8A to FIG. 8B and the single-phase inverter 2 is switched from FIG. 9A to FIG.
The drive signal generating circuit 5 outputs a signal for turning off the switching elements 12a of the three-phase inverter 1 and simultaneously outputs a signal for turning off the switching elements 18a and 18d of the single-phase inverter 2. Thereafter, the drive signal generation circuit 5 issues a command to turn on the switching element of the arm opposite to the arm to which the three-phase inverter 1 and the single-phase inverter 2 are turned off, but the three-phase inverter 1 is Tdm and the single-phase inverter 2 is A signal that turns on with a delay of Tds is output.

  If the current is in the positive direction toward the load 3, the three-phase inverter 1 switches from FIG. 8 (a) to FIG. 8 (b), and thus is a commutation from the switching element 12a to the diode 13b. As described with reference to FIG. 7, the phase voltage of the three-phase inverter 1 is switched after T2m after the drive signal generation circuit 5 outputs a signal for turning off the switching element 12a. It switches as follows. Since the single-phase inverter 2 is switched from FIG. 9A to FIG. 9B, commutation from the diode 19d to the switching element 18c occurs in the arm on the load 3 side, and from the diode 19a in the arm on the three-phase inverter 1 side. A commutation occurs in the switching element 18b. Therefore, in the single-phase inverter 2, the switching is performed after (Tds + T1s) after the drive signal generation circuit 5 outputs a signal for turning off the switching elements 18a and 18d, and a solid line in FIG. 10 (d) is obtained. When the phase voltage of the three-phase inverter 1 shown by the solid line in FIG. 10C and the phase voltage of the single-phase inverter 2 shown by the solid line in FIG. 10D are added, a solid line of FIG. 10E is obtained.

In FIG. 10 (e), the absolute value of the voltage is reduced by switching the single-phase inverter 2 after the voltage greatly fluctuates in the negative direction at the timing when the phase voltage of the three-phase inverter 1 is switched. This surge voltage is a voltage that should not occur if the voltages of the three-phase inverter 1 and the single-phase inverter 2 change simultaneously.
Also, the broken lines in FIGS. 10C, 10 </ b> D, and 10 </ b> E are voltage waveforms when current flows in the negative direction toward the load 3. In this case, a surge voltage is generated in the positive direction with the composite phase voltage of FIG.
Further, even when the voltage switching of the single-phase inverter 2 is in another pattern, the voltage switching of the single-phase inverter 2 is delayed by (Tds + T1s) because the commutation is similarly performed from the diode to the switching element of the opposite arm. Therefore, when the voltage switching between the three-phase inverter 1 and the single-phase inverter 2 is shifted, and the voltage change width is different but the current direction is the same, the above timing is changed from FIG. 9 (a) to FIG. 9 (b). It is the same as when switching.
Similarly, when the voltage of the three-phase inverter 1 is switched in the reverse direction, a timing shift occurs when the voltages of the three-phase inverter 1 and the single-phase inverter 2 are switched.

  If there is a timing shift when the voltages of the three-phase inverter 1 and the single-phase inverter 2 are switched, FIG. 6 is as shown in FIG. In particular, the voltage of the load 3 has a voltage waveform with a surge voltage as shown in FIG.

  FIG. 12 is an example of a voltage waveform when the voltage changes sharply. Even if the voltage on the single-phase inverter 2 side of the cable connecting the single-phase inverter 2 and the load 3 is as shown in FIG. 12 (a), the voltage of the load 3 depends on the inductance of the cable and the stray capacitance between the ground and the like. A voltage waveform as shown in FIG. The peak of the voltage change in FIG. 12B reaches twice as much as the voltage changed by the switching in FIG. 12A, and the dielectric strength required for the load 3 increases. Further, when a harmonic current flows due to such a steep change in voltage, electromagnetic noise is caused, which adversely affects surrounding equipment and increases iron loss of the load.

The control operation in the conventional apparatus and the problems associated therewith have been described above. The power conversion apparatus according to the first embodiment of the present invention will be described below in comparison with the contents.
Returning to FIG. 1, a current sensor 40 is provided between the single-phase inverter 2 and the load 3, or between the three-phase inverter 1 and the single-phase inverter 2, and the measured current value is input to the drive signal generation circuit 5A.
The drive signal generation circuit 5A is configured by a PWM pattern storage circuit 46 as shown in FIG.
The PWM pattern storage circuit 46 stores a drive signal pattern for turning on and off the switching elements of the three-phase inverter 1 and the single-phase inverter 2 for each type of voltage switching operation, and a voltage command from the load control circuit 4. According to the value and the current measured by the current sensor 40, an optimum pattern is output from the stored patterns.

  In other words, the PWM pattern storage circuit 46 decreases or increases the AC output voltage of the single-phase inverter 2 at the timing of increasing or decreasing the AC output voltage of the three-phase inverter 1, so that the first and second drive signals respectively. The voltage change timing at which the AC output voltage of the three-phase inverter 1 actually increases or decreases and the voltage at which the AC output voltage of the single-phase inverter 2 actually decreases or increases with respect to the generated first and second command drive signals. Drive signal correction means for correcting the first and second command drive signals and outputting the first and second corrected drive signals so that the change timing becomes the same synchronous voltage change timing, and the voltage switching operation First and second correction drive signals corresponding to the first and second command drive signals stored in advance for each type are read out It can be said that the.

Hereinafter, a procedure for creating the first and second corrected drive signals from the first and second command drive signals will be described.
FIG. 14 shows the output of the drive signal generation circuit 5A and the phase voltage of the three-phase inverter 1, the phase voltage of the single-phase inverter 2, the single-phase inverter 1 and the single-phase inverter 1 when the current is flowing in the positive direction toward the load 3. The phase voltage waveform which match | combined the phase voltage of the phase inverter 2 is shown. A solid line represents each waveform when the pulse correction of the first embodiment is performed, and corresponds to the first and second correction drive signals described above. A broken line is a waveform when correction is not performed, and corresponds to the above-described first and second command drive signals. When the correction is not performed, it is the same as the solid line in FIG.

A signal for turning off the switching element 12a of the upper arm of the three-phase inverter 1 is output as indicated by a broken line in FIG. 14A, and at the same time, a switching element of the single-phase inverter 2 as indicated by a broken line in FIG. A signal for turning off 18a and 18d is output. This timing is an ideal timing for phase voltage switching between the three-phase inverter 1 and the single-phase inverter 2. Therefore, the drive signal output from the drive signal generation circuit 5A is advanced so that the phase voltage switching timing of the three-phase inverter 1 and the single-phase inverter 2 is aligned with the ideal timing.
When a current flows in the positive direction toward the load 3 and the switching element 12a of the upper arm of the three-phase inverter 1 is turned off, the phase voltage switching timing is delayed by T2m. As indicated by the solid line in a), the switching element OFF signal is output T2m earlier. On the other hand, since the phase voltage switching timing of the single-phase inverter 2 is delayed by (Tds + T1s), as shown by a solid line in FIG. 14 (b), the switching elements 18a and 18d off signals are output earlier. Thereby, the actual voltage switching timing becomes an ideal timing. Therefore, the phase voltage switching timings of the three-phase inverter 1 and the single-phase inverter 2 are aligned, and at the same time, the voltage is switched. Therefore, no surge voltage is generated in the phase voltage of the three-phase inverter 1 and the single-phase inverter 2. No surge voltage is generated in the voltage of the load 3.

  When the current is negative, the phase voltage of the three-phase inverter 1 is switched (Tdm + T1m) after the drive signal of the switching element 12a of the upper arm of the three-phase inverter 1 is turned off as indicated by the broken line in FIG. The single-phase inverter 2 is switched with a delay of T2s after the drive signals of the switching elements 18a and 18d are turned off. Accordingly, as shown by the solid line in FIG. 15A, the timing at which the phase voltage of the three-phase inverter 1 is switched by correcting the timing at which the drive signal of the switching element 12a is turned off (Tdm + T1m) is corrected to an ideal timing. be able to. The single-phase inverter 2 has an ideal timing at which the phase voltage of the single-phase inverter 2 is switched by advancing the timing at which the drive signals of the switching elements 18a and 18d are turned off by T2s as indicated by the solid line in FIG. Can be adjusted to any timing.

  In addition to the example given here, the case where the three-phase inverter 1 is switched from FIG. 8B to FIG. 8A, or the pattern of the single-phase inverter 2 is changed from FIG. 9A to FIG. ), The drive signal can be corrected by the same method even when the direction of the current is different.

  With such a configuration, the phase voltage switching timings of the three-phase inverter 1 and the single-phase inverter 2 are aligned, and the voltages are switched at the same time. Therefore, the phase voltages of the three-phase inverter 1 and the single-phase inverter 2 are The surge voltage caused by the inverter short-circuit prevention time, gate circuit characteristics, and switching element characteristics can be reduced. Therefore, the surge voltage of the voltage of the load 3 is also reduced, and the distortion of the overall output voltage other than the surge voltage can be reduced.

  As a result, special measures for reducing electromagnetic noise are not required, and the apparatus is miniaturized. Further, losses such as iron loss are reduced, and the lifetime of the apparatus is increased.

Embodiment 2. FIG.
The timing for switching the voltage to the ideal timing by advancing the drive signal is the same as in the first embodiment, but an example of drive signal correction means different from the first embodiment is described in the second embodiment. Will be described below.
FIG. 16 is a diagram showing an overall configuration of the power conversion device according to Embodiment 2 of the present invention. FIG. 17 is a diagram showing an internal configuration of the drive signal generation circuit 5B of FIG.
In FIG. 17, a pulse correction circuit 44 and a pulse correction circuit 45 are added to the drive signal generation circuit 5 of FIG. 5, and the drive signal and current sensor output by the three-phase inverter PWM circuit 30 are added to the pulse correction circuit 44. The current value measured at 40 is input. The pulse correction circuit 45 receives a drive signal output from the single-phase inverter PWM circuit 33 and a current value measured by the current sensor 40.

The pulse correction circuit 44 and the pulse correction circuit 45 delay the drive signal to at least the maximum value of the correction amount for advancing the drive signal and determine the direction of the current, and use FIGS. 14 and 15 in the first embodiment. Substantially the same processing as the drive signal correction described above is performed.
Within the time delayed by the pulse correction circuit 44 and the pulse correction circuit 45, the drive signal can be corrected and advanced, so that the same correction as shown in FIGS. 14 and 15 is possible. . In addition, it is assumed that the delay times in the pulse correction circuits 44 and 45 are equal.

FIG. 18 is a diagram showing an internal configuration of the load control circuit 52 of FIG. The load control circuit 52 functions as an advance time setting circuit that compensates for the time delayed by the pulse correction circuits 44 and 45 in the subsequent stage by advancing the AC voltage command.
The load control circuit 4A in the load control circuit 52 outputs the angular frequency and phase of the output voltage used to calculate the AC voltage command of the load control circuit 4 of FIG. The multiplier 50 multiplies the advance time set value and the angular frequency output from the load control circuit 4A to obtain a phase that rotates at the time set by the advance time set value. This is added by an adder 51 to the phase output by the load control circuit 4A. This means that the future phase is obtained for the time set by the advance time set value. The output of the adder 51 is input to the load control circuit 4A. In the load control circuit 4A, the load control calculation is performed at the same current phase as the previous load control circuit 4, but the phase of the voltage command to be output is the future phase by the advance time set value output by the adder 51. Calculate and output the value. The advance time set value is set to be the same as the time delayed by the pulse correction circuits 44 and 45.

In this way, the phase that is added by the adder 51 of FIG. 18 and advanced by the pulse correction circuits 44 and 45 is delayed so that the voltages output by the three-phase inverter 1 and the single-phase inverter 2 are It matches the phase and timing that should be output.
Therefore, the timing of voltage switching between the three-phase inverter 1 and the single-phase inverter 2 is the same, the short-circuit prevention time of each inverter, the characteristics of the gate circuit and the switching of the phase voltage combined with the three-phase inverter 1 and the single-phase inverter 2 Surge voltage due to element characteristics can be suppressed.
In addition, unlike the first embodiment, it is not necessary to calculate and store a large number of drive signal patterns in advance in accordance with the direction of the voltage command or current, so that the configuration becomes simple.

  The reason why the load control circuit 52 outputs the voltage command of the future phase by the advance time set value is that the pulse correction circuits 44 and 45 have a delay action and compensate for control errors caused thereby. However, if the error is sufficiently small and does not cause a problem because the angular frequency is small, the phase compensation may be omitted and the configuration may be further simplified using the load control circuit 4 of FIG. 4 as it is.

Embodiment 3 FIG.
In the third embodiment, first, another method for correcting a pulse (drive signal) will be described.
In FIG. 19, the current flows in the positive direction toward the load 3, and the three-phase inverter 1 is the same as the previous FIG. 8A to FIG. 8B, and the single-phase inverter 2 is the previous FIG. 9A. The waveform when switching from to (b) is shown, the broken line is the case where no correction is performed, and the solid line is the case where the correction of the third embodiment is performed.
In the third embodiment, when the current is flowing in the positive direction toward the load 3, as shown in FIG. 19A, the switching element of the three-phase inverter 1 output by a drive signal generation circuit 5B described later The drive signal for turning off 12a is delayed by (Tds + T1s-T2m) and output. A command to turn off the switching elements 18a and 18d of the single-phase inverter 2 is output at the same timing.

  That is, in the third embodiment, the voltage change timing at which the voltage change timing of the AC output voltage is slower than the drive signal change timing of either the three-phase inverter 1 or the single-phase inverter 2 is The drive signal is corrected so as to coincide with the synchronous voltage change timing described above. Here, since the voltage change timing in the single-phase inverter 2 is later, the drive signal is not corrected (the correction amount is zero). The drive signal of the phase inverter 1 is corrected.

  As a result, as shown in FIG. 19C, the timing at which the phase voltage of the three-phase inverter 1 is switched can be aligned with the timing at which the phase voltage of the single-phase inverter 2 is switched. Thereby, the surge voltage of the phase voltage combining the three-phase inverter 1 and the single-phase inverter 2 can be suppressed. Therefore, the surge voltage of the voltage of the load 3 can be suppressed.

  The above method assumes that (Tds + T1s−T2m) is a positive value, but if (Tds + T1s−T2m) is negative, correct the timing of the drive signal to the three-phase inverter 1. If the timing of the drive signal to the single-phase inverter 2 is delayed by-(Tds + T1s-T2m), the timing at which the phase voltage of the single-phase inverter 2 switches is matched with the timing at which the phase voltage of the three-phase inverter 1 switches. Similarly, the surge voltage of the voltage of the load 3 can be suppressed.

  When the current is flowing in the negative direction toward the load 3, as shown in FIG. 20, a command to turn off the switching elements 18a and 18d of the single-phase inverter 2 output from the drive signal generation circuit 5B is (Tdm + T1m−T2s). ) Output with delay. A command to turn off the switching element 12a of the three-phase inverter 1 is output at a conventional timing. By this correction, the timing at which the phase voltage of the single-phase inverter 2 is switched can be matched with the timing at which the voltage of the three-phase inverter 1 is switched as shown in FIG. Therefore, as shown in FIG. 20E, the surge voltage of the phase voltage combining the three-phase inverter 1 and the single-phase inverter 2 can be suppressed, and the surge voltage of the voltage of the load 3 can be suppressed.

  Further, the above method assumes that (Tdm + T1m−T2s) is a positive value, but when (Tdm + T1m−T2s) is negative, the timing of the signal to the single-phase inverter 2 is set as before. If the timing of the signal to the three-phase inverter 1 is delayed by-(Tds + T1s-T2m), the timing at which the phase voltage of the three-phase inverter 1 is switched to the timing at which the phase voltage of the single-phase inverter 2 is switched. The surge voltage of the voltage of the load 3 can be suppressed.

  In addition to the example given here, the case where the three-phase inverter 1 is switched from FIG. 8B to FIG. 8A, or the pattern of the single-phase inverter 2 is from FIG. 9A. When switching to (c), the same correction can be performed even when the direction of the current is different.

  In the third embodiment, as shown in FIG. 1, a current sensor 40 is provided between the single-phase inverter 2 and the load 3, or between the three-phase inverter 1 and the single-phase inverter 2, and the measured current value is a drive signal generation circuit. Input to 5B. The drive signal generation circuit 5B has a configuration as shown in FIG. 21, for example. The difference from the drive signal generation circuit 5 of FIG. 5 is that a pulse correction circuit 41 is provided between the three-phase inverter PWM circuit 30 and the Td generation circuit 70, and the pulse correction circuit 43 is subtracted from the three-phase inverter PWM circuit 30. This is provided between the container 31 and the container 31.

  In accordance with the current value measured by the current sensor 40, the pulse correction circuit 41 corrects the drive signal output from the three-phase inverter PWM circuit 30 in the manner described with reference to FIGS. The pulse correction circuit 43 shifts the voltage of the single-phase inverter 2 by shifting the timing at which the phase voltage of the three-phase inverter 1 used for the voltage command calculation of the single-phase inverter 2 is switched according to the direction of the current measured by the current sensor 40. The timing at which the command is switched can be shifted, and the timing of the drive signal for driving the switching element of the single-phase inverter 2 can be shifted. In this way, the moments when the voltages of the three-phase inverter 1 and the single-phase inverter 2 are switched can be aligned.

  In order to correct the drive signal of the single-phase inverter 2, the output of the three-phase inverter PWM circuit 30 is corrected depending on the zero-phase voltage operation circuit 32 according to an AC voltage command as shown in FIG. This is because there is a change due to phase switching, so that the number of calculations for correcting between the single-phase inverter PWM circuit 33 and the Td generation circuit 71 increases. Therefore, when the zero-phase voltage operation circuit 32 is omitted, it is easy to perform an operation by inserting a correction circuit between the single-phase inverter PWM circuit 33 and the Td generation circuit 71. Even if there is the zero-phase voltage operation circuit 32, the single-phase inverter PWM circuit 33 and the Td generation circuit 71 are calculated by performing an operation for determining which phase of the three-phase inverter 1 is switched to change the AC voltage command. Pulse correction can be performed between

  By adopting such a configuration, the surge voltage of the load 3 caused by the short-circuit prevention time of each inverter, the characteristics of the gate circuit and the characteristics of the switching element without comprehensively calculating and storing the drive signal pattern in advance. Can be suppressed. Further, since it is not necessary to delay the signal, the control response can be increased.

Embodiment 4 FIG.
The fourth embodiment shows that a three-phase inverter 1 itself can be applied to a configuration different from the previous one. That is, even if the three-phase inverter 1 is the three-phase three-level inverter shown in FIG. 22, the voltage between the three-phase inverter 1 and the single-phase inverter 2 is determined in the same manner as in the first to third embodiments. The voltage surge can be suppressed by correcting the shift.

  As a case where a current flows in the positive direction toward the load 3, the current flows in the three-phase three-level inverter 1 toward the single-phase inverter 2 through the switching elements 16a and 16b of FIG. The current flows in the direction of the single-phase inverter 2 through the diode 15a and the switching element 16b in FIG. 24, and the current flows in the direction of the single-phase inverter 2 through the diodes 17d and 17c in FIG. One of three cases. Further, when the DC voltage of the three-phase inverter 1 is Em and the voltages of the capacitors 14a and 14b are the same Em / 2, the output voltage of the three-phase three-level inverter 1 is Em / 2 in the case of FIG. 23 and in the case of FIG. Is 0, and in the case of FIG. 25, -Em / 2. Therefore, the case where the phase voltage of the three-phase three-level inverter 1 is switched to the decreasing direction is any one of FIG. 23 to FIG. 24, FIG. 24 to FIG. 25, and FIG. In the case of FIGS. 23 to 24, commutation occurs from the switching element 16a to the diode 15a. 24 to 25, commutation occurs from the diode 15a and the switching element 16b to the diodes 17d and 17c. In the case of FIGS. 23 to 25, commutation occurs from the switching elements 16a and 16b to the diodes 17d and 17c.

  In either case, commutation from the switching element to the diode occurs as in the case of the two-level inverter described with reference to FIG. Therefore, the difference in timing of voltage switching between the three-phase inverter 1 and the single-phase inverter 2 is the same as when the three-phase inverter 1 is at two levels. The same applies to the case where the polarity of the voltage and the direction of the current are different. Therefore, the deviation in voltage switching between the three-phase inverter 1 and the single-phase inverter 2 can be corrected using the same method as in the first to third embodiments.

  Thus, even when a 3-level inverter is used instead of a 2-level inverter instead of a 2-level inverter but having a smaller error with the voltage command, the short-circuit prevention time of each inverter, the characteristics of the gate circuit and switching The surge voltage of the load 3 due to the element characteristics can be suppressed.

Embodiment 5 FIG.
The fifth embodiment shows that a single-phase inverter 2 having a configuration different from the previous one can be applied. That is, even if the single-phase inverter 2 is a two-level half bridge circuit as shown in FIG. 26, the three-phase inverter 1 and the single-phase inverter 2 The voltage surge can be suppressed by correcting the voltage switching deviation.

  The current flows in the positive direction toward the load 3 when the current flows through the capacitor 21a and the switching element 22a in FIG. 27A, and when the current in FIG. 27B flows through the capacitor 21b and the diode 23b. There are two patterns: Assuming that the voltages of the capacitors 21a and 21b are the same and Es / 2, in the case of FIG. 27A, the output voltage is Es / 2, and in the case of FIG. 27B, the output voltage is -Es / 2. When the voltage of the three-phase inverter 1 is switched to the decreasing direction and the voltage of the single-phase inverter 2 is switched to the increasing direction, the switching is performed from the diode 23b to the switching element 22a. To commutate. The commutation from the diode to the switching element is the same as in the case of the two-level full bridge circuit described with reference to FIG.

  Therefore, the difference in voltage switching between the three-phase inverter 1 and the single-phase inverter 2 is the same as when the single-phase inverter 2 is a two-level full bridge circuit. Further, the case where the voltage has a different polarity and the direction of the current is the same as the two-level full bridge circuit. Therefore, the deviation in voltage switching between the three-phase inverter 1 and the single-phase inverter 2 can be corrected using the same method as in the first to third embodiments.

  Thus, even if the single-phase inverter 2 is not a two-level full-bridge circuit but a two-level half-bridge circuit with few components, it is caused by the short-circuit prevention time of each inverter, the characteristics of the gate circuit, and the characteristics of the switching element. The surge voltage of the load 3 can be suppressed.

Embodiment 6 FIG.
Furthermore, even if the single-phase inverter 2 is a three-level full-bridge inverter as shown in FIG. 28, the three-phase inverter 1 and the single-phase inverter 2 The voltage surge can be suppressed by correcting the voltage switching timing deviation.

  In the circuit of FIG. 28, when the current flows in the positive direction toward the load 3, as shown in FIG. 29, the current flows through the diodes 25b and 25a and the switching elements 24e and 24f, and as shown in FIG. When the current flows through the switching element 24c, the diode 26b, the diode 26c, and the switching element 24f, when the current flows through the switching element 24c, the switching element 24d, the diode 25h, and the diode 25g as shown in FIG. 31, and as shown in FIG. When the current flows through the switching elements 24c and 24d, the capacitors 27b and 27a, and the switching elements 24e and 24f, and the current flows through the switching element 24c, the diode 26b, the capacitor 27a, and the switching elements 24e and 24f as shown in FIG. As shown in FIG. 34, when current flows through the switching elements 24c and 24d, the capacitor 27b, the diode 26c, and the switching element 24f, and as shown in FIG. 35, the diodes 25b and 25a, the capacitor 27a, the diode 26c, and the switching element. The case where current flows through 24f, the case where current flows through switching element 24c, diode 26b, capacitor 27b, diodes 25h, 25g as shown in FIG. 36, and the case where diode 25b, diode 25a, capacitor 27a, In some cases, current flows through the diodes 27b and the diodes 25h and 25g.

  Assuming that the voltages of the capacitors 27a and 27b are the same and Es / 2, the output voltage of the single-phase inverter 2 is 0 in the case of FIGS. 29, 30, and 31, Es in the case of FIG. 32, and Es in the cases of FIGS. / 2, FIGS. 35 and 36, −Es / 2, and FIG. 37, −Es.

  When switching is performed so that the voltage of the three-phase inverter 1 decreases, the output voltage of the three-phase inverter 1 shifts from a state where the voltage is too high to a state where it is too low with respect to the command. Therefore, the output voltage of the single-phase inverter 2 shifts from a voltage that decreases the combined voltage of the three-phase inverter 1 and the single-phase inverter 2 to a voltage that increases the combined voltage. Therefore, the output voltage of the single-phase inverter 2 is switched from -Es to Es, Es / 2, 0, from -Es / 2 to Es, Es / 2, 0, and from 0 to Es, Es / 2. There are times when it switches to. Although detailed description of each is omitted, in most cases, the pattern is a commutation from a diode to a switching element. Since this pattern has the same timing shift as the case where the single-phase inverter 2 is a two-level full bridge circuit, the methods of the first to third embodiments can be applied as they are.

An exceptional pattern is the case of switching from FIG. 35 to FIG.
When switching from FIG. 35 to FIG. 31, the diodes 25b and 25a are commutated to the switching elements 24c and 24d, and the diode 26c and the switching element 24f are commutated to the diodes 25h and 25g. The drive signals of the three-phase inverter 1 and single-phase inverter 2 and the voltage switching timing of the three-phase inverter 1 and single-phase inverter 2 at this time are as shown in FIG. In the three-phase inverter 1, the driving signal for turning off the switching element 12a is turned off, and the voltage is switched after T2m as shown by the solid line in FIG.

In the single-phase inverter 2, in the circuit on the three-phase inverter 1 side from the capacitors 27a and 27b, commutation does not commutate until the switching elements 24c and 24d are turned on. Assuming that the voltage from the input terminal on the three-phase inverter 1 side of the single-phase inverter 2 to the DC voltage neutral point between the capacitors 27a and 27b is the three-phase inverter 1 side voltage of the single-phase inverter 2, FIG. As indicated by the solid line, the voltage is switched after the drive signals of the switching elements 24a and 24b are turned off (Tds + T1s).
On the other hand, on the load 3 side of the capacitors 27a and 27b, when the switching element 24f is turned off, the current is commutated to the diodes 25h and 25g. Assuming that the voltage from the DC voltage neutral point to the load 3 side output terminal is the load 3 side voltage of the single-phase inverter 2, the voltage is switched after T2s as shown by the solid line in FIG. Therefore, the voltage of the single-phase inverter 2 is a voltage obtained by combining FIGS. 38D and 38E, and is as shown by a solid line in FIG. When this is combined with the phase voltage of the three-phase inverter 1 in FIG. 38 (c), the solid line in FIG. 38 (g) is obtained.
Further, when the direction of the current is opposite, the waveform is as shown by a broken line in FIG.

  As described above, when the drive signal is simultaneously turned off, the voltage switching between the three-phase inverter 1 and the single-phase inverter 2 is divided into three times. As shown below, the voltage is corrected by correcting the drive signal of each element. The timing of switching can be aligned.

  When the current is positive, the drive signals for the switching elements 12a and 12b are advanced by T2m as shown in FIG. 39A, and the drive signals for the switching elements 24a, 24b, 24c, and 24d as shown in FIG. 39B. (Tds + T1s) earlier, the drive signals of the switching elements 24f, 24h are advanced T2s, so that the voltage switching timing of the three-phase inverter 1 and the single-phase inverter 2 can be aligned, and the surge voltage of the load 3 can be suppressed. it can.

  Even when the current is negative, the drive signals of the switching elements 12a and 12b are advanced by (Tdm + T1m) as shown in FIG. 40A, and the switching elements 24a, 24b, 24c and 24d are changed as shown in FIG. The drive signal is advanced by T2s, and the drive signals of the switching elements 24f and 24h are advanced by (Tds + T1s), so that the timing of voltage switching of the three-phase inverter 1 and the single-phase inverter 2 can be aligned, and the surge voltage of the load 3 can be reduced. Can be suppressed.

This is an application of the first and second embodiments, and can be realized by changing the pulse correction algorithm in the control circuit.
Further, as in the case of the third embodiment, if the driving signal is delayed, the correction may be made to match the latest one of the voltage switching timing shifts in the three-phase inverter 1 and the single-phase inverter 2. Therefore, this can be realized by changing the pulse correction algorithm in the control circuit of the third embodiment.

As described above, the single-phase inverter 2 can output a voltage with a smaller error from the AC voltage command than the two-level inverter, but even when a three-level full bridge circuit having a complicated configuration is used, the short-circuit prevention time of each inverter The surge voltage of the load 3 due to the characteristics of the gate circuit and the characteristics of the switching element can be suppressed.
In the above fourth to sixth embodiments, the case where either the three-phase inverter 1 or the single-phase inverter 2 is different from the circuit used in the description of the first to third embodiments has been described. Any combination is possible, such as the three-level inverter of FIG. 22 and the single-phase inverter 2 of the three-level inverter of FIG. 28, and the surge voltage of the load 3 can be suppressed by the same method.

Embodiment 7 FIG.
In the first to sixth embodiments described above, the single-phase inverter 2 has been described with respect to an example in which one phase is provided. However, as illustrated in FIG. 41, the single-phase inverter 2 includes the AC side of a plurality of single-phase inverters. It may be connected in series. Even if it is such a structure, the surge voltage of the load 3 can be suppressed using the method similar to Embodiment 1-6.
41 and 42 are diagrams assuming that the same technique as that of the second embodiment is used. The drive signal generation circuit 82 is a single-phase inverter PWM circuit 90 as shown in FIG. A drive signal for the inverters 80 and 81 is generated. The pulse correction circuits 91 and 92 may operate in the same manner as the pulse correction circuit 45 of the second embodiment. The single-phase inverters 80 and 81 may be the same circuit, for example, a combination of different circuits such as the single-phase inverter 80 being a two-level inverter and the single-phase inverter 81 being a three-level inverter, or a combination of the single-phase inverters 80 and 81 having different DC voltages. I do not care.

Embodiment 8 FIG.
Further, the correction method described in the first to sixth embodiments can also be applied to a configuration in which the three-phase inverter 1 is used as a single-phase inverter for a single-phase load. FIG. 43 shows a case where the load 103 is a single-phase load. Here, the three-phase inverter 1 is changed to a single-phase inverter 100 and a single-phase inverter 102 is used. The single-phase inverter 100 may be any one of the two-level full-bridge inverter in FIG. 44, the two-level half-bridge inverter in FIG. 45, the three-level full-bridge inverter in FIG. 46, the three-level half-bridge inverter in FIG. The single-phase inverter 102 may be any circuit described in the first to sixth embodiments. The correction method may be any method described in the first to sixth embodiments. For example, if it is the same method as Embodiment 2, it will become a structure like FIG. FIG. 48 shows a configuration in which the previous FIG. 17 is made to correspond to a single-phase power conversion device. Since it is a single phase, the zero-phase voltage operation circuit 32 is omitted. Other Embodiments 1 and 3 to 5 can be easily adapted to a single-phase power converter. Thus, even if it is a single phase power converter device, the effect similar to Embodiment 1-6 is acquired.

Embodiment 9 FIG.
Moreover, although previous Embodiment 1-6 demonstrated the use as an inverter which converts direct-current power into alternating current power and supplies it to a load, an alternating current power system was connected instead of load, and alternating current power was supplied. It can also be used as a converter for converting to DC power.

It is a figure which shows the whole structure of the power converter device in Embodiment 1 of this invention. It is a figure which shows the internal structure of the three-phase inverter 1 of FIG. It is a figure which shows the internal structure of the single phase inverter 2 of FIG. It is a figure which shows the whole structure of the conventional power converter device assumed for convenience of description of this invention. FIG. 5 is a diagram showing an internal configuration of a drive signal generation circuit 5 in FIG. 4. It is a figure explaining the voltage command and output voltage in the power converter device of FIG. It is a figure explaining the operation | movement in a general 2 level inverter. It is a figure explaining the current pathway in the three-phase inverter 1 of FIG. It is a figure explaining the current pathway in the single phase inverter 2 of FIG. It is a figure explaining operation | movement of the power converter device of FIG. It is a figure which shows the voltage command and output voltage in the conventional power converter device, and illustrates the conventional problem. It is a figure explaining the condition of the load voltage when the output voltage of a power converter device changes sharply. It is a figure which shows the internal structure of 5 A of drive signal generation circuits of FIG. It is a figure explaining the point which correct | amends a drive signal in Embodiment 1 of this invention. It is a figure explaining the point which correct | amends a drive signal in Embodiment 1 of this invention. It is a figure which shows the whole structure of the power converter device in Embodiment 2 of this invention. It is a figure which shows the internal structure of the drive signal generation circuit 5B of FIG. It is a figure which shows the internal structure of the load control circuit 52 of FIG. It is a figure explaining the point which correct | amends a drive signal in Embodiment 2 of this invention. It is a figure explaining the point which correct | amends a drive signal in Embodiment 2 of this invention. It is a figure which shows the whole structure of the power converter device in Embodiment 3 of this invention. It is a figure which shows the internal structure of the three-phase inverter 1 in Embodiment 4 of this invention. It is a figure explaining the current pathway in the three-phase inverter 1 of FIG. It is a figure explaining the current pathway in the three-phase inverter 1 of FIG. It is a figure explaining the current pathway in the three-phase inverter 1 of FIG. It is a figure which shows the internal structure of the single phase inverter 2 in Embodiment 5 of this invention. It is a figure explaining the current pathway in the single phase inverter 2 of FIG. It is a figure which shows the internal structure of the single phase inverter 2 in Embodiment 6 of this invention. It is a figure explaining the current pathway in the single phase inverter 2 of FIG. It is a figure explaining the current pathway in the single phase inverter 2 of FIG. It is a figure explaining the current pathway in the single phase inverter 2 of FIG. It is a figure explaining the current pathway in the single phase inverter 2 of FIG. It is a figure explaining the current pathway in the single phase inverter 2 of FIG. It is a figure explaining the current pathway in the single phase inverter 2 of FIG. It is a figure explaining the current pathway in the single phase inverter 2 of FIG. It is a figure explaining the current pathway in the single phase inverter 2 of FIG. It is a figure explaining the current pathway in the single phase inverter 2 of FIG. It is a figure explaining the operation | movement when not correct | amending the drive signal assumed for convenience of description of Embodiment 6 of this invention. It is a figure explaining the point which correct | amends a drive signal in Embodiment 6 of this invention. It is a figure explaining the point which correct | amends a drive signal in Embodiment 6 of this invention. It is a figure which shows the whole structure of the power converter device in Embodiment 7 of this invention. FIG. 42 is a diagram showing an internal configuration of a drive signal generation circuit 82 of FIG. 41. It is a figure which shows the whole structure of the power converter device in Embodiment 8 of this invention. FIG. 44 is a diagram illustrating an example of an internal configuration of the single-phase inverter 100 of FIG. 43. FIG. 44 is a diagram illustrating an example of an internal configuration of the single-phase inverter 100 of FIG. 43. FIG. 44 is a diagram illustrating an example of an internal configuration of the single-phase inverter 100 of FIG. 43. FIG. 44 is a diagram illustrating an example of an internal configuration of the single-phase inverter 100 of FIG. 43. FIG. 44 is a diagram illustrating an internal configuration of a drive signal generation circuit 105 in FIG. 43.

Explanation of symbols

1 three-phase inverter, 2, 80, 81, 100, 102 single-phase inverter, 3 loads, 4, 4A, 52 load control circuit, 5, 5A, 5B drive signal generation circuit,
6, 7, 83, 84 Gate drive circuit,
11, 14a, 14b, 20, 21a, 21b, 27a, 27b capacitors,
12a-12f, 16a-16l, 18a-18d, 22a, 22b, 24a-24h switching elements,
30 3-phase inverter PWM circuit,
33, 90, 110, 112 Single-phase inverter PWM circuit, 40, 104 current sensor, 41, 43 to 45, 91, 92, 113, 114 pulse correction circuit,
46 PWM pattern storage circuit,
70, 71, 93, 94, 115, 116 Td generation circuit.

Claims (5)

A power conversion device in which the alternating current sides of the first and second power converters that perform power conversion between direct current and alternating current by controlling on and off of the switching elements are connected in series,
Power conversion comprising a drive signal generation circuit for creating a first drive signal for driving the switching element of the first power converter and a second drive signal for driving the switching element of the second power converter In the device
In order to decrease or increase the AC output voltage of the second power converter at the timing of increasing or decreasing the AC output voltage of the first power converter, the first and second drive signals created as the first and second drive signals are generated. The voltage change timing at which the AC output voltage of the first power converter actually increases or decreases and the AC output voltage of the second power converter actually decreases or increases with respect to the first and second command drive signals. Drive signal correcting means for correcting the first and second command drive signals and outputting the first and second corrected drive signals so that the voltage change timing to be the same synchronous voltage change timing ,
The drive signal generation circuit creates the first drive signal by PWM (pulse width modulation) control based on the AC voltage command, and calculates a deviation between the AC voltage command and the AC output voltage of the first power converter. The second drive signal is created by PWM control based on a certain deviation command,
A lead time setting circuit for advancing the AC voltage command for a predetermined time;
The drive signal correction means includes a short-circuit prevention time set in the first and second power converters, and an on / off operation output from an on / off drive signal input to the switching elements of the first and second power converters. The voltage change timing based on the first and second command drive signals is coincident with the synchronous voltage change timing based on the on / off delay time until and the direction of the AC side current of the first and second power converters Thus, the first and second correction drive signals are obtained by delaying the first and second command drive signals by a predetermined correction time amount . The first power converter is a three-phase inverter that converts a DC voltage of the first DC voltage source into a three-phase AC voltage, and the second power converter is a DC of the second DC voltage source. A single-phase inverter that converts a voltage into a single-phase AC voltage, wherein each phase AC side of the three-phase inverter and the AC side of the single-phase inverter are connected in series to a three-phase AC load. The power conversion device according to claim 1 . 3. The power converter according to claim 2, wherein the single-phase inverter is composed of a plurality of single-phase inverters whose AC sides are connected in series with each other . The first power converter is a first single-phase inverter that converts a DC voltage of a first DC voltage source into a single-phase AC voltage, and the second power converter includes a second DC voltage. A second single-phase inverter that converts a DC voltage of the source into a single-phase AC voltage, wherein the AC side of the first single-phase inverter and the AC side of the second single-phase inverter are connected in series. The power converter according to claim 1, wherein the power converter is connected to an AC load . 2. The first and second converters according to claim 1, wherein the first and second power converters are first and second converters that convert an AC voltage of an AC power source connected to an AC side thereof into a DC voltage. Power conversion device.

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