JP7051600B2 - Multi-stage transducer control device - Google Patents

Description

An embodiment of the present invention relates to a control device for a multi-stage converter.

As a large-capacity method of a semiconductor power converter represented by an inverter, there is a method of connecting a plurality of power converter outputs in series to obtain a high voltage. This is called a multi-stage converter or MMC (Modular Multilevel Converter), and is mainly applied to large-capacity converters such as grid interconnection converters and motor drive converters.

The multi-stage converter has a feature that a plurality of levels of voltage output can be obtained by a circuit configuration in which the outputs of unit converters having DC power supplies such as capacitors and rectifiers are connected in multiple series. From such a feature, a voltage output of a plurality of steps can be obtained, and an output close to a sine wave can be directly obtained. As the number of converter stages increases, the number of steps increases. Therefore, if the number of converter stages is large, one-pulse drive that drives each switching element at the output voltage fundamental frequency without high-speed switching such as PWM, produces less distortion. The voltage is obtained. In one-pulse drive, the switching frequency can be suppressed as compared with PWM, so the switching loss that occurs every switching can be reduced, and the effect of reducing the converter loss and the cooler can be expected.

In order to operate the multi-stage converter, it is possible to operate the unit power converter by performing PWM modulation by triangular wave carrier comparison, etc. in the same way as a single converter, but when performing one-pulse modulation, it operates by conventional carrier comparison. It is difficult to make it. Therefore, Non-Patent Document 1 proposes a one-pulse modulation method for a multi-series converter using an H-bridge as a unit converter.

In this method, the output voltage command of the multi-stage converter is compared with the threshold value having the same number of voltage steps as the number of converter stages for positive and negative, and one pulse is obtained by switching each converter at the point where the command and the threshold value intersect. This is a method that realizes modulation. One-pulse control can be easily implemented because of the simple configuration that compares the command and the threshold value.

Hiroshi Koyama, Ryuta Hasegawa, Takuro Arai "1 Pulse Control of Delta Connection Modular Multi-Level STATCOM", Institute of Electrical Engineers of Japan D, Vol.137 No. 3 pp.246-255 (2017)

However, since the number of converter stages that output voltage changes according to the magnitude of the output voltage command, the number of converter stages that output voltage decreases when the output voltage is small, and the converter utilization rate decreases. Further, since the converter that does not output the voltage is in a bypass state without switching, the low-order harmonics may increase as the number of output stages decreases in the region where the output voltage is small, and the voltage distortion may increase.

An embodiment of the present invention has been made in view of the above circumstances, and provides a control device for a multi-stage converter capable of realizing a one-pulse drive that suppresses the generation of harmonics and reduces voltage distortion.

The control device of the multi-stage converter according to the embodiment controls a multi-stage converter in which a plurality of unit converters including a DC power supply and a positive leg and a negative leg connected in parallel with the DC power supply are connected in series. A control device, which is a modulation factor calculation unit that calculates a modulation factor using the output voltage command of the multi-stage converter and the voltage of the DC power supply, and a plurality of unit converters based on the modulation factor. A phase shift amount generator that generates a phase shift amount of a gate signal that drives the upper arm of the positive leg and the upper arm of the negative leg, and a signal that drives a plurality of the unit converters at the output voltage fundamental frequency. Therefore, the on-pulse width and the off-pulse width are the same, and the center of the on-pulse width is the first gate signal whose phase shift amount is advanced with respect to the phase of the output voltage command or the third gate signal whose phase shift amount is delayed. , The center of the off-pulse width generates a second gate signal whose phase shift amount is delayed with respect to the phase of the output voltage command, or a fourth gate signal whose phase shift amount is advanced, and the first gate signal is used as a plurality of the above. The gate signal of the upper arm of the positive leg of the unit converter and the second gate signal are the gate signal of the upper arm of the negative leg of the plurality of unit converters, or the third gate signal. Is the gate signal of the upper arm of the positive leg of the unit converter, and the fourth gate signal is the gate signal of the negative leg of the unit converter. When the modulation factor is changed, the gate signal generation unit has a different value between the gate signal corresponding to the modulation factor before the change and the gate signal corresponding to the modulation factor after the change. When it is determined that the level of the gate signal corresponding to the modulation factor after the change changes during the period before the level of the gate signal corresponding to the modulation factor before the change changes from the present time, after the change. The modulation factor is changed after the level of the gate signal corresponding to the modulation factor of the above and the gate signal corresponding to the modulation factor before the change become the same level.

FIG. 1 is a diagram schematically showing a control device for the multi-stage converter of the first embodiment. FIG. 2 is a diagram showing an example of the relationship between the modulation factor and the phase shift amount. FIG. 3 is a diagram showing another example of the relationship between the modulation factor and the phase shift amount. FIG. 4 is a diagram showing an example of a gate signal and an output voltage for driving the multi-stage converter shown in FIG. FIG. 5 is a diagram showing an example of a gate signal waveform when the modulation factor of the multi-stage converter is changed. FIG. 6 is a diagram showing an example of a gate signal corresponding to the modulation factor before the change, a gate signal corresponding to the modulation factor after the change, and a gate signal when the modulation factor is changed at a predetermined timing. FIG. 7 is a diagram showing other examples of a gate signal corresponding to the modulation factor before the change, a gate signal corresponding to the modulation factor after the change, and a gate signal when the modulation factor is changed at a predetermined timing. be. FIG. 8 is a flowchart for explaining an example of an operation of determining the timing for changing the modulation factor in the control device of the multi-stage converter of the present embodiment. FIG. 9 is a diagram illustrating an example of the operation of the control device of the multi-stage converter of the present embodiment. FIG. 10 is a diagram for explaining an example of the operation of the control device of the multi-stage converter of the second embodiment. FIG. 11 is a diagram for explaining an example of an operation of compensating for an error voltage in the control device of the multi-stage converter of the second embodiment.

Hereinafter, the control device of the multi-stage converter of the embodiment will be described with reference to the drawings.
FIG. 1 is a diagram schematically showing a control device for the multi-stage converter of the first embodiment.

The control device of the present embodiment is a control device that controls the operation of the multi-stage converter 1 using, for example, an H bridge composed of four arms as a unit converter.
The multi-stage converter 1 includes two output terminals. In the following description, one output terminal of the multi-stage converter 1 is referred to as a positive output terminal TP, and the other output terminal is referred to as a negative output terminal TN.

The multi-stage converter 1 includes a plurality of unit converters 11 to 14. Each of the unit converters 11 to 14 is an H-bridge circuit in which a positive leg LP having an upper arm S1 and a lower arm S2 and a negative leg LN having an upper arm S3 and a lower arm S4 are connected in parallel. Is.

The multi-stage converter 1 is located between the output terminal located between the upper arm S1 and the lower arm S2 of the positive leg LP of the unit converters 11 to 14 and the upper arm S3 and the lower arm S4 of the negative leg LN. The output terminal is connected in series between the unit converters 11 to 14. The multi-stage converter 1 may have a configuration in which at least two stages of unit converters are connected in series, and it is not necessary to set an upper limit on the number of stages.

In the following explanation, in a multi-stage converter in which N unit converters are connected in series, the unit converter connected to the positive output terminal is used as the first-stage unit converter, and the unit conversion connected to the negative output terminal is used. The unit is referred to as an N-stage unit converter, and is referred to as a first-stage, second-stage, ... N-stage in the order in which N unit converters connected in series are arranged. In the example shown in FIG. 1, the multi-stage converter includes four unit converters 11 to 14, and the unit converter 11 connected to the positive output terminal TP is the first stage, and the unit is connected to the negative output terminal TN. The converter 14 is the fourth stage, the unit converter 12 is the second stage, and the unit converter 13 is the third stage in the order in which the four unit converters 11 to 14 connected in series are arranged.

The unit converters 11 to 14 have the same configuration. Each of the unit converters 11 to 14 includes a positive leg LP, a negative leg LN, a DC power supply PS, a voltage sensor SV, and a current sensor (not shown).

The voltage sensor SV detects the voltage of the DC power supply PS and outputs the detected value to the control device 2.
The current sensor outputs the detected value of the output current of the multi-stage converter 1 (or the detected value of the output current of any of the plurality of unit converters 11 to 14) to the control device 2.

In each of the plurality of unit converters 11 to 14, the leg connected to the positive output terminal TP of the multistage converter 1 or the unit converter on the positive side of itself is referred to as the positive leg LP, and the negative output terminal TN or itself is used. The leg connected to the negative unit converter is defined as the negative leg LN. The positive leg LP and the negative leg LN are connected in parallel with a capacitor which is a DC power supply PS.

In each of the plurality of unit converters 11 to 14, each of the four arms (two upper arms S1, S3 and two lower arms S2, S4) is an IGBT (Insulated Gate Bipolar Transistor) or MOSFET (semiconductor). It is equipped with a semiconductor switching element in which diodes are connected in antiparallel to a semiconductor element such as a metal-oxide semiconductor field-effect transistor, or a MOSFET (metal-oxide semiconductor field-effect transistor).

In each of the positive leg LP and the negative leg LN of the unit converters 11 to 14, the semiconductor switching elements of the upper arms S1 and S3 and the lower arms S2 and S4 perform inversion operations, respectively, and the semiconductor switching of the upper arms S1 and S3 is performed. When the element is on, the semiconductor switching elements of the lower arms S2 and S4 are turned off. However, in order to prevent a short circuit between the upper arms S1, S3 and the lower arms S2, S4, when a dead time period for turning off both the semiconductor switching elements of the upper arms S1, S3 and the lower arms S2, S4 is provided. A dead time period is provided so that the semiconductor switching elements of the upper arms S1 and S3 and the lower arms S2 and S4 are turned off at the same time.

The configuration of the multi-stage converter 1 is not limited to that shown in FIG. For example, an energy storage element such as a storage battery may be connected to the DC unit of the unit converter instead of the capacitor. Further, the DC portion of the unit converters 11 to 14 may be connected to the AC power supply and the transformer via the rectifier. It is also possible to make a three-phase output by making three sets of multi-stage converter outputs star connection, delta connection, or V connection.

The control device 2 includes a modulation factor calculation unit 21, a phase shift amount generation unit 22, and a gate signal generation unit 23.

In the present embodiment, the control device 2 operates the multi-stage converter 1 by one-pulse drive. In the one-pulse drive, the semiconductor switching elements of the unit converters 11 to 14 are driven at the output voltage fundamental wave frequency. Since the switching frequency can be suppressed in the one-pulse drive as compared with the PWM drive, the loss generated during switching can be reduced, and the effect of reducing the converter loss and the cooler can be expected.

The control device 2 drives the legs LPs and LNs of the unit converters 11 to 14 with switching pulses (gate signals) having the same time width between on and off (Duty 50%), and sets the phase of the gate signal. Adjust the output voltage by adjusting with the leg. At this time, the phase adjustment amount (phase shift amount) is the center of the on-pulse width of the gate signal of the upper arm S1 of the positive leg LP and the center of the off-pulse width of the gate signal of the upper arm S3 of the negative leg LN, respectively. , Perform a phase operation so that the lead / lag with respect to the output voltage has the same phase amount.

The modulation factor calculation unit 21 calculates the modulation factor M using the voltage _VDC of the DC power supply PS of the unit converters 11 to 14 and the voltage command value V ^* . The modulation factor M calculated by the modulation factor calculation unit 21 is input to the phase shift amount generation unit 22. The modulation factor calculation unit 21 calculates the modulation factor M using, for example, the equation (4) described later.

The phase shift amount generation unit 22 outputs the phase shift amount of each leg LP and LN of the unit converters 11 to 14 corresponding to the input modulation factor M. Since the positive leg LP and the negative leg LN exist for the number of stages of the unit converters 11 to 14, the lead / lag phase operation amount (phase shift amount) is required for the number of converter stages. In the example shown in FIG. 1, since the number of stages of the unit converter is four, the phase shift amount generation unit 22 outputs four phase shift amounts α ₁ to α ₄ .

The relationship between the phase shift amount α _n and the fundamental wave amplitude of the output voltage of the multi-stage converter when the lead / delay is evenly shifted is shown in the following equation. However, the _VDC is the voltage value of the DC power supply PS of each of the unit converters 11 to 14, and in this embodiment, it is assumed that the plurality of DC power supply voltages _VDC are equal. Note that N is the number of stages of the unit converter constituting the multi-stage converter.

The fundamental wave v ₁ is defined by the following equation. In the following equation (2), ω is the output voltage angular frequency.
v ₁ = V ₁ cosωt (2)
From the above equation (1), the fundamental wave amplitude amount in the case of the four-stage configuration shown in FIG. 1 is expressed by the following equation (3).

ｋ次の高調波電圧は以下式で求められる。

Here, the ratio of the sum of the DC power supply voltage _VDC of _each stage and the output fundamental wave amplitude V1 is defined as the modulation factor M as shown in the following equation (4).

The harmonic voltage of the kth order is calculated by the following equation.

The phase shift amount generation unit 22 uses the harmonic voltage of the kth order obtained by the above equation (5) to combine the phase shift amounts α ₁ to α ₄ that satisfy the desired output fundamental wave amplitude V ₁ as a constraint condition. From among these, the phase shift amounts α ₁ to α ₄ can be selected using a predetermined evaluation function. The evaluation function used here is, for example, an evaluation function that minimizes the total harmonic voltage or the specific harmonic voltage, and minimizes the total harmonic current or the specific harmonic current based on the current calculated from the voltage. An evaluation function or the like can be adopted.

FIG. 2 is a diagram showing an example of the relationship between the modulation factor and the phase shift amount. Here, it is assumed that the phase shift amounts α ₁ to α ₄ are α ₁ <α ₂ <α ₃ <α ₄ .
From the above equations (3) to (5), it can be seen that there are innumerable combinations of phase shift amounts α ₁ to α ₄ for obtaining a desired modulation factor M (or output voltage). For example, the relationship between the modulation factor M and the phase shift amounts α ₁ to α ₄ in FIG. 2 is a harmonic from a plurality of combinations of the phase shift amounts α ₁ to α ₄ that satisfy the modulation factor M as a constraint condition. This is an example of calculating the phase shift amounts α ₁ to α ₄ that minimizes the total sum of currents (for example, the sum of 3rd to 39th harmonics). It is also possible to calculate the phase shift amounts α ₁ to α ₄ from the solutions of the nonlinear simultaneous equations. In the present embodiment, the phase shift amounts α ₁ to α ₄ are in a range larger than zero and less than 180 °.

Further, the phase shift amount generation unit 22 can generate the phase shift amount of the number of stages of the unit converter by a simultaneous equation using the equation of the number of phase shift amounts to be generated (the number of stages of the multi-stage converter).

In the present embodiment, the phase shift amount generation unit 22 uses, for example, a phase shift by a simultaneous equation of a fundamental wave amplitude equation and three other harmonic amplitude equations (= the number of stages of the multi-stage converter-1). The quantities α ₁ to α ₄ can be calculated.

FIG. 3 is a diagram showing another example of the relationship between the modulation factor and the phase shift amount. Here, it is assumed that the phase shift amounts α ₁ to α ₄ are α ₁ <α ₂ <α ₃ <α ₄ .
Here, for example, as shown in the following equation, the calculation is performed by the following simultaneous equations using equations in which the fundamental wave amplitude, the third harmonic amplitude, the fifth harmonic amplitude, and the seventh harmonic amplitude are set to zero, respectively. An example of four phase shift amounts α ₁ to α ₄ is shown.

The phase shift amount generation unit 22 uses, for example, a table of phase shift amounts α ₁ to α ₄ corresponding to the modulation factor M by using the phase shift amounts α ₁ to α ₄ calculated in advance as described above. You may.

FIG. 4 is a diagram showing an example of a gate signal and an output voltage for driving the multi-stage converter shown in FIG.
The gate signal generation unit 23 receives the phase shift amounts α ₁ to α ₄ from the phase shift amount generation unit 22, and supplies the gate signals of the upper arm S1 of the positive leg LP to the four unit converters 11 to 14 (the gate signal of the upper arm S1 of the positive leg LP. The first gate signal) S _pα1 to S _pα4 and the gate signal (second gate signal) S _nα1 to S _nα4 of the upper arm S3 of the negative leg LN are generated. In the present embodiment, the on time and the off time of the gate signal are equal (Duty is 50%), and the phase is 180 °.

For example, the gate signal generation unit 23 sets the center of the off-pulse width in the time axis direction of the gate signal (second gate signal) _Snα1 to _Snα4 of the upper arm S3 of the negative leg LN from the phase of the voltage command (position at 0 °). Also delays the phase of the phase shift amount α ₁ to α ₄ , and the phase of the voltage command is centered on the on-pulse width in the time axis direction of the gate signal (first gate signal) S _pα 1 to _Sp α 4 of the upper arm S1 of the positive leg LP. The phase of the phase shift amount α ₁ to α ₄ is advanced from (the position of 0 °).

As described above, the gate signal generation unit 23 adjusts the phases of the phase shift amounts α ₁ to α ₄ with reference to the phase of the voltage command, and outputs four gate signals of the upper arm S1 of the positive leg LP to the negative leg. Generates four gate signals for the upper arm S3 of the LN. The gate signal generation unit 23 inverts the gate signal of the upper arm S1 of the positive leg LP to generate the gate signal of the lower arm S2, and inverts the gate signal of the upper arm S3 of the negative leg LN to invert the gate of the lower arm S4. Generate a signal.

In the present embodiment, the gate signal _Spα1 is a signal obtained by shifting (advancing) the center of the on-pulse width of the gate signal by a _phase shift amount α1; and the gate signal _Spα2 is the center of the on-pulse width of the gate signal. Is a signal shifted (advanced) by the phase shift amount α ₂ and the gate signal S _pα3 is a signal obtained by shifting (advancing) the center of the on-pulse width of the gate signal by the phase shift amount α ₃ and the gate signal S. _pα4 is a signal obtained by shifting ₍ advancing) the center of the on-pulse width of the gate signal by a phase shift amount α4.

Further, the gate signal S _nα1 is a signal in which the center of the off-pulse width of the gate signal is shifted ₍ delayed) by a _phase shift amount _α1 ; It is a shifted (delayed) signal, the gate signal S _nα3 is a signal in which the center of the off-pulse width of the gate signal is shifted (delayed) by a phase shift amount α3 _, and the gate signal _Snα4 is the off-pulse width of the gate signal. This is a signal in which the center of the signal is shifted ₍ delayed) by the phase shift amount α4.

The gate signal generation unit 23 converts a plurality of units so that gate signals having an inverted relationship with each other are supplied to the upper arms S1 and S3 and the lower arms S2 and S4 in each of the positive leg LP and the negative leg LN. The generated gate signal is output to the vessels 11 to 14.

In the present embodiment, the gate signal generation unit 23 may assign the gate signals _Spα1 to _Spα4 to any of the positive leg LPs of the unit converters 11 to 14, and the gate of the upper arm S3 of the negative leg LN. The signals S _nα1 to Snα4 may be assigned to any of the negative leg _LNs of the unit converters 11-14.

According to the control device of the multi-stage converter of the present embodiment, the leg LPs and LNs of all the unit converters 11 to 14 are switched even when the modulation factor of the multi-stage converter 1 is low. Further, even if the unit converters 11 to 14 of each stage are operated by one-pulse drive, the total output voltage of the multi-stage converter 1 becomes a waveform like PWM modulation in a pseudo manner, and the generation of low-order harmonics can be suppressed. ..

Further, by defining the phase shift amount of the gate signal as described above, as shown in FIG. 3, the leg LPs of all the unit converters 11 to 14 are in the timing of zero output voltage and the time domain before and after that. , The upper arms S1 and S3 of the LN are turned on, or all the upper arms S1 and S3 are turned off.

For example, when one-pulse drive is performed, if the center of the off-pulse width and the center of the on-pulse width of the gate signal having a duty ratio of 50% do not lag or advance from the voltage command (when the phase shift amount is zero), the gate signal is a voltage. The phase of the command will be switched at the timing of 90 ° and −90 °.

On the other hand, in the present embodiment, the center of the off-pulse width of the gate signal of the upper arm S3 of the negative leg LN is delayed from the voltage command, and the center of the on-pulse width of the gate signal of the upper arm S1 of the positive leg LP is advanced from the voltage command. No. As a result, the extinguishing timing of the gate signal of the upper arm S3 of the negative leg LN becomes -90 ° from the center of the off width, and the upper arm of all negative leg LNs before the phase of the voltage command reaches -90 °. S3 turns off. Further, the ignition timing of the gate signal of the upper arm S3 of the negative leg LN is at a point of + 90 ° from the center of the off pulse width, and all the upper arms S3 of the negative leg LN are turned on before the phase of the voltage command reaches 90 °. do.

On the other hand, when the phase shift amount is zero, the firing timing of the gate signal of the upper arm S1 of the positive leg LP is at a point −90 ° from the center of the on-pulse width. On the other hand, in the present embodiment, since the center of the on-pulse width of the gate signal of the upper arm S1 of the positive leg LP is advanced from the position of 0 ° of the voltage command, the gate signal of the upper arm S1 of the positive leg LP is a voltage command. The upper arm S1 of all positive leg LPs turns on at the point where the phase of is -90 ° or later. Further, the arc extinguishing timing of the gate signal of the upper arm S1 of the positive leg LP is at a point of + 90 ° from the center of the on-pulse width, and all the upper arms S1 of the positive leg LP are turned off at the point where the phase of the voltage command is 90 ° or later. do.

From the above, all the upper arms S1 and S3 are in the turn-off state at the timing when the phase of the voltage command is −90 °, and all the upper arms S and S3 are turned on at the timing when the phase of the voltage command is + 90 °. At the timing when the output voltage of the multi-stage converter 1 becomes zero, the output voltages of all the unit converters 11 to 14 also become zero.

The timing at which the output voltage becomes zero exists twice, −90 ° and + 90 °, in each cycle of the output voltage. At this timing, the switching states of all leg LPs and LNs of all unit converters 11 to 14 are the same. Therefore, for example, in the positive leg LP or in the negative leg LN between the plurality of unit converters 11 to 14. It is possible to replace the gate signal with. That is, at the timing when the output voltage becomes zero, the switching state is the same for all legs, so even if the gate signal is switched, the switching state does not change before and after, and the gate signal can be replaced without affecting the output voltage. It will be possible. In addition, it can be replaced twice every cycle.

Next, in the control device 2 of the multi-stage converter 1, an example of the operation of the control device 2 when changing the phase of the gate signal in response to a change in the output voltage command V ^* of the multi-stage converter 1 will be described. ..

In the present embodiment, the control device 2 has a gate signal currently driving the unit converters 11 to 14 when the output voltage command of the multi-stage converter 1 changes, that is, when the modulation factor changes, and after the change. The timing for changing the modulation factor of the multi-stage converter 1 is determined based on the comparison result by comparing with the gate signal obtained by the modulation factor of.

FIG. 5 is a diagram showing an example of a gate signal waveform when the modulation factor of the multi-stage converter is changed.
For example, focusing on the gate signal that drives the unit converter 11 in the first stage of the example shown in FIG. 5, by changing the modulation factor, 2 in one cycle of the gate signal that drives the upper arm S3 of the negative leg LN. Two pulses are occurring.

Focusing on the gate signal that drives the unit converter 12 in the second stage of the example shown in FIG. 5, by changing the modulation factor, 2 in one cycle of the gate signal that drives the upper arm S1 of the positive leg LP. Two pulses are occurring.

As in this example, when two pulses are generated in one cycle, the number of switchings in one cycle increases, multiple switchings must be performed in a short period of time, and the switching frequency may temporarily increase. rice field. Further, if the number of switchings in one cycle is increased, the switching loss in the unit converter becomes large.

FIG. 6 is a diagram showing an example of a gate signal corresponding to the modulation factor before the change, a gate signal corresponding to the modulation factor after the change, and a gate signal when the modulation factor is changed at a predetermined timing.
Here, the gate signal A corresponding to the modulation factor before the change and the gate signal B corresponding to the modulation factor after the change are shown.

At a predetermined change timing, the gate signal A is at a high level, the gate signal B is at a low level, and the gate signal after changing the modulation factor changes from high level to low level. The gate signal after the modulation factor change becomes high level at the timing when the gate signal B becomes high level, and then has the same waveform as the gate signal B.

In this example, the level of the gate signal B changes after the predetermined change timing and before the level of the gate signal A changes. As a result, two pulses are generated in one cycle in the gate signal after the modulation factor is changed.

FIG. 7 is a diagram showing other examples of a gate signal corresponding to the modulation factor before the change, a gate signal corresponding to the modulation factor after the change, and a gate signal when the modulation factor is changed at a predetermined timing. be.
Here, the gate signal A corresponding to the modulation factor before the change and the gate signal B corresponding to the modulation factor after the change are shown.

In this example, at a predetermined change timing, the gate signal A is low level, the gate signal B is high level, and the gate signal after changing the modulation factor changes from low level to high level. The gate signal after the modulation factor change becomes low level at the timing when the gate signal B becomes low level, and then has the same waveform as the gate signal B.

Also in this example, the level of the gate signal B changes after the predetermined change timing and before the level of the gate signal A changes. As a result, two pulses are generated in one cycle in the gate signal after the modulation factor is changed.

As shown in FIGS. 6 and 7, the levels of the gate signal A and the gate signal B are different at the timing of changing the modulation factor, and the level of the gate signal A is next from the timing of changing the modulation factor. When the level of the gate signal B changes during the period until the change, two pulses are generated in one cycle of the gate pulse after the modulation factor change.
Therefore, in the present embodiment, the control device 2 determines the timing for changing the modulation factor so that two pulses are not generated in one cycle of the gate pulse.

FIG. 8 is a flowchart for explaining an example of an operation of determining the timing for changing the modulation factor in the control device of the multi-stage converter of the present embodiment.
The gate signal generation unit 23 of the control device 2 determines whether or not the modulation factor has changed based on, for example, the value of the voltage command V ^* (step S1). When the modulation factor has not changed, the above step S1 is repeated.

When it is determined that the modulation factor has changed, the gate signal generation unit 23 corresponds to the gate signal corresponding to the modulation factor before the change and the modulation factor after the change for all the gate signals of the plurality of unit converters 11 to 14. It is determined whether or not the level is different from that of the gate signal to be used (step S2).

If the gate signal levels before and after the change are the same for all the gate signals of the plurality of unit converters 11 to 14, the gate signal generation unit 23 changes the modulation factor and changes the modulation factor. The gate signal corresponding to is output to a plurality of unit converters 11 to 14 (step S4).

If the gate signal levels of the gate signals before and after the change are different for all the gate signals of the plurality of unit converters 11 to 14, the gate signal generation unit 23 is the gate corresponding to the modulation factor before the change from the present time. It is determined whether or not the level of the gate signal corresponding to the changed modulation factor changes during the period until the signal level changes (step S3).

In step S3, before the level of the gate signal corresponding to the modulation factor before the change changes, if the level of the gate signal corresponding to the modulation factor after the change does not change, the gate signal generation unit 23 changes the modulation factor. Then, the gate signal corresponding to the changed modulation factor is output to the plurality of unit converters 11 to 14 (step S4).

In step S3, before the level of the gate signal corresponding to the modulation factor before the change changes, when the level of the gate signal corresponding to the modulation factor after the change changes, the gate signal generation unit 23 returns to step S2. In this case, the gate signal generation unit 23 changes the level of the gate signal corresponding to the modulation factor before the change, and all the gate signals are either steps S2 or S3 before and after the change of the modulation factor. After the N determination is made in, the modulation factor is changed and the gate signal corresponding to the changed modulation factor is output to the plurality of unit converters 11 to 14 (step S4).

FIG. 9 is a diagram illustrating an example of the operation of the control device of the multi-stage converter of the present embodiment. The waveform of the gate signal shown here has the same conditions as those shown in FIG. 5 except for the timing of changing the modulation factor.
In this example, when the gate signal generation unit 23 determines that the modulation factor has changed based on, for example, a voltage command, the procedure shown in FIG. 8 is performed without immediately switching to the gate signal corresponding to the changed modulation factor. The timing for changing the modulation factor is determined based on the result of comparing the gate signal corresponding to the modulation factor before the change and the gate signal corresponding to the modulation factor after the change.

For example, in the example shown in FIG. 5, focusing on the gate signal that drives the unit converter 11 in the first stage, by changing the modulation factor, the gate signal that drives the upper arm S3 of the negative leg LN becomes one cycle. Two pulses are generated, but if the timing of changing the modulation factor is delayed as shown in FIG. 9, two pulses are not generated in one cycle.

Focusing on the gate signal that drives the unit converter 12 in the second stage of the example shown in FIG. 5, by changing the modulation factor, 2 in one cycle of the gate signal that drives the upper arm S1 of the positive leg LP. One pulse is generated, but if the timing of changing the modulation factor is delayed as shown in FIG. 9, two pulses are not generated in one cycle.
As described above, according to the present embodiment, it is possible to provide a control device for a multi-stage converter capable of realizing one-pulse drive that suppresses the generation of harmonics and reduces voltage distortion.

Next, the control device of the multi-stage converter of the second embodiment will be described in detail with reference to the drawings. In the following description, the same components as those in the above-described first embodiment are designated by the same reference numerals and the description thereof will be omitted.

In the present embodiment, the control device 2 has an upper arm in order to prevent the upper arm and the lower arm from conducting at the same time in each of the positive leg LP and the negative leg LN of the plurality of unit converters 11 to 14. There is a dead time when both the lower arm and the lower arm are off.

FIG. 10 is a diagram for explaining an example of the operation of the control device of the multi-stage converter of the second embodiment. Here, an example of the output current and output voltage of the unit converter when a dead time is provided by delaying the ignition timing of the gate signal in any unit converter is shown.
Here, the direction of the current flowing from the unit converter to the load is positive, and the direction of the current flowing from the load to the unit converter is negative.

As shown in FIG. 10, when the current is positive, when the upper arm S1 of the positive leg LP of the unit converter is turned on (when the gate signal ignites), an error voltage ΔV corresponding to the dead time is generated.
Further, when the current is negative, when the upper arm S3 of the negative leg LN of the unit converter turns on (when the gate signal ignites), an error voltage ΔV corresponding to the dead time is also generated.

On the other hand, when the current was negative, no error voltage was generated when the upper arm S1 of the positive leg LP turned on (when the gate signal ignited). Further, when the current was positive and the upper arm S3 of the negative leg LN turned on (when the gate signal ignited), no error voltage was generated.

Therefore, in the present embodiment, the gate signal generation unit 23 of the control device 2 performs a phase shift for obtaining a desired modulation factor for the gate signal that turns on the upper arm of the positive leg LP when the output current direction is positive. The shift amount is added or subtracted from the amount by the amount corresponding to the angle of the dead time time.

Further, the gate signal generation unit 23 of the control device 2 desires a shift amount corresponding to the angle of the dead time time for the gate signal that turns on the upper arm S3 of the negative leg LN when the output current is negative. Add or subtract from the phase shift amount to obtain the modulation factor. This makes it possible to compensate for the error voltage ΔV generated by providing the dead time.

The angle equivalent amount of the dead time time is, for example, when the output voltage frequency is 50 [Hz] and a dead time of 3 [μs] is provided, one cycle of 50 [Hz] is 20 [ms], which is 20. Assuming that [ms] is 360 [°], the amount equivalent to the angle of 3 [μs] is 360 [°] × 3 [us] / 20 [ms] = 0.054 [°].

FIG. 11 is a diagram for explaining an example of an operation of compensating for an error voltage in the control device of the multi-stage converter of the second embodiment.
That is, the gate signal generation unit 23 generates a gate signal using the received phase shift amounts α ₁ to α ₄ , and then performs unit conversion based on the detected value of the output current of the multi-stage converter 1 received from the current sensor. Among the gate signals output to the devices 11 to 14, it is determined whether or not there is a gate signal that turns on the upper arm S1 of the positive leg LP when the output current is positive.

Further, when the output current is negative in the gate signal output to the unit converters 11 to 14, the gate signal generation unit 23 is based on the detection value of the output current of the multi-stage converter 1 received from the current sensor. It is determined whether or not there is a gate signal for turning on the upper arm S3 of the negative leg LN.

When there is a corresponding gate signal, the gate signal generation unit 23 calculates the phase shift amount after voltage compensation by adding or subtracting an amount equivalent to the angle of the dead time time to the phase shift amount of the corresponding gate signal. A gate signal whose phase is shifted by the phase shift amount after voltage compensation is generated, and the gate signal is output to a plurality of unit converters 11 to 14.
Since the amount equivalent to the angle of the dead time time is a relative amount, it may be added or subtracted from the phase shift amount according to the definition of the sign for the phase advance and the phase delay. For example, in the case of the polarity in the example shown in FIG. 11, only the selection is made whether to subtract the amount equivalent to the angle of the dead time with respect to the phase shift amount or not, and the angle of the dead time with respect to the phase shift amount. No equivalent amount is added.

In the example shown in FIG. 11, two of the four gate signals driving the upper arm S1 of the positive leg LP are turned on when the output current of the multistage converter 1 is positive, and the gate signal generation unit 23 is used. , The angle equivalent amount of the dead time time is subtracted from the phase shift amount of these gate signals to generate a gate signal whose phase is shifted by the phase shift amount after voltage compensation, and a plurality of unit converters 11 to 14 are generated. Outputs a gate signal.

As described above, according to the present embodiment, it is possible to compensate for the error of the output voltage due to the dead time, and it is possible to realize one-pulse drive that suppresses the generation of harmonics and reduces the voltage distortion. It is possible to provide a control device for a multi-stage converter.

Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other embodiments, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are also included in the scope of the invention described in the claims and the equivalent scope thereof.

For example, in the above-described embodiment, the gate signal generation unit 23 uses the center of the off-pulse width in the time axis direction of the gate signals _Snα1 to _Snα4 of the upper arm S3 of the negative leg LN as the phase of the voltage command (position at 0 °). The phase of the on-pulse width in the time axis direction of the gate signal _Spα1 to _Spα4 of the upper arm S1 of the positive leg LP is set at the center of the on _- pulse width in the time axis direction by delaying the phase of the _phase shift amount α1 to α4. ), It is assumed that the phase of the phase shift amount α ₁ to α ₄ is advanced.

For example, the gate signal generation unit 23 shifts the center of the off-pulse width in the time axis direction of the gate signal (fourth gate signal) of the upper arm S3 of the negative leg LN from the phase of the voltage command (position at 0 °). By advancing the phase of the quantities α ₁ to α ₄ , the center of the on-pulse width in the time axis direction of the gate signal (third gate signal) of the upper arm S1 of the positive leg LP is from the phase of the voltage command (position at 0 °). Also, the phase of the phase shift amounts α ₁ to α ₄ may be delayed to generate a gate signal.

In this case as well, the gate signal generation unit 23 adjusts the phases of the phase shift amounts α ₁ to α ₄ with reference to the phase of the voltage command V ^* as described above, and each of the upper arms S1 of the four positive leg LPs. Gate signals S _pα1 to S _pα4 and gate signals S _nα1 to S _nα4 for each of the upper arms S3 of the four negative leg LNs are generated. The gate signal generation unit 23 inverts the gate signal of the upper arm S1 of the positive leg LP to generate the gate signal of the lower arm S2, and inverts the gate signal of the upper arm S3 of the negative leg LN to invert the gate of the lower arm S4. Generate a signal.

The gate signal generation unit 23 converts a plurality of units so that gate signals having an inverted relationship with each other are supplied to the upper arms S1 and S3 and the lower arms S2 and S4 in each of the positive leg LP and the negative leg LN. The generated gate signal is output to the vessels 11 to 14. When the phase shift amounts α ₁ to α ₄ are common, the output of the multi-stage converter 1 is the same in the case shown in FIG. 3 and the case shown in FIG.
Also in the above case, the same effect as that of the first embodiment and the second embodiment can be obtained.

1 ... Multi-stage converter, 2 ... Control device, 11-14 ... Unit converter, 21 ... Modulation rate calculation unit, 22 ... Phase shift amount generation unit, 23 ... Gate signal generation unit, 100 ... Transformer, 200 ... Rectifier, LP ... Positive leg, LN ... Negative leg, S1, S3 ... Upper arm, S2, S4 ... Lower arm, _Snα1 to _Snα4 , _Spα1 to _Spα4 ... Gate signal, α1 to α4 ... Phase shift amount, PS ... DC Power supply, SV ... voltage sensor, TP ... positive output terminal, TN ... negative output terminal, ΔV ... voltage error.

Claims (5)

A control device for controlling a multi-stage converter in which a plurality of unit converters having a DC power supply and a positive leg and a negative leg connected in parallel with the DC power supply are connected in series.
A modulation factor calculation unit that calculates a modulation factor using the output voltage command of the multi-stage converter and the voltage of the DC power supply.
A phase shift amount generation unit that generates a phase shift amount of a gate signal that drives the upper arm of the positive leg and the upper arm of the negative leg of the plurality of unit converters based on the modulation factor.
A signal that drives a plurality of the unit converters at the output voltage fundamental frequency, the on-pulse width and the off-pulse width are the same, and the center of the on-pulse width advances the phase shift amount with respect to the phase of the output voltage command. However, the first gate signal or the third gate signal delayed by the phase shift amount, and the second gate signal whose center of the off-pulse width is delayed by the phase shift amount with respect to the phase of the output voltage command or the phase shift amount advanced. A four-gate signal is generated, the first gate signal is used as the gate signal of the upper arm of the positive leg of the unit converter, and the second gate signal is used as the negative leg of the unit converter. The gate signal of the upper arm, or the third gate signal is the gate signal of the upper arm of the positive leg of the plurality of unit converters, and the fourth gate signal is the gate signal of the plurality of unit converters. A gate signal generation unit for the gate signal of the negative leg of the above.
When the modulation factor is changed, the gate signal generation unit has a value different between the gate signal corresponding to the modulation factor before the change and the gate signal corresponding to the modulation factor after the change. When it is determined that the level of the gate signal corresponding to the modulation factor after the change changes during the period before the level of the gate signal corresponding to the modulation factor before the change changes from the present time, the change A control device for a multi-stage converter that changes the modulation factor after the level of the gate signal corresponding to the modulation factor and the gate signal corresponding to the modulation factor before the change become the same level. A control device for controlling a multi-stage converter in which a plurality of unit converters having a DC power supply and a positive leg and a negative leg connected in parallel with the DC power supply are connected in series.
A modulation factor calculation unit that calculates a modulation factor using the output voltage command of the multi-stage converter and the voltage of the DC power supply.
A phase shift amount generation unit that generates a phase shift amount of a gate signal that drives the upper arm of the positive leg and the upper arm of the negative leg of the plurality of unit converters based on the modulation factor.
A signal that drives a plurality of the unit converters at the output voltage fundamental frequency, the on-pulse width and the off-pulse width are the same, and the center of the on-pulse width advances the phase shift amount with respect to the phase of the output voltage command. However, the first gate signal or the third gate signal delayed by the phase shift amount, and the second gate signal whose center of the off-pulse width is delayed by the phase shift amount with respect to the phase of the output voltage command or the phase shift amount advanced. A four-gate signal is generated, the first gate signal is used as the gate signal of the upper arm of the positive leg of the unit converter, and the second gate signal is used as the negative leg of the unit converter. The gate signal of the upper arm, or the third gate signal is the gate signal of the upper arm of the positive leg of the plurality of unit converters, and the fourth gate signal is the gate signal of the plurality of unit converters. A gate signal generation unit for the gate signal of the negative leg of the above.
The gate signal generation unit is said to have the positive leg when the output current is positive among the gate signals output to the plurality of unit converters based on the detected value of the output current of the multi-stage converter. For the gate signal that turns on the upper arm and the gate signal that turns on the upper arm of the negative leg when the output current is negative, the amount corresponding to the angle of the dead time time is added or subtracted from the phase shift amount. A control device for a multi-stage converter that calculates the phase shift amount after voltage compensation and shifts the phase by the phase shift amount after voltage compensation. The control of the multi-stage converter according to claim 1 or 2, wherein the plurality of phase shift amounts are a combination in which the sum of harmonics of a predetermined order is minimized with the fundamental wave amplitude of the multi-stage converter as a constraint condition. Device. A control device that controls the N-stage unit converter.
The multi-stage converter according to claim 1 or 2, wherein the plurality of phase shift quantities are a combination of a simultaneous equation of a fundamental wave amplitude equation and an equation of N-1 having a harmonic amplitude of zero. Control device. The control device for a multi-stage converter according to any one of claims 1 to 4, wherein the phase shift amount generation unit includes a table in which the values of the phase shift amount with respect to the desired modulation factor are stored.

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