JP2022084042A - Electric power conversion system and control method therefor - Google Patents

Abstract

To provide an electric power conversion system capable of achieving high output voltage distortion rate and high system efficiency.SOLUTION: An electric power conversion system includes: a three-level power converter for outputting a three-level voltage; and a control section for generating a gate signal of the three-level power converter on the basis of synchronous PWM control by comparison between an upper carrier signal carry 1, a lower carrier signal carry 2 and a phase voltage command. The control section generates the upper carrier signal carry 1 and the lower carrier signal carry 2 on the basis of a correction internal phase θm with a sine wave component of six-time frequency of an internal phase θ added.SELECTED DRAWING: Figure 3

Description

The present invention relates to a control method for a power conversion device.

As the DC / three-phase AC converter, a two-level power converter, a three-level power converter, or the like is generally used. The three-level power converter is a device that includes a voltage source of voltage E divided by two and outputs three levels of AC voltage of + E, 0, and −E.

In the vicinity of the zero cross of the phase voltage command given to the three-level power converter, the width of the pulse voltage modulated by PWM becomes narrow, and the pulse voltage may not be output due to the dead time.

As a result, the distortion of the output pulse voltage increases, so measures such as increasing the switching frequency (carrier frequency) to reduce the voltage distortion are taken. However, as the switching frequency increases, the switching loss generally increases, which reduces the efficiency of the device.

In Patent Document 3, the two-phase modulation is improved so that the pulse voltage is not generated at the zero cross of the phase voltage command. By increasing the carrier frequency, it is possible to increase the switching frequency while preventing the generation of an unnecessary thin pulse voltage around the zero cross.

In addition, Patent Document 2 discloses a kind of mode switching method in which the carrier frequency is made variable according to the rotation speed in order to raise the carrier frequency locally. It is considered that it can also be applied to means such as switching the carrier frequency to make it variable near the zero cross of the phase voltage command.

Japanese Unexamined Patent Publication No. 2020-25378 Japanese Unexamined Patent Publication No. 2019-146380 WO2014 / 141398A1

In the three-level power converter as shown in FIG. 1 of Patent Document 1, the width of the pulse voltage modulated by PWM becomes narrow near the zero cross of the phase voltage command value shown in FIG. 2, and the pulse voltage is output due to the dead time. It may not be done. As a result, the distortion of the output voltage increases, so in this region, improvements such as increasing the carrier frequency for performing PWM and making it variable are required.

From the above, it is an issue to provide a power conversion device having an improved output voltage distortion rate and improved device efficiency.

The present invention has been devised in view of the above-mentioned conventional problems, and one aspect thereof is a three-level power converter that outputs a three-level voltage and a sinusoidal wave having an internal phase having a frequency six times that of the internal phase. The upper carrier signal and the lower carrier signal are generated based on the corrected internal phase to which the components are added, and the three-level power is based on the synchronous PWM control by comparing the upper carrier signal, the lower carrier signal and the phase voltage command. It is characterized by having a control unit for generating a gate signal of a converter.

Further, as one aspect thereof, the control unit has a first adder that calculates the correction internal phase by the following equation (4), and a third adder that multiplies the output of the first adder by 1 / 2π. A fourth adder that multiplies the output of the third adder by the number of carriers per cycle, a fifth adder that multiplies the output of the fourth adder by 2, and the output of the fifth adder. A first subtractor for subtracting 1 from the first subtractor, an absolute value calculation unit for calculating the absolute value of the output of the first subtractor, and a second subtractor for subtracting 1 from the output of the absolute value calculation unit. The output of the absolute value calculation unit is used as the upper carrier signal, and the output of the second subtractor is used as the lower carrier signal.

θm: Corrected internal phase ωrat: Frequency of internal phase Ncarry: Number of carriers per cycle Δωcarrymax: Magnitude of maximum deviation of carrier frequency after modulation (upper carrier signal, lower carrier signal) t: Time.

Further, as one aspect thereof, the carrier frequencies of the upper carrier signal and the lower carrier signal are set to the following equation (5).

ωcarry_m: Carrier frequency after modulation (upper carrier signal, lower carrier signal) Ncarry: Number of carriers per cycle θm: Corrected internal phase ωrat: Internal phase frequency t: Time Δωcarrymax: After modulation (upper carrier signal, lower side) The magnitude of the maximum deviation of the carrier frequency of the carrier signal) ωcarry: The carrier frequency of the carrier signal before modulation.

According to the present invention, it is possible to provide a power conversion device having an improved output voltage distortion rate and improved device efficiency.

The figure which shows the relationship between a three-phase phase voltage command using an internal phase θ, and a sine wave of a 6θ component. The block diagram which shows the relationship between the conventional internal phase and the synchronous carrier frequency, and the conventional synchronous carrier signal generation part. The block diagram which shows the relationship between the internal phase of an embodiment and a synchronous carrier frequency, and the synchronous carrier signal generation part of an embodiment.

Hereinafter, embodiments of the power conversion device according to the present invention will be described in detail with reference to FIGS. 1 to 3.

[Embodiment 1]
The power converter of this embodiment includes a three-level power converter and a control unit. The 3-level power converter outputs a 3-level voltage. The control unit generates a gate signal of the three-level power converter based on the synchronous PWM control by comparing the upper carrier signal, the lower carrier signal and the phase voltage command. Here, the synchronous PWM control is performed in a cycle of the power supply cycle.

As a method for generating a gate signal based on the main circuit configuration of the three-level power converter, the upper carrier signal, and the lower carrier signal, for example, the same configuration as in FIGS. 1 and 2 of Patent Document 1 can be considered.

Here, an example of the main circuit configuration of the three-level power converter will be briefly described. The three-level power converter includes a positive-side capacitor (reference numeral 1a in Patent Document 1) and a negative-side capacitor (reference numeral 1b in Patent Document 1) connected in series.

An upper arm switching element (reference numeral 2a in Patent Document 1) and a lower arm switching element (reference numeral 2b in Patent Document 1) are connected in series between one end of the positive side capacitor and the other end of the negative side capacitor. Diode elements are connected in anti-parallel to the upper arm switching element and the lower arm switching element, respectively.

A bidirectional switch (reference numeral 3 in Patent Document 1) is connected between the connection point between the positive side capacitor and the negative side capacitor and the connection point between the upper arm switching element and the lower arm switching element. This bidirectional switch is configured by connecting two semiconductor switching elements in antiparallel. The connection point between the upper arm switching element, the lower arm switching element, and the bidirectional switch is connected to the load via a reactor or the like.

The control unit generates a gate signal input to the gates of two semiconductor switching elements, an upper arm switching element, a lower arm switching element, and a bidirectional switch.

Specifically, the control unit compares the phase voltage command with the upper carrier signal, sets the gate signal of the upper arm switching element to high during the period when the phase voltage command is larger than the upper carrier signal, and sets one semiconductor of the bidirectional switch. The switching element (reference numeral 3a in Patent Document 1) is defined as low. Further, during the period when the phase voltage command is smaller than the upper carrier signal, the gate signal of the upper arm switching element is set to low, and one of the semiconductor switching elements of the bidirectional switch is set to high.

During the period during which one of the semiconductor switching elements of the upper arm switching element and the bidirectional switch is switching (the first half cycle of the phase voltage command), the lower arm switching element is fixed to low and the other of the bidirectional switches. The semiconductor switching element (reference numeral 3b in Patent Document 1) is fixed to high.

Further, the control unit compares the phase voltage command with the lower carrier signal, sets the gate signal of the lower arm switching element to high during the period when the phase voltage command is smaller than the lower carrier signal, and sets the other semiconductor of the bidirectional switch to high. The switching element is low. Further, during the period when the phase voltage command is smaller than the lower carrier signal, the gate signal of the lower arm switching element is set to low, and the other semiconductor switching element of the bidirectional switch is set to high.

During the period during which the lower arm switching element and the other semiconductor switching element of the bidirectional switch are switching (the second half cycle of the phase voltage command), the upper arm switching element is fixed to low and one of the bidirectional switches is used. The semiconductor switching element of is fixed to high.

Although an example of the main circuit configuration of the 3-level power converter and an example of the method of generating the gate signal thereof have been described above, the main circuit of the 3-level power converter may have another configuration, and there are two methods of generating the gate signal. Any other method may be used as long as it is a method of generating a gate signal based on the upper carrier signal and the lower carrier signal.

FIG. 1 shows the internal phase θ in a DC / three-phase AC converter, the three-phase voltage commands sinθ, sin (θ + 3π / 2), sin (θ-3π / 2), and the sine waveform sin6θ with a frequency component of 6 times. show. Utilizing this relationship, the carrier frequency is lowered at the timing of 6f when the phase voltage command peaks, and conversely, the carrier frequency is raised near zero cross and the carrier frequency is modulated so that the average carrier frequency becomes constant.

FIG. 2A shows the relationship between the conventional internal phase θ and the carrier frequency ωcarry synchronized with the internal phase θ. When the frequency (slope) of the internal phase is constant, the carrier frequency ωcarry is constant. The carrier frequency ωcarry is Ncarry (carrier frequency per cycle) times the frequency of the internal phase θ.

FIG. 2B is an example of a block diagram of a conventional synchronous PWM carrier generation unit 1, and the carrier signal is 1p., Which is generally used in a three-level power converter. u. Upper carrier signals in the amplitude range from 0 to 0 carry1 and -1p. u. The lower carrier signal carry2 in the amplitude range from 0 to 0.

FIG. 3A is an explanatory diagram of a carrier signal generated based on a corrected internal phase obtained by adding an internal phase θ and a sine wave component having a frequency 6 times synchronized with the internal phase θ. The first stage on the left side of FIG. 3A shows a three-phase phase voltage command, and the second stage on the left side of FIG. 3A shows a phase modulation wave which is a sinusoidal component having a frequency 6 times the internal phase θ. The third stage on the left side of FIG. 3A is the corrected internal phase obtained by adding the phase modulation wave to the internal phase.

The upper carrier signal carry1 and the lower carrier signal carry2 are generated by using the corrected internal phase obtained by adding the phase modulation wave to the internal phase θ. As a result, as shown on the right side of FIG. 3A, the effect of increasing or decreasing the carrier frequency according to the slope (dθ / dt) of the sine wave component can be obtained. The carrier frequency has a maximum value of ωcarry + Δωcarrymax, an intermediate value of ωcarry, and a minimum value of ωcarry−Δωcarrymax.

The control unit of the present embodiment will be described with reference to FIG. 3 (b). The first multiplier 8 multiplies the internal phase θ by 6 to calculate 6θ. The SIN unit calculates sin6θ based on 6θ. The second multiplier 10 multiplies sin6θ by Δωcarrymax / Ncarry6ωrat to calculate Δωcarrymax / Ncarry6ωlatsin (6θ). The adder 11 adds the output of the second multiplier 10 to the internal phase θ.

The third multiplier 2 multiplies the output of the adder 11 by 1 / 2π. The fourth multiplier 3 multiplies the output of the third multiplier 2 by the number of carriers Ncarry per cycle. The fifth multiplier 4 multiplies the output of the fourth multiplier 3 by 2. The first subtractor 5 subtracts 1 from the output of the fifth multiplier 4. The absolute value calculation unit 6 calculates the absolute value of the output of the first subtractor 5. The second subtractor 7 subtracts 1 from the output of the absolute value calculation unit 6.

The output of the absolute value calculation unit 6 becomes the upper carrier signal carry1, and the output of the second subtractor 7 becomes the lower carrier signal carry2.

Since the sine wave component is synchronized with the internal phase, the number of carriers per cycle is always constant (Ncurry). Further, even in a device in which the cycle of the internal phase fluctuates depending on the PLL of the system voltage or the like, the number of carriers per cycle can be kept constant.

The relationship between the internal phase θ before the addition of the sinusoidal component and the frequency ω _rat of the internal phase is shown in (1) below. t is time.

Since the synchronous PWM generates carriers having a frequency Ncarry times the internal phase θ, the carrier frequency ωcarry when the sine wave component is not added can be obtained by the following equation (2).

Assuming that the magnitude of the maximum deviation between the carrier frequency ωcarry (constant) before modulation and the carrier frequency ωcarry_m (changed at 6f) after modulation (upper carrier signal, lower carrier signal) is Δωcarrymax, the internal phase is set in the present embodiment. The sine wave to be added can be expressed by the following equation (3).

The corrected internal phase θm to which the sine wave is added is given by the following equation (4).

The carrier frequency ωcarry_m after modulation (upper carrier signal, lower carrier signal) is given by the following equation (5).

From the above, the carrier frequency changes by ± Δωcarrymax at a frequency 6 times the internal phase.

As shown above, according to the present embodiment, since the sinusoidal waveform having a frequency of 6 times is generated from the internal phase, the number of carriers per period of the internal phase is always constant. Further, even in a device in which the frequency of the internal phase fluctuates depending on the PLL of the power system or the like, the number of carriers per cycle can be kept constant while fluctuating the carrier frequency.

By using the upper and lower carrier signals carry1 and carry2 generated in this way, the voltage ripple usually rises due to pulse chipping in the vicinity of zero cross, and the THD (total harmonic distortion) deteriorates, but the carrier frequency near zero cross increases. By doing so, the number of equivalent switchings when viewed as a line voltage is increased, and the output voltage distortion is improved.

Furthermore, as a side effect, when the output current power factor of the DC / three-phase AC converter is 1, the amplitude of the output current when the phase voltage command value peaks also peaks, so that the output current amplitude peaks. Sometimes the carrier frequency drops and the carrier frequency increases when the output current amplitude is zero, thus reducing switching loss. This effect increases as the output current power factor approaches 1.

Therefore, it is possible to improve the output voltage distortion rate of the power conversion device and improve the efficiency of the device.

Although the above description has been made in detail only for the specific examples described in the present invention, it is obvious to those skilled in the art that various modifications and modifications are possible within the scope of the technical idea of the present invention. It goes without saying that such modifications and modifications fall within the scope of the claims.

1 ... Synchronous carrier generator 2 ... 3rd multiplier 3 ... 4th multiplier 4 ... 5th multiplier 5 ... 1st multiplier 6 ... Absolute value calculation unit 7 ... 2nd multiplier 8 ... 1st multiplier 9 ... SIN part 10 ... Second multiplier 11 ... Adder θ ... Internal phase θm ... Corrected internal phase carry1, carry2 ... Upper carrier signal, lower carrier signal ωcarry ... Carrier frequency before modulation ωcarry_m ... After modulation (upper carrier signal, lower) Carrier frequency of side carrier signal Ncarry… Number of carriers per cycle ωrat… Frequency of internal phase Δωcarrymax… magnitude of maximum deviation of carrier frequency after modulation (upper carrier signal, lower carrier signal)

Claims (4)

A 3-level power converter that outputs a 3-level voltage,
An upper carrier signal and a lower carrier signal are generated based on the corrected internal phase obtained by adding a sinusoidal component having a frequency 6 times the internal phase to the internal phase, and the upper carrier signal, the lower carrier signal, and the phase voltage command are used. The control unit that generates the gate signal of the three-level power converter based on the synchronous PWM control by comparison of
A power conversion device characterized by being equipped with. The control unit
The first adder that calculates the corrected internal phase by the following equation (4),
A third multiplier that multiplies the output of the first adder by 1 / 2π,
A fourth multiplier that multiplies the output of the third multiplier by the number of carriers per cycle,
A fifth multiplier that multiplies the output of the fourth multiplier by 2.
A first subtractor that subtracts 1 from the output of the fifth multiplier,
An absolute value calculation unit that calculates the absolute value of the output of the first subtractor,
A second subtractor that subtracts 1 from the output of the absolute value calculation unit,
The power conversion device according to claim 1, wherein the output of the absolute value calculation unit is used as the upper carrier signal, and the output of the second subtractor is used as the lower carrier signal.

θm: Corrected internal phase ωrat: Frequency of internal phase Ncarry: Number of carriers per cycle Δωcarrymax: Size of maximum deviation of carrier frequency after modulation (upper carrier signal, lower carrier signal) t: Time The power conversion device according to claim 1 or 2, wherein the carrier frequencies of the upper carrier signal and the lower carrier signal are set to the following equation (5).

ωcarry_m: Carrier frequency after modulation (upper carrier signal, lower carrier signal) Ncarry: Number of carriers per cycle θm: Corrected internal phase ωrat: Internal phase frequency t: Time Δωcarrymax: After modulation (upper carrier signal, lower side) The magnitude of the maximum deviation of the carrier frequency of the carrier signal) ωcarry: Carrier frequency of the carrier signal before modulation A 3-level power converter that outputs a 3-level voltage,
A control unit that generates a gate signal of the three-level power converter based on synchronous PWM control by comparing the upper carrier signal, the lower carrier signal and the phase voltage command, and
It is a control method of a power conversion device equipped with
The control unit
A control method for a power conversion device, characterized in that an upper carrier signal and a lower carrier signal are generated based on a corrected internal phase in which a sine wave component having a frequency six times the internal phase is added to the internal phase.

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