JPH1126943A - Multilayer wiring board and manufacture of the same - Google Patents

Multilayer wiring board and manufacture of the same

Info

Publication number
JPH1126943A
JPH1126943A JP9173839A JP17383997A JPH1126943A JP H1126943 A JPH1126943 A JP H1126943A JP 9173839 A JP9173839 A JP 9173839A JP 17383997 A JP17383997 A JP 17383997A JP H1126943 A JPH1126943 A JP H1126943A
Authority
JP
Japan
Prior art keywords
capacitor element
insulating sheet
insulating
wiring board
electrodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9173839A
Other languages
Japanese (ja)
Other versions
JP3199664B2 (en
Inventor
Katsura Hayashi
桂 林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=15968123&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=JPH1126943(A) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP17383997A priority Critical patent/JP3199664B2/en
Publication of JPH1126943A publication Critical patent/JPH1126943A/en
Application granted granted Critical
Publication of JP3199664B2 publication Critical patent/JP3199664B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PROBLEM TO BE SOLVED: To manufacture a compact wiring board incorporating a capacitor element in a simple method without affecting the characteristics or structure of the wiring board. SOLUTION: A capacitor element A in which a dielectric layer 6 is interposed between a pair of electrodes 4 and 5 made of a metallic foil or the like is formed on the surface of a film. Next, a through-hole conductor 2 and a wiring circuit layer 3 are formed in an insulating sheet 1 including an organic resin so that a wiring layer S1 can be formed. The capacitor element A is transferred from the film on which the capacitor element A is formed to the surface of a wiring layer S1. Other wiring layers S2 and S3 in which wiring circuit layers 8 and 9 and through-hole conductors 10 and 11 are formed are laminated and pressed on the surface so that a multilayer wiring board incorporating the capacitor element can be obtained. Also, the wiring circuit layer 3 is processed simultaneously with the transfer of the capacitor element A so that the process can be simplified.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、コンデンサ素子を
内蔵した半導体素子収納用パッケージなどに適した多層
配線基板とその製造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring board suitable for a semiconductor device housing package or the like having a built-in capacitor element and a method of manufacturing the same.

【0002】[0002]

【従来技術】従来より、多層配線基板、例えば、半導体
素子を収納するパッケージに使用される多層配線基板と
して、高密度の配線が可能なセラミック多層配線基板が
多用されている。この多層セラミック配線基板は、アル
ミナなどの絶縁基板と、その表面に形成されたWやMo
等の高融点金属からなる配線導体とから構成されるもの
で、この絶縁基板の一部に凹部が形成され、この凹部内
に半導体素子が収納され、蓋体によって凹部を気密に封
止されるものである。
2. Description of the Related Art Conventionally, ceramic multilayer wiring boards capable of high-density wiring have been frequently used as multilayer wiring boards, for example, multilayer wiring boards used for packages containing semiconductor elements. This multilayer ceramic wiring board is composed of an insulating substrate such as alumina and W or Mo formed on the surface thereof.
And a wiring conductor made of a metal having a high melting point such as the above. A concave portion is formed in a part of the insulating substrate, the semiconductor element is accommodated in the concave portion, and the concave portion is hermetically sealed by the lid. Things.

【0003】ところが、このようなセラミック多層配線
基板の絶縁基板を構成するセラミックスは、硬くて脆い
性質を有することから、セラミックスの欠けや割れ等が
発生しやすく、また、高温での焼成により焼成収縮が生
じるために、得られる基板に反り等の変形や寸法のばら
つき等が発生しやすいという問題があり、回路基板の超
高密度化やフリップチップ等のような基板の平坦度の厳
しい要求に対して、十分に対応できないという問題があ
った。
However, ceramics constituting such an insulating substrate of a ceramic multilayer wiring board are hard and brittle, so that chipping or cracking of the ceramics is liable to occur, and firing shrinkage due to firing at high temperature. The problem is that the resulting substrate is liable to be deformed such as warpage or dimensional variation in the obtained substrate. Therefore, there was a problem that it was not possible to respond sufficiently.

【0004】これに対して、銅箔を接着した有機樹脂を
含む絶縁基板表面にエッチング法により微細な回路を形
成し、しかるのちにこの基板を積層して多層化した後、
スルーホールを形成してその内面をメッキ処理して、層
間の電気的な接続を行う多層プリント基板は、セラミッ
クスのような高温での処理が不要であり、あらゆる形状
に対応できるなどの点で有利である。
On the other hand, a fine circuit is formed on the surface of an insulating substrate containing an organic resin to which a copper foil is adhered by an etching method.
Multi-layer printed circuit boards that form through holes and plating the inner surface to make electrical connections between layers do not require processing at high temperatures like ceramics, and are advantageous in that they can be used in any shape. It is.

【0005】また、近年、携帯情報端末の発達や、コン
ピュータを持ち運んで操作するいわゆるモバイルコンピ
ューティングの普及によって、これらの機器の小型、薄
型化に伴い、その機器内に搭載される多層配線基板も、
高精細化、小型化などの要求が高まりつつある。
[0005] In recent years, with the development of portable information terminals and the spread of so-called mobile computing that carries and operates a computer, these devices have become smaller and thinner, and a multilayer wiring board mounted in the device has also been required. ,
Demands for high definition and miniaturization are increasing.

【0006】また、半導体素子を搭載するパッケージン
グ技術においては、半導体素子への信号波形の乱れを少
なくするために、絶縁基板内に誘電体層と一対の電極か
らなるコンデンサを形成する、絶縁基板表面にコンデン
サを外付けする、半導体素子や蓋体にコンデンサ素子を
形成する、などの種々の手法により、いわゆるデカップ
リングコンデンサを形成することが行われている。
In a packaging technique for mounting a semiconductor element, a capacitor formed of a dielectric layer and a pair of electrodes is formed in an insulating substrate in order to reduce disturbance of a signal waveform to the semiconductor element. 2. Description of the Related Art A so-called decoupling capacitor is formed by various methods such as attaching a capacitor externally to a surface or forming a capacitor element on a semiconductor element or a lid.

【0007】[0007]

【発明が解決しようとする課題】一般に、有機樹脂を含
む絶縁基板からなる多層プリント基板を用いたパッケー
ジにおいて、デカップリングコンデンサを設ける場合、
図3に示すように、多層構造からなる絶縁基板20内の
1層の絶縁層20aの両側に一対の電極21,22を形
成し、その電極21、22をスルーホール導体23、2
4で表面に引出し、表面に形成されたパッド25、26
と接続し、このパッド25、26にて静電容量を取り出
す構造が知られている。しかしながら、かかる構造で
は、コンデンサの容量が、絶縁層の性質によって決定さ
れるために、必要な静電容量を取り出すためには、その
電極面積や、絶縁層の厚みを変更するなどの設計上の制
約が発生する。
Generally, when a decoupling capacitor is provided in a package using a multilayer printed circuit board made of an insulating substrate containing an organic resin,
As shown in FIG. 3, a pair of electrodes 21 and 22 are formed on both sides of a single insulating layer 20a in an insulating substrate 20 having a multilayer structure, and the electrodes 21 and 22 are connected to through-hole conductors 23 and 2 respectively.
4. Pads 25 and 26 formed on the surface by being pulled out to the surface with 4
A structure is known in which the capacitance is connected to the pads 25 and 26 to take out the capacitance. However, in such a structure, since the capacitance of the capacitor is determined by the properties of the insulating layer, in order to take out the necessary capacitance, the electrode area or the thickness of the insulating layer must be changed in design. Restrictions occur.

【0008】また、電極間に挟まれた絶縁層の誘電特性
を他の絶縁層と変えて制御することも可能であるが、格
別な絶縁材料の設計や、他の絶縁層の積層化におけるマ
ッチング性等を検討する必要がある。
It is also possible to control the dielectric properties of the insulating layer sandwiched between the electrodes by changing the dielectric properties of the other insulating layers. It is necessary to consider sex etc.

【0009】よって、現在では、ほとんどが基板表面に
コンデンサを取付ける方法が主流であるが、このような
方法は、配線基板の小型化に対して十分に対応できない
という問題があった。
Therefore, at present, a method of mounting a capacitor on the surface of a substrate is mainly used, but such a method has a problem that it cannot sufficiently cope with miniaturization of a wiring substrate.

【0010】従って、本発明の目的は、小型化が可能
で、配線基板の特性や構造に影響を与えることなく、コ
ンデンサ素子を内蔵した配線基板を提供するにある。ま
た、本発明の他の目的は、簡便な方法で、配線基板の特
性や構造に影響を与えることなく、コンデンサ素子を内
蔵させることのできる配線基板の製造方法を提供するに
ある。
Accordingly, it is an object of the present invention to provide a wiring board having a built-in capacitor element which can be reduced in size and does not affect the characteristics and structure of the wiring board. It is another object of the present invention to provide a method of manufacturing a wiring board that can incorporate a capacitor element by a simple method without affecting the characteristics and structure of the wiring board.

【0011】[0011]

【課題を解決するための手段】本発明者は、コンデンサ
素子の基板内への内蔵方法について検討を重ねた結果、
フィルム上において、金属箔と誘電体層を積層して形成
したコンデンサ素子を、配線回路層が形成された未硬化
または半硬化状態の絶縁シートの表面に加圧しながら転
写して、絶縁シートの表面にコンデンサ素子を埋め込
み、さらに他の絶縁シートを重ねた後、一括して硬化さ
せること、またはコンデンサ素子を配線回路層が形成さ
れた未硬化または半硬化状態の絶縁シート間に介在させ
て積層圧着して、コンデンサ素子を絶縁シート間に埋め
込んだ後、一括して硬化させることにより、基板の配線
基板の特性や構造に影響を与えることなく、コンデンサ
素子を配線基板内に内蔵できることを見いだし、本発明
に至った。
Means for Solving the Problems The present inventor has repeatedly studied a method of incorporating a capacitor element into a substrate, and as a result,
On a film, a capacitor element formed by laminating a metal foil and a dielectric layer is transferred while being pressed onto the surface of an uncured or semi-cured insulating sheet on which a wiring circuit layer is formed, and the surface of the insulating sheet is After embedding the capacitor element and further laminating another insulating sheet, it is cured together, or the capacitor element is interposed between the uncured or semi-cured insulating sheets with the wiring circuit layer formed, and laminated and crimped Then, after embedding the capacitor element between the insulating sheets and curing it all together, it was found that the capacitor element can be built into the wiring board without affecting the characteristics and structure of the wiring board of the board. Invented the invention.

【0012】即ち、本発明の多層配線基板は、少なくと
も有機樹脂を含有する複数の絶縁層が積層されてなる絶
縁基板と、該絶縁基板の少なくとも前記絶縁層間に配設
された配線回路層とを具備する多層配線基板において、
前記絶縁層間に、一対の電極間に誘電体層が挟持された
コンデンサ素子を埋設したことを特徴とするものであ
り、さらには、配線基板表面に一対の表面電極を設け、
該表面電極と前記コンデンサ素子の前記一対の電極と
を、一対のスルーホール導体によりそれぞれ電気的に接
続したことを特徴とするものである。
That is, the multilayer wiring board of the present invention comprises an insulating substrate having at least a plurality of insulating layers containing an organic resin laminated, and a wiring circuit layer provided at least between the insulating layers of the insulating substrate. In the multilayer wiring board provided,
A capacitor element in which a dielectric layer is sandwiched between a pair of electrodes is buried between the insulating layers, and further, a pair of surface electrodes is provided on the surface of the wiring board,
The surface electrode and the pair of electrodes of the capacitor element are electrically connected by a pair of through-hole conductors.

【0013】また、本発明の多層配線基板の製造方法
は、フィルムの表面に、一対の電極間に誘電体層が挟持
されたコンデンサ素子を形成する工程と、熱硬化性樹脂
を含む未硬化または半硬化状態の絶縁シートの表面に配
線回路層を形成する工程と、前記フィルム表面に形成さ
れたコンデンサ素子を前記絶縁シート表面に加圧しなが
ら転写して、前記コンデンサ素子を前記絶縁シート表面
に埋め込む工程と、前記コンデンサ素子が埋め込まれた
前記絶縁シート表面に、熱硬化性樹脂を含む未硬化また
は半硬化状態の他の絶縁シートを積層圧着する工程と、
前記積層物を加熱処理して、前記積層物を一括して硬化
する工程と、を具備することを特徴とするものであり、
また、前記配線回路層が、フィルム表面に被着された金
属箔をエッチングして配線回路層を形成した後、該フィ
ルムから前記絶縁シートに転写して形成することを特徴
とするものであり、さらには、前記配線回路層の前記絶
縁シートへの転写と、前記コンデンサ素子の前記絶縁シ
ートへの転写を同時に行うことを特徴とするものであ
る。
[0013] The method for manufacturing a multilayer wiring board according to the present invention comprises the steps of: forming a capacitor element having a dielectric layer sandwiched between a pair of electrodes on a surface of a film; Forming a wiring circuit layer on the surface of the semi-cured insulating sheet, transferring the capacitor element formed on the film surface to the insulating sheet surface while applying pressure, and embedding the capacitor element on the insulating sheet surface. Step, and a step of laminating and pressing another insulating sheet containing a thermosetting resin on the surface of the insulating sheet in which the capacitor element is embedded, including an uncured or semi-cured state,
Heat-treating the laminate, and curing the laminate at once, characterized by comprising:
Further, the wiring circuit layer is formed by etching a metal foil adhered to a film surface to form a wiring circuit layer, and then transferring the film from the film to the insulating sheet. Furthermore, the transfer of the wiring circuit layer to the insulating sheet and the transfer of the capacitor element to the insulating sheet are performed simultaneously.

【0014】また、本発明の他の多層配線基板の製造方
法は、熱硬化性樹脂を含む未硬化または半硬化状態の第
1の絶縁シートの表面に配線回路層を形成する工程と、
熱硬化性樹脂を含む未硬化または半硬化状態の第2の絶
縁シートの表面に配線回路層を形成する工程と、配線回
路層が形成された前記第1の絶縁シートおよび前記第2
の絶縁シートを、一対の電極間に誘電体層が挟持された
コンデンサ素子を所定位置に介在させて加圧しながら積
層し、前記コンデンサ素子を前記絶縁シート間に埋め込
む工程と、前記積層物を加熱処理して、前記積層物を一
括して硬化させる工程と、を具備することを特徴とする
ものである。
Further, another method of manufacturing a multilayer wiring board according to the present invention includes a step of forming a wiring circuit layer on a surface of an uncured or semi-cured first insulating sheet containing a thermosetting resin;
Forming a wiring circuit layer on the surface of an uncured or semi-cured second insulating sheet containing a thermosetting resin; and forming the first insulating sheet on which a wiring circuit layer is formed and the second insulating sheet.
Laminating the insulating sheet, while pressing a capacitor element having a dielectric layer sandwiched between a pair of electrodes at a predetermined position, embedding the capacitor element between the insulating sheets, and heating the laminate. And curing the laminate at once.

【0015】[0015]

【発明の実施の形態】以下、本発明の多層配線基板につ
いて、その第1の製造方法を説明するための工程図であ
る図1、および第2の製造方法を説明するための図2を
もとに説明する。本発明における第1の配線基板の製造
方法によれば、まず、図1(a)に示すように、有機樹
脂からなる軟質の絶縁シート1を準備する。また、この
絶縁シート1には、所望により厚み方向に貫通するスル
ーホールを形成し、そのスルーホール内に金属粉末を含
む導体ペーストをスクリーン印刷や吸引処理しながら充
填して、スルーホール導体2を形成する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A multilayer wiring board according to the present invention will be described with reference to FIG. 1 which is a process chart for explaining a first manufacturing method and FIG. 2 for explaining a second manufacturing method. This will be explained. According to the first method for manufacturing a wiring board of the present invention, first, as shown in FIG. 1A, a soft insulating sheet 1 made of an organic resin is prepared. Further, the insulating sheet 1 is formed with a through-hole penetrating in the thickness direction as required, and the through-hole is filled with a conductive paste containing a metal powder while performing screen printing or suction processing to form the through-hole conductor 2. Form.

【0016】具体的には、まず、絶縁シートとして、前
述したような熱硬化性有機樹脂、または熱硬化性有機樹
脂とフィラーなどの組成物を混練機や3本ロールなどの
手段によって十分に混合し、これを圧延法、押し出し
法、射出法、ドクターブレード法などによってシート状
に成形する。そして、所望により熱処理して熱硬化性樹
脂を半硬化させる。半硬化には、樹脂が完全硬化するに
十分な温度よりもやや低い温度に加熱する。
Specifically, first, as an insulating sheet, a thermosetting organic resin or a composition of a thermosetting organic resin and a filler as described above is sufficiently mixed by means of a kneader or a three-roll mill. This is formed into a sheet by a rolling method, an extrusion method, an injection method, a doctor blade method, or the like. Then, the thermosetting resin is semi-cured by heat treatment if desired. For semi-curing, the resin is heated to a temperature slightly lower than a temperature sufficient to completely cure the resin.

【0017】そして、この状態の絶縁層に対して、スル
ーホールを形成する。このスルーホールの形成は、ドリ
ル、パンチング、サンドブラスト、あるいは炭酸ガスレ
ーザ、YAGレーザ、及びエキシマレーザ等の照射によ
る加工など公知の方法が採用される。
Then, a through hole is formed in the insulating layer in this state. A well-known method such as drilling, punching, sandblasting, or processing by irradiation with a carbon dioxide gas laser, a YAG laser, an excimer laser, or the like is employed for forming the through hole.

【0018】なお、絶縁シートを形成する有機樹脂は、
通常、熱硬化性樹脂、あるいは高融点の耐熱性熱可塑性
樹脂、又は、これらの樹脂からなる組成物等が用いられ
る。
The organic resin forming the insulating sheet is as follows:
Usually, a thermosetting resin, a heat-resistant thermoplastic resin having a high melting point, a composition composed of these resins, or the like is used.

【0019】熱硬化性樹脂としては、絶縁材料としての
電気的特性、耐熱性、および機械的強度を有する熱硬化
性樹脂であれば特に限定されるものでなく、例えば、フ
ェノール樹脂、エポキシ樹脂、イミド樹脂、フッ素樹
脂、フェニレンエーテル樹脂、ビスマイレイドトリアジ
ン樹脂、ユリア樹脂、メラミン樹脂、シリコーン樹脂、
ウレタン樹脂、不飽和ポリエステル樹脂、アリル樹脂等
が、単独または組み合わせて使用できる。
The thermosetting resin is not particularly limited as long as it is a thermosetting resin having electrical properties, heat resistance, and mechanical strength as an insulating material. Examples of the thermosetting resin include a phenol resin, an epoxy resin, Imide resin, fluororesin, phenylene ether resin, bismailide triazine resin, urea resin, melamine resin, silicone resin,
Urethane resins, unsaturated polyester resins, allyl resins and the like can be used alone or in combination.

【0020】また、上記の絶縁シート1中には、絶縁基
板あるいは配線基板全体の強度を高めるために、有機樹
脂に対してフィラーを複合化させることもできる。有機
樹脂と複合化されるフィラーとしては、SiO2 、Al
2 3 、ZrO2 、TiO2、AlN、SiC、BaT
iO3 、SrTiO3 、ゼオライト、CaTiO3 、ほ
う酸アルミニウム等の無機質フィラーが好適に用いられ
る。また、ガラスやアラミド樹脂からなる不織布、織布
などに上記樹脂を含浸させて用いてもよい。なお、有機
樹脂とフィラーとは、体積比率で15:85〜50:5
0の比率で複合化されるのが適当である。
In the insulating sheet 1, a filler can be compounded with an organic resin in order to increase the strength of the entire insulating substrate or wiring substrate. SiO 2 , Al
2 O 3 , ZrO 2 , TiO 2 , AlN, SiC, BaT
Inorganic fillers such as iO 3 , SrTiO 3 , zeolite, CaTiO 3 and aluminum borate are preferably used. Further, a nonwoven fabric or a woven fabric made of glass or aramid resin may be used by impregnating the above resin. The organic resin and the filler are in a volume ratio of 15:85 to 50: 5.
Suitably, the compound is formed in a ratio of 0.

【0021】一方、スルーホール導体2に充填される金
属ペーストは、銅粉末、銀粉末、銀被覆銅粉末、銅銀合
金などの、平均粒径が0.5〜50μmの金属粉末を含
む。
On the other hand, the metal paste filled in the through-hole conductor 2 includes metal powder having an average particle size of 0.5 to 50 μm, such as copper powder, silver powder, silver-coated copper powder, and copper-silver alloy.

【0022】金属粉末の平均粒径が0.5μmよりも小
さいと、金属粉末同士の接触抵抗が増加してスルーホー
ル導体の抵抗が高くなる傾向にあり、50μmを越える
とスルーホール導体の低抵抗化が難しくなる傾向にあ
る。
If the average particle size of the metal powder is smaller than 0.5 μm, the contact resistance between the metal powders increases and the resistance of the through-hole conductor tends to increase. Tend to be difficult.

【0023】また、導体ペーストは、前述したような金
属粉末に対して、前述したような結合用有機樹脂や溶剤
を添加混合して調製される。ペースト中に添加される溶
剤としては、用いる結合用有機樹脂が溶解可能な溶剤で
あればよく、例えば、イソプロピルアルコール、テルピ
ネオール、2−オクタノール、ブチルカルビトールアセ
テート等が用いられる。
The conductor paste is prepared by adding and mixing the above-mentioned binding organic resin and solvent to the above-mentioned metal powder. The solvent to be added to the paste may be any solvent that can dissolve the binding organic resin to be used. For example, isopropyl alcohol, terpineol, 2-octanol, butyl carbitol acetate and the like are used.

【0024】上記の結合用有機樹脂としては、前述した
種々の絶縁シートを構成する有機樹脂の他、セルロース
なども使用される。この有機樹脂は、前記金属粉末同士
を互いに接触させた状態で結合するとともに、金属粉末
を絶縁シートに接着させる作用をなしている。この有機
樹脂は、金属ペースト中において、0.1乃至40体積
%、特に0.3乃至30体積%の割合で含有されること
が望ましい。これは、樹脂量が0.1体積%よりも少な
いと、金属粉末同士を強固に結合することが難しく、低
抵抗金属を絶縁層に強固に接着させることが困難とな
り、逆に40体積%を越えると、金属粉末間に樹脂が介
在することになり粉末同士を十分に接触させることが難
しくなり、スルーホール導体の抵抗が大きくなるためで
ある。
As the above-mentioned organic resin for binding, cellulose and the like are used in addition to the organic resins constituting the above-mentioned various insulating sheets. The organic resin has a function of bonding the metal powders to each other in a state where they contact each other and bonding the metal powders to the insulating sheet. This organic resin is desirably contained in the metal paste at a ratio of 0.1 to 40% by volume, particularly 0.3 to 30% by volume. If the amount of the resin is less than 0.1% by volume, it is difficult to firmly bond the metal powders to each other, and it is difficult to firmly bond the low-resistance metal to the insulating layer. If it exceeds, the resin is interposed between the metal powders, making it difficult to bring the powders into sufficient contact with each other and increasing the resistance of the through-hole conductor.

【0025】次に、図1(b)に示すように、絶縁シー
ト1の表面に配線回路層3を形成する。この配線回路層
3は、絶縁シート1の表面に金属箔を貼り付けた後、エ
ッチング処理して回路パターンを形成する方法、絶縁シ
ート1表面にレジストを形成して、メッキにより形成す
る方法、樹脂フィルム表面に金属箔を貼り付け、金属箔
をエッチング処理して回路パターンを形成した後、この
金属箔からなる回路パターンを絶縁シート1表面に転写
させる方法等が挙げられる。
Next, as shown in FIG. 1B, a wiring circuit layer 3 is formed on the surface of the insulating sheet 1. The wiring circuit layer 3 is formed by attaching a metal foil to the surface of the insulating sheet 1 and then etching it to form a circuit pattern, forming a resist on the surface of the insulating sheet 1 and plating the same, resin A method of attaching a metal foil to the film surface, etching the metal foil to form a circuit pattern, and transferring the circuit pattern made of the metal foil to the surface of the insulating sheet 1 may be used.

【0026】次に、本発明によれば、上記のスルーホー
ル導体2および配線回路層3が形成された絶縁シート1
の表面に、一対の電極4、5間に誘電体層6を配設した
コンデンサ素子を形成する。このコンデンサ素子の形成
方法としては、例えば、絶縁シートの表面に、金属箔か
らなる電極4を転写し、次いで、誘電体層6、金属箔か
らなる電極5を形成することにより形成することが可能
である。しかしながら、かかる方法は、絶縁シート1表
面に直接的にコンデンサ素子を形成するために、絶縁シ
ート1に悪影響を及ぼす場合があり、コンデンサ素子の
設計上の制約が多い。
Next, according to the present invention, the insulating sheet 1 on which the through-hole conductor 2 and the wiring circuit layer 3 are formed.
A capacitor element having a dielectric layer 6 disposed between a pair of electrodes 4 and 5 is formed on the surface of the capacitor element. As a method for forming the capacitor element, for example, the capacitor element can be formed by transferring an electrode 4 made of a metal foil to the surface of an insulating sheet, and then forming a dielectric layer 6 and an electrode 5 made of a metal foil. It is. However, in such a method, since the capacitor element is formed directly on the surface of the insulating sheet 1, the insulating sheet 1 may be adversely affected, and there are many restrictions on the design of the capacitor element.

【0027】そこで、本発明によれば、別途コンデンサ
素子を作製し、そのコンデンサ素子を絶縁シート1表面
に転写して形成することが望ましい。その具体的な方法
を図1(c1)〜(c4)に示す。この方法によれば、
例えば、樹脂フィルム7の表面に金属箔をエッチングし
て電極4を形成した後(図1(c1))、その電極4の
表面に誘電体層6を形成する(図1(c2))。また
は、金属箔からなる電極4表面に誘電体層6を形成した
ものを樹脂フィルムに貼り付ける。
Therefore, according to the present invention, it is desirable to separately manufacture a capacitor element and transfer the capacitor element to the surface of the insulating sheet 1 to form the capacitor element. The specific method is shown in FIGS. 1 (c1) to 1 (c4). According to this method,
For example, after the metal foil is etched on the surface of the resin film 7 to form the electrode 4 (FIG. 1 (c1)), the dielectric layer 6 is formed on the surface of the electrode 4 (FIG. 1 (c2)). Alternatively, a material in which the dielectric layer 6 is formed on the surface of the electrode 4 made of a metal foil is attached to a resin film.

【0028】誘電体層6の形成は、スパッタリング等の
物理蒸着法が低温で形成できる点で望ましい。例えば、
銅箔の誘電体層形成箇所以外をマスクして真空容器内に
設置し、蒸着源にチタン酸バリウム等公知の高誘電率材
料を設置してスパッタリングを行い、電極表面に誘電体
層を形成する。さらに高容量のコンデンサ素子を必要と
する場合には、高誘電率材料と、銅などの金属を交互に
スパッタして薄膜多層コンデンサ素子を形成することも
できる。
The formation of the dielectric layer 6 is desirable in that a physical vapor deposition method such as sputtering can be formed at a low temperature. For example,
A portion other than the dielectric layer forming portion of the copper foil is masked and set in a vacuum vessel, a known high dielectric constant material such as barium titanate is set as a vapor deposition source, and sputtering is performed to form a dielectric layer on the electrode surface. . When a capacitor element having a higher capacity is required, a high-dielectric-constant material and a metal such as copper can be alternately sputtered to form a thin-film multilayer capacitor element.

【0029】また、誘電体層の形成の他の方法として
は、金属箔からなる電極の表面に、誘電体材料からなる
アルコキシド等の溶液を塗布し、熱処理して誘電体層を
形成することもできる。
As another method of forming a dielectric layer, a solution such as an alkoxide made of a dielectric material is applied to the surface of an electrode made of a metal foil, and heat treatment is performed to form the dielectric layer. it can.

【0030】そして、誘電体層6の表面に、電極5を形
成することによりコンデンサ素子Aを形成することがで
きる(図1(c3))。この電極5は、例えば、スパッ
タリング等の物理蒸着法によって銅などの金属を所定箇
所にスパッタするか、または誘電体層6の表面に金属箔
を被着させる。また、電極5は、後述するように転写す
る絶縁シート側に形成しておき、電極4と誘電体層6を
絶縁シート1に形成した電極5の表面に転写して形成す
ることも可能である。
Then, the capacitor element A can be formed by forming the electrode 5 on the surface of the dielectric layer 6 (FIG. 1 (c3)). The electrode 5 is formed by, for example, sputtering a metal such as copper at a predetermined location by a physical vapor deposition method such as sputtering, or applying a metal foil on the surface of the dielectric layer 6. Further, the electrodes 5 can be formed on the side of the insulating sheet to be transferred as described later, and the electrodes 4 and the dielectric layer 6 can be formed by transferring them to the surface of the electrodes 5 formed on the insulating sheet 1. .

【0031】その後、このコンデンサ素子Aが形成され
た樹脂フィルム7を絶縁シート1に積層して(図1(c
4))、圧着した後、樹脂フィルム7を剥がしてコンデ
ンサ素子Aを絶縁シート1表面に転写することによっ
て、図1(d)に示すような、スルーホール導体2と配
線回路層3とコンデンサ素子Aが形成された単層の配線
層S1を形成することができる。この時、コンデンサ素
子Aを絶縁シート1表面に圧着した場合、絶縁シート1
は、未硬化または半硬化状態であり軟質であることか
ら、コンデンサ素子Aを絶縁シート1の表面に埋め込む
ことができる。
Thereafter, the resin film 7 on which the capacitor element A is formed is laminated on the insulating sheet 1 (FIG. 1 (c)).
4)) After the compression bonding, the resin film 7 is peeled off, and the capacitor element A is transferred to the surface of the insulating sheet 1 so that the through-hole conductor 2, the wiring circuit layer 3, and the capacitor element as shown in FIG. A single wiring layer S1 on which A is formed can be formed. At this time, when the capacitor element A is pressed on the surface of the insulating sheet 1, the insulating sheet 1
Is in an uncured or semi-cured state and is soft, so that the capacitor element A can be embedded in the surface of the insulating sheet 1.

【0032】また、配線回路層3を樹脂フィルムからの
転写法によって絶縁シート1の表面に形成する場合、そ
の樹脂フィルム表面に、配線回路層3とコンデンサ素子
Aを形成して、これらを絶縁シート1表面に同時に転写
すれば、工程の簡略化を図ることができる。
When the wiring circuit layer 3 is formed on the surface of the insulating sheet 1 by a transfer method from a resin film, the wiring circuit layer 3 and the capacitor element A are formed on the surface of the resin film, and these are formed on the insulating sheet. Simultaneous transfer to one surface can simplify the process.

【0033】配線回路層3は、例えば、銅、銀、アルミ
ニウム、金の群から選ばれる少なくとも1種、または2
種以上の合金を主体とする低抵抗金属を含むことが望ま
しく、特に、銅または銅を含む合金が最も望ましい。ま
た、場合によっては、導体組成物として回路の抵抗調整
のためにNi−Cr合金などの高抵抗の金属を混合、ま
たは合金化してもよい。さらには、配線層の低抵抗化の
ために、前記低抵抗金属よりも低融点の金属、例えば、
半田、錫などの低融点金属を導体組成物中の金属成分中
にて2〜20重量%の割合で含んでもよい。
The wiring circuit layer 3 is made of, for example, at least one selected from the group consisting of copper, silver, aluminum, and gold;
It is desirable to include a low resistance metal mainly composed of at least one kind of alloy, and particularly copper or an alloy containing copper is most desirable. In some cases, a high-resistance metal such as a Ni—Cr alloy may be mixed or alloyed as the conductor composition for adjusting the resistance of the circuit. Further, for lowering the resistance of the wiring layer, a metal having a lower melting point than the low-resistance metal, for example,
A low melting point metal such as solder or tin may be contained in the metal component in the conductor composition at a ratio of 2 to 20% by weight.

【0034】次に、上記図1(a)(b)と同様にして
作製された単一の配線層S2や配線層S3とを位置合わ
せして積層圧着し、配線層S1〜S3における絶縁シー
ト中の熱硬化性樹脂が硬化するに十分な温度に加熱して
一括して完全硬化させることにより、図1(e)に示す
ようなコンデンサ素子を内蔵する多層プリント配線基板
を形成することができる。
Next, a single wiring layer S2 or S3 manufactured in the same manner as in FIGS. 1A and 1B is aligned and laminated and pressed, and the insulating sheets in the wiring layers S1 to S3 are formed. By heating to a temperature sufficient to cure the thermosetting resin therein and performing complete curing at once, a multilayer printed wiring board incorporating a capacitor element as shown in FIG. 1 (e) can be formed. .

【0035】この時、図1(e)に示すように、配線層
2の表面に、表面電極8、9を形成し、さらに、表面電
極8、9とコンデンサ素子Aの電極4、5とそれぞれ電
気的に接続できる位置にスルーホール導体10、11を
形成することにより、積層圧着した後において、コンデ
ンサ素子Aからの容量をスルーホール導体10、11を
介して表面電極8,9より取り出すことができる。
At this time, as shown in FIG. 1E, surface electrodes 8 and 9 are formed on the surface of the wiring layer 2, and further, the surface electrodes 8 and 9 and the electrodes 4 and 5 of the capacitor element A are respectively connected. By forming the through-hole conductors 10 and 11 at positions where they can be electrically connected, it is possible to take out the capacitance from the capacitor element A from the surface electrodes 8 and 9 via the through-hole conductors 10 and 11 after lamination and pressure bonding. it can.

【0036】次に、本発明の第2の製造方法によれば、
図2(a)に示すように、高誘電層12を銅箔などの一
対の電極13、14により挟持したフィルム状のコンデ
ンサ素子Bを形成する。
Next, according to the second manufacturing method of the present invention,
As shown in FIG. 2A, a film-shaped capacitor element B in which the high dielectric layer 12 is sandwiched between a pair of electrodes 13 and 14 such as a copper foil is formed.

【0037】一方、前記図1(a)(b)の手法によ
り、未硬化または半硬化状態の絶縁シート15の表面に
配線回路層18,20,21やスルーホール導体16,
17,19を形成した配線層S4,S5、S6を準備
し、図2(b)に示すように、図2(a)にて準備した
コンデンサ素子Bを配線層S5、S6の間に位置合わせ
して積層する。
On the other hand, the wiring circuit layers 18, 20, 21 and the through-hole conductors 16, 16 are formed on the surface of the uncured or semi-cured insulating sheet 15 by the method shown in FIGS.
The wiring layers S4, S5 and S6 on which the layers 17 and 19 are formed are prepared, and as shown in FIG. 2B, the capacitor element B prepared in FIG. 2A is positioned between the wiring layers S5 and S6. And laminate.

【0038】その後、この積層体を加圧しながら圧着す
ることにより、配線層S5,S6の軟質状態の絶縁シー
ト15間にコンデンサ素子Bが埋め込まれる。そして、
この積層体を絶縁シート15中の熱硬化性樹脂が硬化す
るに十分な温度に加熱して一括して完全硬化させること
により、図2(c)に示すように、コンデンサ素子が絶
縁層間に埋設された多層配線基板を作製することができ
る。
Thereafter, by pressing the laminate while applying pressure, the capacitor element B is embedded between the soft insulating sheets 15 of the wiring layers S5 and S6. And
This laminate is heated to a temperature sufficient to cure the thermosetting resin in the insulating sheet 15 and completely cured at once, so that the capacitor element is embedded between the insulating layers as shown in FIG. A multi-layer wiring board can be manufactured.

【0039】また、図2(c)によれば、配線層S5、
S6にコンデンサ素子Bの電極13、14と電気的に接
続するスルーホール導体16、17を形成し、スルーホ
ール導体16を配線回路層18、スルーホール導体19
を経由して、表面電極20に接続し、また、スルーホー
ル導体17を表面電極21に電気的に接続することによ
り、コンデンサ素子Bの容量を表面電極20、21によ
り取り出すことができる。
According to FIG. 2C, the wiring layer S5,
In S6, through-hole conductors 16 and 17 electrically connected to the electrodes 13 and 14 of the capacitor element B are formed, and the through-hole conductor 16 is connected to the wiring circuit layer 18 and the through-hole conductor 19.
The capacitance of the capacitor element B can be taken out by the surface electrodes 20 and 21 by connecting the through-hole conductor 17 to the surface electrode 21 by connecting the through hole conductor 17 to the surface electrode 21 via the surface electrodes 20 and 21.

【0040】なお、図1および図2において、表面電極
の形成位置は、配線基板の一方側の面、または表面と裏
面のいずれでもよく、内蔵されたコンデンサ素子A,B
の電極とスルーホール導体等を用いて電気的に接続すれ
ばよい。
In FIGS. 1 and 2, the surface electrode may be formed on either one of the surfaces of the wiring board, or on the front surface and the back surface.
The electrodes may be electrically connected to each other using a through-hole conductor or the like.

【0041】このようにして、本発明によれば、複数の
絶縁層が積層されてなる絶縁基板における絶縁層間に、
一対の電極間に誘電体層が挟持されたコンデンサ素子を
形成することができる結果、絶縁基板の特性や配線基板
の構造を格別に変更することなく、簡便な方法によって
コンデンサ素子を内蔵した配線基板を作製することがで
きる。
As described above, according to the present invention, between the insulating layers of the insulating substrate formed by laminating a plurality of insulating layers,
As a result of forming a capacitor element in which a dielectric layer is sandwiched between a pair of electrodes, a wiring board with a built-in capacitor element can be formed in a simple manner without specially changing the characteristics of the insulating substrate and the structure of the wiring board. Can be produced.

【0042】[0042]

【実施例】【Example】

実施例1 イミド樹脂50体積%を、アラミド樹脂の不織布50体
積%の割合で含浸した半硬化状態のプリプレグに炭酸ガ
スレーザーで直径0.1mmのスルーホールを形成し、
そのホール内に銀をメッキした銅粉末を含む銅ペースト
を充填してスルーホール導体を形成した(絶縁シート
A)。
Example 1 A prepreg in a semi-cured state in which 50% by volume of an imide resin was impregnated with 50% by volume of a nonwoven fabric of an aramid resin was used to form a through hole having a diameter of 0.1 mm with a carbon dioxide gas laser.
The holes were filled with a copper paste containing copper powder plated with silver to form through-hole conductors (insulating sheet A).

【0043】また、イミド樹脂50体積%、シリカ粉末
50体積%の割合からなるワニス状態の樹脂と粉末を混
合しドクターブレード法で絶縁シートにパンチングで直
径0.1mmのスルーホールを形成し、そのホール内に
銀をメッキした銅粉末を含む銅ペーストを充填してスル
ーホール導体を形成した(絶縁シートB)。
Also, a resin in a varnish state consisting of 50% by volume of imide resin and 50% by volume of silica powder and powder were mixed, and punched into an insulating sheet by a doctor blade method to form a through hole having a diameter of 0.1 mm. The holes were filled with a copper paste containing copper powder plated with silver to form through-hole conductors (insulating sheet B).

【0044】一方、ポリエチレンテレフタレート(PE
T)樹脂からなる樹脂フィルムの表面に接着剤を塗布し
て粘着性をもたせ、厚さ12μm、表面粗さ0.8μm
の銅箔を一面に接着した。その後、コンデンサ素子形成
箇所以外の領域をマスクして、その樹脂フィルムを真空
容器内に設置しスパッタリングにより表面に10μmの
チタン酸バリウムからなる誘電体層を形成した。さらに
その誘電体層の表面に1μmの厚みの銅からなる電極を
形成した。
On the other hand, polyethylene terephthalate (PE)
T) An adhesive is applied to the surface of a resin film made of a resin to impart tackiness, and the thickness is 12 μm and the surface roughness is 0.8 μm.
Was adhered to one surface. Thereafter, a region other than the capacitor element forming portion was masked, the resin film was placed in a vacuum vessel, and a 10 μm-thick dielectric layer made of barium titanate was formed on the surface by sputtering. Further, an electrode made of copper having a thickness of 1 μm was formed on the surface of the dielectric layer.

【0045】その後、金属箔に対して、フォトレジスト
を塗布し露光現像を行った後、塩化第二鉄溶液中に浸漬
して非パターン部をエッチング除去して配線回路層を形
成した。なお、作製した配線回路層は、線幅が60μ
m、配線と配線との間隔が60μmの微細なパターンで
ある。
Thereafter, a photoresist was applied to the metal foil, exposed and developed, and then immersed in a ferric chloride solution to remove non-pattern portions by etching to form a wiring circuit layer. The manufactured wiring circuit layer has a line width of 60 μm.
m, a fine pattern with a distance between wirings of 60 μm.

【0046】そして、スルーホール導体を形成した絶縁
シートAに、前記コンデンサ素子および配線回路層を形
成した樹脂フィルムを位置決めして50kg/cm2
圧力下で積層圧着して、樹脂フィルムのみを剥離してプ
リプレグにコンデンサ素子および配線回路層を同時に転
写して配線層A1を形成した。また、同様に絶縁シート
Aにそれぞれ配線回路層を形成し、配線層A2、A3を
作製した。
Then, the resin film on which the capacitor element and the wiring circuit layer are formed is positioned on the insulating sheet A on which the through-hole conductor is formed, and laminated and pressed under a pressure of 50 kg / cm 2 to peel off only the resin film. Then, the capacitor element and the wiring circuit layer were simultaneously transferred to the prepreg to form a wiring layer A1. Similarly, a wiring circuit layer was formed on each of the insulating sheets A, and wiring layers A2 and A3 were produced.

【0047】また、上記と同様にして、スルーホール導
体を形成した絶縁シートBにも、銅箔からなる配線回路
層を転写して形成して、配線層B1、B2を作製した。
In the same manner as described above, a wiring circuit layer made of copper foil was transferred to and formed on the insulating sheet B on which the through-hole conductor was formed, and wiring layers B1 and B2 were produced.

【0048】そして、上記配線層A1,A2,A3の積
層体を中心に、その両側に配線層B1,B2をそれぞれ
重ねて積層し、50kg/cm2 の圧力で圧着し、20
0℃で1時間加熱してその積層物を一括して完全硬化さ
せて多層配線基板を作製した。
Then, the wiring layers B1 and B2 are stacked on both sides of the laminate of the wiring layers A1, A2 and A3, respectively, and the two layers are laminated and pressed under a pressure of 50 kg / cm 2.
The laminate was heated at 0 ° C. for one hour to completely cure the laminate at once, thereby producing a multilayer wiring board.

【0049】得られた多層配線基板に対して、断面にお
ける配線回路層やスルーホール導体の形成付近を観察し
た結果、配線回路層とスルーホール導体とは良好な接続
状態であり、各配線間の導通テストを行った結果、配線
の断線も認められなかった。
As a result of observing the vicinity of the formation of the wiring circuit layer and the through-hole conductor in the cross section of the obtained multilayer wiring board, the wiring circuit layer and the through-hole conductor were in a good connection state, and the As a result of the continuity test, no disconnection of the wiring was observed.

【0050】また、コンデンサ素子としての特性も良好
であった。
The characteristics as a capacitor element were also good.

【0051】得られた多層配線基板を湿度85%、温度
85℃の高温多湿雰囲気に100時間放置したが、目視
で判別できる程度の変化は生じていなかった。1000
時間放置後、周辺部にわずかな層の剥離が認められた。
The obtained multilayer wiring board was left for 100 hours in a high-temperature and high-humidity atmosphere at a humidity of 85% and a temperature of 85 ° C., but no change was observed to the extent that it could be visually discriminated. 1000
After leaving for a while, slight peeling of the layer was observed at the periphery.

【0052】実施例2 ポリアミノビスマレイミド樹脂55体積%とアラミド不
織布45体積%からなるプリプレグに炭酸ガスレーザに
より直径0.1mmのスルーホールを形成しそのホール
内に粒径約5μmの銀をメッキした銅粉末からなる銅ペ
ーストを充填した(絶縁シートA)。
Example 2 Copper having a diameter of 0.1 mm was formed in a prepreg composed of 55% by volume of polyaminobismaleimide resin and 45% by volume of aramid non-woven fabric by a carbon dioxide laser, and silver having a particle size of about 5 μm was plated in the hole. A copper paste made of powder was filled (insulating sheet A).

【0053】また、ポリアミノビスマレイミド樹脂50
体積%、シリカ粉末50体積%の割合でとなるよう、ワ
ニス状態の樹脂と粉末を混合しドクターブレード法で作
製したシート状絶縁層にパンチングで直径0.1mmの
スルーホールを形成し、そのホール内に銀をメッキした
銅粉末を含む銅ペーストを充填してスルーホール導体を
形成した(絶縁シートB)。
The polyaminobismaleimide resin 50
A varnished resin and powder were mixed so that the volume ratio was 50% by volume and the silica powder was 50% by volume, and a through hole having a diameter of 0.1 mm was formed by punching in a sheet-like insulating layer produced by a doctor blade method. The inside was filled with a copper paste containing copper powder plated with silver to form a through-hole conductor (insulating sheet B).

【0054】厚さ18μmの銅箔の表面にチタン酸バリ
ウムのアルコキシド溶液を塗布し、乾燥と塗布を繰り返
した後、500℃で熱処理して誘電体層を形成し、さら
にその上に銅箔の電極を貼り付けた全体厚み100μm
のフィルムコンデンサ素子を作製し、これを所定の容量
となるようにカットした。
An alkoxide solution of barium titanate is applied to the surface of a copper foil having a thickness of 18 μm, and after repeating drying and application, a heat treatment is performed at 500 ° C. to form a dielectric layer. Total thickness 100μm with electrodes attached
Was prepared and cut to a predetermined capacity.

【0055】そして、前記絶縁シートAと、前記絶縁シ
ートBとの間に、上記のフィルムコンデンサ素子を配設
して、上下から挟み込んで50kg/cm2 の圧力で積
層圧着して、200℃で1時間加熱してその積層物を一
括して完全硬化させて多層配線基板を作製した。
Then, the above-described film capacitor element is disposed between the insulating sheet A and the insulating sheet B, sandwiched from above and below, and laminated and pressed at a pressure of 50 kg / cm 2 at 200 ° C. The laminate was heated for one hour and completely cured at once to produce a multilayer wiring board.

【0056】得られた多層配線基板に対して、断面にお
ける配線回路層やスルーホール導体の形成付近を観察し
た結果、配線回路層とスルーホール導体とは良好な接続
状態であり、各配線間の導通テストを行った結果、配線
の断線も認められなかった。
As a result of observing the vicinity of the formation of the wiring circuit layer and the through-hole conductor in the cross section of the obtained multilayer wiring board, the wiring circuit layer and the through-hole conductor were in a good connection state, and the connection between each wiring was good. As a result of the continuity test, no disconnection of the wiring was observed.

【0057】またコンデンサ素子も良好な特性を有し、
所定の容量が得られた。得られた多層配線基板を湿度8
5%、温度85℃の高温多湿雰囲気に100時間放置し
たが、目視で判別できる程度の変化は生じていなかっ
た。
The capacitor element also has good characteristics,
The desired volume was obtained. The obtained multilayer wiring board was subjected to a humidity of 8
It was left in a hot and humid atmosphere of 5% and a temperature of 85 ° C. for 100 hours, but no change that could be visually recognized was generated.

【0058】[0058]

【発明の効果】以上詳述したとおり、本発明によれば、
複数の絶縁層が積層されてなる絶縁基板における絶縁層
間に、一対の電極間に誘電体層が挟持されたコンデンサ
素子を形成することができる結果、絶縁基板の特性や配
線基板の構造を格別に変更することなく、簡便な方法に
よってコンデンサ素子を内蔵した配線基板を作製するこ
とができる。
As described in detail above, according to the present invention,
Capacitor elements in which a dielectric layer is sandwiched between a pair of electrodes can be formed between insulating layers of an insulating substrate in which a plurality of insulating layers are stacked. As a result, the characteristics of the insulating substrate and the structure of the wiring substrate are exceptionally improved. A wiring board incorporating a capacitor element can be manufactured by a simple method without any change.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の多層配線基板の製造方法を説明するた
めの工程図である。
FIG. 1 is a process chart for explaining a method for manufacturing a multilayer wiring board of the present invention.

【図2】本発明の多層配線基板の製造方法において、コ
ンデンサ素子を形成するための工程図である。
FIG. 2 is a process diagram for forming a capacitor element in the method for manufacturing a multilayer wiring board of the present invention.

【図3】従来のコンデンサ素子を内蔵した多層配線基板
の構造を説明するための概略断面図である。
FIG. 3 is a schematic cross-sectional view for explaining the structure of a conventional multilayer wiring board having a built-in capacitor element.

【符号の説明】[Explanation of symbols]

1 絶縁シート 2 スルーホール導体 3 配線回路層 4,5 電極 6 誘電体層 7 樹脂フィルム 8,9 表面電極 10、11 スルーホール導体 DESCRIPTION OF SYMBOLS 1 Insulation sheet 2 Through-hole conductor 3 Wiring circuit layer 4,5 Electrode 6 Dielectric layer 7 Resin film 8,9 Surface electrode 10,11 Through-hole conductor

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】少なくとも有機樹脂を含有する複数の絶縁
層が積層されてなる絶縁基板と、該絶縁基板の少なくと
も前記絶縁層間に配設された配線回路層とを具備する多
層配線基板において、前記絶縁層間に、一対の電極間に
誘電体層が挟持されたコンデンサ素子を埋設したことを
特徴とする多層配線基板。
1. A multilayer wiring board comprising: an insulating substrate formed by laminating a plurality of insulating layers containing at least an organic resin; and a wiring circuit layer provided at least between the insulating layers of the insulating substrate. A multilayer wiring board comprising a capacitor element in which a dielectric layer is sandwiched between a pair of electrodes between insulating layers.
【請求項2】基板表面に一対の表面電極を設け、該表面
電極と前記コンデンサ素子の前記一対の電極とを、少な
くとも一対のスルーホール導体によりそれぞれ電気的に
接続したことを特徴とする請求項1記載の多層配線基
板。
2. A method according to claim 1, wherein a pair of surface electrodes is provided on the surface of the substrate, and the surface electrodes and the pair of electrodes of the capacitor element are electrically connected by at least a pair of through-hole conductors. 2. The multilayer wiring board according to 1.
【請求項3】フィルムの表面に、一対の電極間に誘電体
層が挟持されたコンデンサ素子を形成する工程と、熱硬
化性樹脂を含む未硬化または半硬化状態の絶縁シートの
表面に配線回路層を形成する工程と、前記フィルム表面
に形成されたコンデンサ素子を前記絶縁シート表面に加
圧しながら転写して、前記コンデンサ素子を前記絶縁シ
ート表面に埋め込む工程と、前記コンデンサ素子が埋め
込まれた前記絶縁シート表面に、熱硬化性樹脂を含む未
硬化または半硬化状態の他の絶縁シートを積層圧着する
工程と、前記積層物を加熱処理して、前記積層物を一括
して硬化する工程と、を具備することを特徴とする多層
配線基板の製造方法。
3. A step of forming a capacitor element having a dielectric layer sandwiched between a pair of electrodes on a surface of a film, and a step of forming a wiring circuit on an uncured or semi-cured insulating sheet containing a thermosetting resin. Forming a layer, transferring the capacitor element formed on the film surface to the insulating sheet surface while applying pressure, and embedding the capacitor element on the insulating sheet surface; and embedding the capacitor element in the insulating sheet surface. On the surface of the insulating sheet, a step of laminating and pressing another insulating sheet containing an uncured or semi-cured state containing a thermosetting resin, and a step of heat-treating the laminate to collectively cure the laminate, A method for manufacturing a multilayer wiring board, comprising:
【請求項4】前記配線回路層が、フィルム表面に被着さ
れた金属箔をエッチングして配線回路層を形成した後、
該フィルムから前記絶縁シートに転写して形成すること
を特徴とする請求項3記載の多層配線基板の製造方法。
4. The wiring circuit layer is formed by etching a metal foil applied to a film surface to form a wiring circuit layer.
4. The method according to claim 3, wherein the film is transferred from the film to the insulating sheet.
【請求項5】前記配線回路層の前記絶縁シートへの転写
と、前記コンデンサ素子の前記絶縁シートへの転写を同
時に行うことを特徴とする請求項4記載の多層配線基板
の製造方法。
5. The method according to claim 4, wherein the transfer of the wiring circuit layer to the insulating sheet and the transfer of the capacitor element to the insulating sheet are simultaneously performed.
【請求項6】熱硬化性樹脂を含む未硬化または半硬化状
態の第1の絶縁シートの表面に配線回路層を形成する工
程と、熱硬化性樹脂を含む未硬化または半硬化状態の第
2の絶縁シートの表面に配線回路層を形成する工程と、
配線回路層が形成された前記第1の絶縁シートおよび前
記第2の絶縁シートを、一対の電極間に誘電体層が挟持
されたコンデンサ素子を所定位置に介在させて加圧しな
がら積層し、前記コンデンサ素子を前記絶縁シート間に
埋め込む工程と、前記積層物を加熱処理して、前記積層
物を一括して硬化させる工程と、を具備することを特徴
とする多層配線基板の製造方法。
6. A step of forming a wiring circuit layer on the surface of an uncured or semi-cured first insulating sheet containing a thermosetting resin, and a step of forming a second uncured or semi-cured state containing a thermosetting resin. Forming a wiring circuit layer on the surface of the insulating sheet,
The first insulating sheet and the second insulating sheet on which a wiring circuit layer is formed are laminated while pressing a capacitor element having a dielectric layer sandwiched between a pair of electrodes at a predetermined position, and laminating the first insulating sheet and the second insulating sheet. A method for manufacturing a multilayer wiring board, comprising: a step of embedding a capacitor element between the insulating sheets; and a step of heat-treating the laminate to collectively cure the laminate.
JP17383997A 1997-06-30 1997-06-30 Method for manufacturing multilayer wiring board Expired - Fee Related JP3199664B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17383997A JP3199664B2 (en) 1997-06-30 1997-06-30 Method for manufacturing multilayer wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17383997A JP3199664B2 (en) 1997-06-30 1997-06-30 Method for manufacturing multilayer wiring board

Publications (2)

Publication Number Publication Date
JPH1126943A true JPH1126943A (en) 1999-01-29
JP3199664B2 JP3199664B2 (en) 2001-08-20

Family

ID=15968123

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17383997A Expired - Fee Related JP3199664B2 (en) 1997-06-30 1997-06-30 Method for manufacturing multilayer wiring board

Country Status (1)

Country Link
JP (1) JP3199664B2 (en)

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1265466A2 (en) * 2001-06-05 2002-12-11 Dai Nippon Printing Co., Ltd. Method for fabrication wiring board provided with passive element and wiring board provided with passive element
JP2003521119A (en) * 2000-01-25 2003-07-08 スリーエム イノベイティブ プロパティズ カンパニー Electronic package with integrated capacitors
US6625037B2 (en) 1997-11-25 2003-09-23 Matsushita Electric Industrial Co., Ltd. Printed circuit board and method manufacturing the same
WO2004089049A1 (en) * 2003-03-28 2004-10-14 Tdk Corporation Multilayer substrate and method for producing same
JP2004327905A (en) * 2003-04-28 2004-11-18 Doshisha Method and apparatus for forming thin film material
US7013561B2 (en) 1999-11-12 2006-03-21 Matsushita Electric Industrial Co., Ltd. Method for producing a capacitor-embedded circuit board
JP2006210908A (en) * 2004-12-28 2006-08-10 Ngk Spark Plug Co Ltd Wiring board and manufacturing method thereof
JP2006229214A (en) * 2005-01-21 2006-08-31 Ngk Spark Plug Co Ltd Method for manufacturing wiring board
JP2006237132A (en) * 2005-02-23 2006-09-07 Ngk Spark Plug Co Ltd Wiring board and its production process
EP1737283A1 (en) * 2005-06-20 2006-12-27 E.I.Du pont de nemours and company Embedded capacitors, electronic devices comprising such capacitors and methods for making the same
CN1309285C (en) * 2001-11-26 2007-04-04 索尼公司 High frequency circuit block member, its manufacturing method, high refrequency module device and its manufaturing method
US7304248B2 (en) 2003-04-04 2007-12-04 Denso Corporation Multi-layer printed circuit board and method for manufacturing the same
KR100861618B1 (en) 2007-03-02 2008-10-07 삼성전기주식회사 Printed circuit board for improving tolerance of embedded capacitors, and process for manufacturing the same
WO2011086797A1 (en) * 2010-01-15 2011-07-21 三洋電機株式会社 Method of manufacturing substrate with built-in capacitor
WO2011086795A1 (en) * 2010-01-15 2011-07-21 三洋電機株式会社 Capacitor element and substrate with built-in capacitor
WO2012014648A1 (en) * 2010-07-30 2012-02-02 三洋電機株式会社 Substrate-embedded capacitor, capacitor-integrated substrate provided with same, and method for producing substrate-embedded capacitor

Cited By (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6625037B2 (en) 1997-11-25 2003-09-23 Matsushita Electric Industrial Co., Ltd. Printed circuit board and method manufacturing the same
US7068519B2 (en) 1997-11-25 2006-06-27 Matsushita Electric Industrial Co., Ltd. Printed circuit board and method manufacturing the same
US7013561B2 (en) 1999-11-12 2006-03-21 Matsushita Electric Industrial Co., Ltd. Method for producing a capacitor-embedded circuit board
JP2003521119A (en) * 2000-01-25 2003-07-08 スリーエム イノベイティブ プロパティズ カンパニー Electronic package with integrated capacitors
JP4878100B2 (en) * 2000-01-25 2012-02-15 スリーエム イノベイティブ プロパティズ カンパニー Electronic package with integrated capacitors
US7679925B2 (en) 2001-06-05 2010-03-16 Dai Nippon Printing Co., Ltd. Method for fabricating wiring board provided with passive element, and wiring board provided with passive element
EP2315510A3 (en) * 2001-06-05 2012-05-02 Dai Nippon Printing Co., Ltd. Wiring board provided with passive element
EP1265466A3 (en) * 2001-06-05 2004-07-21 Dai Nippon Printing Co., Ltd. Method for fabrication wiring board provided with passive element and wiring board provided with passive element
EP2315510A2 (en) 2001-06-05 2011-04-27 Dai Nippon Printing Co., Ltd. Wiring board provided with passive element
US7100276B2 (en) 2001-06-05 2006-09-05 Dai Nippon Printing Co., Ltd. Method for fabricating wiring board provided with passive element
EP1265466A2 (en) * 2001-06-05 2002-12-11 Dai Nippon Printing Co., Ltd. Method for fabrication wiring board provided with passive element and wiring board provided with passive element
US6872893B2 (en) 2001-06-05 2005-03-29 Dai Nippon Printing Co., Ltd. Wiring board provided with passive element and cone shaped bumps
CN1309285C (en) * 2001-11-26 2007-04-04 索尼公司 High frequency circuit block member, its manufacturing method, high refrequency module device and its manufaturing method
KR100755088B1 (en) 2003-03-28 2007-09-03 티디케이가부시기가이샤 Multilayered substrate and manufacturing method thereof
WO2004089049A1 (en) * 2003-03-28 2004-10-14 Tdk Corporation Multilayer substrate and method for producing same
US7304248B2 (en) 2003-04-04 2007-12-04 Denso Corporation Multi-layer printed circuit board and method for manufacturing the same
JP2004327905A (en) * 2003-04-28 2004-11-18 Doshisha Method and apparatus for forming thin film material
JP2006210908A (en) * 2004-12-28 2006-08-10 Ngk Spark Plug Co Ltd Wiring board and manufacturing method thereof
JP2006229214A (en) * 2005-01-21 2006-08-31 Ngk Spark Plug Co Ltd Method for manufacturing wiring board
JP2006237132A (en) * 2005-02-23 2006-09-07 Ngk Spark Plug Co Ltd Wiring board and its production process
JP4667070B2 (en) * 2005-02-23 2011-04-06 日本特殊陶業株式会社 Wiring board and method of manufacturing wiring board
EP1737283A1 (en) * 2005-06-20 2006-12-27 E.I.Du pont de nemours and company Embedded capacitors, electronic devices comprising such capacitors and methods for making the same
KR100861618B1 (en) 2007-03-02 2008-10-07 삼성전기주식회사 Printed circuit board for improving tolerance of embedded capacitors, and process for manufacturing the same
WO2011086797A1 (en) * 2010-01-15 2011-07-21 三洋電機株式会社 Method of manufacturing substrate with built-in capacitor
WO2011086795A1 (en) * 2010-01-15 2011-07-21 三洋電機株式会社 Capacitor element and substrate with built-in capacitor
WO2012014648A1 (en) * 2010-07-30 2012-02-02 三洋電機株式会社 Substrate-embedded capacitor, capacitor-integrated substrate provided with same, and method for producing substrate-embedded capacitor

Also Published As

Publication number Publication date
JP3199664B2 (en) 2001-08-20

Similar Documents

Publication Publication Date Title
JP3051700B2 (en) Method of manufacturing multilayer wiring board with built-in element
JP3236818B2 (en) Method for manufacturing multilayer wiring board with built-in element
KR100907045B1 (en) Passive device structure
JP3199664B2 (en) Method for manufacturing multilayer wiring board
JP3547423B2 (en) Component built-in module and manufacturing method thereof
JPH11126978A (en) Multilayered wiring board
JP3207174B2 (en) Wiring board mounted with electric element and method of manufacturing the same
US7755165B2 (en) iTFC with optimized C(T)
JP2004007006A (en) Multilayer wiring board
JP2002043752A (en) Wiring board, multilayer wiring board, and their manufacturing method
JPH1174648A (en) Wiring board
JP2002198654A (en) Electric element built-in wiring board and method of manufacturing the same
JP2000353875A (en) Carrier board with built-in capacitor and its manufacture
JPH0786743A (en) Manufacture of multilayer ceramic board
JP3071764B2 (en) Film with metal foil and method of manufacturing wiring board using the same
JP2001339164A (en) Wiring board incorporating capacitor element
JP2000183526A (en) Multilayer wiring board and manufacture of the same
JP2001244367A (en) Wiring board with built-in electric element
JP3063427B2 (en) Circuit board and method of forming the same
TW200931458A (en) Capacitors and method for manufacturing the same
JP2002344145A (en) Multilayer wiring board and its manufacturing method
WO2007010705A1 (en) Capacitor, method for manufacturing capacitor, substrate with built-in capacitor, and method for manufacturing substrate with built-in capacitor
JP2002141628A (en) Wiring board
JP3232002B2 (en) Wiring board
JP2001102754A (en) Multilayer wiring board

Legal Events

Date Code Title Description
FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090615

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090615

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100615

Year of fee payment: 9

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110615

Year of fee payment: 10

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120615

Year of fee payment: 11

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130615

Year of fee payment: 12

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140615

Year of fee payment: 13

LAPS Cancellation because of no payment of annual fees