JPH11265315A - 様々なｄｒａｍバンクサイズと複数のインターリービング機構とをサポートする高速でコンパクトなアドレスビット経路指定機構 - Google Patents

様々なｄｒａｍバンクサイズと複数のインターリービング機構とをサポートする高速でコンパクトなアドレスビット経路指定機構

Info

Publication number
JPH11265315A
JPH11265315A JP10303740A JP30374098A JPH11265315A JP H11265315 A JPH11265315 A JP H11265315A JP 10303740 A JP10303740 A JP 10303740A JP 30374098 A JP30374098 A JP 30374098A JP H11265315 A JPH11265315 A JP H11265315A
Authority
JP
Japan
Prior art keywords
bits
bit
address
bank
rank
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10303740A
Other languages
English (en)
Japanese (ja)
Other versions
JPH11265315A5 (enExample
Inventor
Gapta Anurag
アヌラグ・ガプタ
Pikesley Scott
スコット・ピケスリー
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HP Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of JPH11265315A publication Critical patent/JPH11265315A/ja
Publication of JPH11265315A5 publication Critical patent/JPH11265315A5/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0607—Interleaved addressing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0215—Addressing or allocation; Relocation with look ahead addressing means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G06F12/0882—Page mode

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Memory System (AREA)
  • Dram (AREA)
JP10303740A 1997-10-31 1998-10-26 様々なｄｒａｍバンクサイズと複数のインターリービング機構とをサポートする高速でコンパクトなアドレスビット経路指定機構 Pending JPH11265315A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/962,490 US6108745A (en) 1997-10-31 1997-10-31 Fast and compact address bit routing scheme that supports various DRAM bank sizes and multiple interleaving schemes
US962490 1997-10-31

Publications (2)

Publication Number Publication Date
JPH11265315A true JPH11265315A (ja) 1999-09-28
JPH11265315A5 JPH11265315A5 (enExample) 2005-12-02

Family

ID=25505941

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10303740A Pending JPH11265315A (ja) 1997-10-31 1998-10-26 様々なｄｒａｍバンクサイズと複数のインターリービング機構とをサポートする高速でコンパクトなアドレスビット経路指定機構

Country Status (2)

Country Link
US (1) US6108745A (enExample)
JP (1) JPH11265315A (enExample)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002175216A (ja) * 2000-09-29 2002-06-21 Intel Corp 行及び列コマンドを同時供給するためのシステム及び方法
JP2008016024A (ja) * 2006-06-30 2008-01-24 Seagate Technology Llc キャッシュされたデータのダイナミック適応フラッシング
JP2008046989A (ja) * 2006-08-18 2008-02-28 Fujitsu Ltd メモリ制御装置
CN109783395A (zh) * 2017-11-15 2019-05-21 阿里巴巴集团控股有限公司 内存访问方法、交换芯片、内存模组及电子设备

Families Citing this family (54)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0778106A (ja) * 1993-09-08 1995-03-20 Hitachi Ltd データ処理システム
EP0931290A1 (en) * 1997-03-21 1999-07-28 International Business Machines Corporation Address mapping for system memory
US6272594B1 (en) * 1998-07-31 2001-08-07 Hewlett-Packard Company Method and apparatus for determining interleaving schemes in a computer system that supports multiple interleaving schemes
US6389514B1 (en) * 1999-03-25 2002-05-14 Hewlett-Packard Company Method and computer system for speculatively closing pages in memory
US6543013B1 (en) * 1999-04-14 2003-04-01 Nortel Networks Limited Intra-row permutation for turbo code
US6477613B1 (en) * 1999-06-30 2002-11-05 International Business Machines Corporation Cache index based system address bus
US6366983B1 (en) * 1999-09-14 2002-04-02 Intel Corporation Method and system for symmetric memory population
US6449706B1 (en) * 1999-12-22 2002-09-10 Intel Corporation Method and apparatus for accessing unaligned data
US6622201B1 (en) * 2000-01-28 2003-09-16 Advanced Micro Devices, Inc. Chained array of sequential access memories enabling continuous read
US6480943B1 (en) * 2000-04-29 2002-11-12 Hewlett-Packard Company Memory address interleaving and offset bits for cell interleaving of memory
US6928520B2 (en) * 2000-04-30 2005-08-09 Hewlett-Packard Development Company, L.P. Memory controller that provides memory line caching and memory transaction coherency by using at least one memory controller agent
JP2001338497A (ja) * 2000-05-24 2001-12-07 Fujitsu Ltd メモリ試験方法
DE10034854A1 (de) * 2000-07-18 2002-02-14 Infineon Technologies Ag Verfahren und Vorrichtung zur Erzeugung digitaler Signalmuster
JP2002063069A (ja) 2000-08-21 2002-02-28 Hitachi Ltd メモリ制御装置、データ処理システム及び半導体装置
US6493814B2 (en) * 2001-03-08 2002-12-10 International Business Machines Corporation Reducing resource collisions associated with memory units in a multi-level hierarchy memory system
US6625081B2 (en) 2001-08-13 2003-09-23 Micron Technology, Inc. Synchronous flash memory with virtual segment architecture
WO2004006103A1 (en) * 2002-07-09 2004-01-15 Globespanvirata Incorporated Method and system for improving access latency of multiple bank devices
US7159066B2 (en) * 2002-08-27 2007-01-02 Intel Corporation Precharge suggestion
DE10343525B4 (de) * 2002-09-27 2011-06-16 Qimonda Ag Verfahren zum Betreiben von Halbleiterbausteinen, Steuervorrichtung für Halbleiterbausteine und Anordnung zum Betreiben von Speicherbausteinen
KR100506448B1 (ko) * 2002-12-27 2005-08-08 주식회사 하이닉스반도체 불휘발성 강유전체 메모리를 이용한 인터리브 제어 장치
US6961281B2 (en) * 2003-09-12 2005-11-01 Sun Microsystems, Inc. Single rank memory module for use in a two-rank memory module system
US8250295B2 (en) * 2004-01-05 2012-08-21 Smart Modular Technologies, Inc. Multi-rank memory module that emulates a memory module having a different number of ranks
US7289386B2 (en) * 2004-03-05 2007-10-30 Netlist, Inc. Memory module decoder
US7532537B2 (en) * 2004-03-05 2009-05-12 Netlist, Inc. Memory module with a circuit providing load isolation and memory domain translation
US7916574B1 (en) 2004-03-05 2011-03-29 Netlist, Inc. Circuit providing load isolation and memory domain translation for memory module
KR100608913B1 (ko) * 2004-11-10 2006-08-09 한국전자통신연구원 직교주파수분할다중(ｏｆｄｍ) 송신기에서의 인터리빙장치 및 방법
US7272699B2 (en) * 2004-11-12 2007-09-18 International Business Machines Corporation Flexible sub-column to sub-row mapping for sub-page activation in XDR™ DRAMs
US7287145B1 (en) * 2004-12-13 2007-10-23 Nvidia Corporation System, apparatus and method for reclaiming memory holes in memory composed of identically-sized memory devices
US8443162B2 (en) * 2005-01-21 2013-05-14 Qualcomm Incorporated Methods and apparatus for dynamically managing banked memory
KR100712505B1 (ko) * 2005-02-12 2007-05-02 삼성전자주식회사 메모리 어드레스 생성회로 및 이를 구비하는 메모리 콘트롤러
US7339840B2 (en) * 2005-05-13 2008-03-04 Infineon Technologies Ag Memory system and method of accessing memory chips of a memory system
US7184360B2 (en) * 2005-06-15 2007-02-27 Infineon Technologies, Ag High-speed interface circuit for semiconductor memory chips and memory system including semiconductor memory chips
US7475192B2 (en) * 2005-07-12 2009-01-06 International Business Machines Corporation Cache organization for power optimized memory access
EP1969564A2 (en) * 2005-12-20 2008-09-17 University of Maryland, Baltimore Method and apparatus for accelerated elastic registration of multiple scans of internal properties of a body
US8078791B1 (en) 2007-04-16 2011-12-13 Juniper Networks, Inc. Ordering refresh requests to memory
US8006032B2 (en) * 2007-08-22 2011-08-23 Globalfoundries Inc. Optimal solution to control data channels
US8417870B2 (en) 2009-07-16 2013-04-09 Netlist, Inc. System and method of increasing addressable memory space on a memory board
US8516185B2 (en) 2009-07-16 2013-08-20 Netlist, Inc. System and method utilizing distributed byte-wise buffers on a memory module
US8154901B1 (en) 2008-04-14 2012-04-10 Netlist, Inc. Circuit providing load isolation and noise reduction
US9128632B2 (en) 2009-07-16 2015-09-08 Netlist, Inc. Memory module with distributed data buffers and method of operation
US8972620B2 (en) * 2010-07-02 2015-03-03 Dell Products L.P. Methods and systems to simplify population of modular components in an information handling system
KR102273094B1 (ko) 2013-05-16 2021-07-05 어드밴스드 마이크로 디바이시즈, 인코포레이티드 영역-특정 메모리 액세스 스케줄링을 가진 메모리 시스템
EP3028153B1 (en) 2013-07-27 2019-03-06 Netlist, Inc. Memory module with local synchronization
GB2519349B (en) 2013-10-18 2018-06-27 Stmicroelectronics Grenoble2 Sas Method and apparatus for supporting the use of interleaved memory regions
US9837135B2 (en) * 2016-03-03 2017-12-05 Samsung Electronics Co., Ltd. Methods for addressing high capacity SDRAM-like memory without increasing pin cost
US10565335B2 (en) 2016-03-04 2020-02-18 Montana Systems Inc. Event-driven design simulation
US10268478B2 (en) * 2016-03-04 2019-04-23 Montana Systems Inc. Event-driven design simulation
US10747930B2 (en) 2016-03-04 2020-08-18 Montana Systems Inc. Event-driven design simulation
US10789405B2 (en) 2016-03-04 2020-09-29 Montana Systems Inc. Event-driven design simulation
US11275582B2 (en) 2017-01-06 2022-03-15 Montana Systems Inc. Event-driven design simulation
US9971691B2 (en) * 2016-09-12 2018-05-15 Intel Corporation Selevtive application of interleave based on type of data to be stored in memory
CN108604206B (zh) * 2016-11-23 2021-10-22 华为技术有限公司 一种内存分配方法和设备
US10755014B2 (en) 2018-03-14 2020-08-25 Montana Systems Inc. Event-driven design simulation
US12271627B2 (en) 2022-09-30 2025-04-08 Advanced Micro Devices, Inc. Off-chip memory shared by multiple processing nodes

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5390308A (en) * 1992-04-15 1995-02-14 Rambus, Inc. Method and apparatus for address mapping of dynamic random access memory
US5696917A (en) * 1994-06-03 1997-12-09 Intel Corporation Method and apparatus for performing burst read operations in an asynchronous nonvolatile memory
US5890221A (en) * 1994-10-05 1999-03-30 International Business Machines Corporation Method and system for offset miss sequence handling in a data cache array having multiple content addressable field per cache line utilizing an MRU bit
US5761695A (en) * 1995-09-19 1998-06-02 Hitachi, Ltd. Cache memory control method and apparatus, and method and apparatus for controlling memory capable of interleave control
US5745913A (en) * 1996-08-05 1998-04-28 Exponential Technology, Inc. Multi-processor DRAM controller that prioritizes row-miss requests to stale banks

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002175216A (ja) * 2000-09-29 2002-06-21 Intel Corp 行及び列コマンドを同時供給するためのシステム及び方法
JP2008016024A (ja) * 2006-06-30 2008-01-24 Seagate Technology Llc キャッシュされたデータのダイナミック適応フラッシング
JP2008046989A (ja) * 2006-08-18 2008-02-28 Fujitsu Ltd メモリ制御装置
US8706945B2 (en) 2006-08-18 2014-04-22 Fujitsu Limited Memory control device
CN109783395A (zh) * 2017-11-15 2019-05-21 阿里巴巴集团控股有限公司 内存访问方法、交换芯片、内存模组及电子设备
CN109783395B (zh) * 2017-11-15 2023-03-31 阿里巴巴集团控股有限公司 内存访问方法、交换芯片、内存模组及电子设备

Also Published As

Publication number Publication date
US6108745A (en) 2000-08-22

Similar Documents

Publication Publication Date Title
JPH11265315A (ja) 様々なｄｒａｍバンクサイズと複数のインターリービング機構とをサポートする高速でコンパクトなアドレスビット経路指定機構
JP3715837B2 (ja) バンク・ビット割り当て方法
US6070227A (en) Main memory bank indexing scheme that optimizes consecutive page hits by linking main memory bank address organization to cache memory address organization
US5519664A (en) Dynamic random access memory persistent page implemented as processor register sets
US5111386A (en) Cache contained type semiconductor memory device and operating method therefor
US6389514B1 (en) Method and computer system for speculatively closing pages in memory
US5509132A (en) Semiconductor memory device having an SRAM as a cache memory integrated on the same chip and operating method thereof
US5226147A (en) Semiconductor memory device for simple cache system
US5590078A (en) Method of and apparatus for improved dynamic random access memory (DRAM) providing increased data bandwidth and addressing range for current DRAM devices and/or equivalent bandwidth and addressing range for smaller DRAM devices
US5025421A (en) Single port dual RAM
US6442098B1 (en) High performance multi-bank compact synchronous DRAM architecture
US8730759B2 (en) Devices and system providing reduced quantity of interconnections
EP0549139A1 (en) Programmable memory timing
GB2193017A (en) Improved memory access system
JPH02297791A (ja) メモリ・サブシステム
KR20010093642A (ko) 개선된 메모리 시스템 장치 및 방법
JP4199658B2 (ja) 読出及び書込動作でバースト順序が異なるアドレッシングを行うメモリデバイス
US7340584B2 (en) Sequential nibble burst ordering for data
JP2648548B2 (ja) コンピュータ・メモリ
US6535966B1 (en) System and method for using a page tracking buffer to reduce main memory latency in a computer system
US6459647B1 (en) Split-bank architecture for high performance SDRAMs
US4796222A (en) Memory structure for nonsequential storage of block bytes in multi-bit chips
JP2000268560A (ja) 半導体集積回路装置
US6101579A (en) Multi-port memory device having masking registers
JPWO2002080180A1 (ja) Ｄｒａｍ及びアクセス方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20051011

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20051011

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20081017

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20081028

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20090128

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20090202

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20090707