JPH11265315A5 - - Google Patents

Info

Publication number
JPH11265315A5
JPH11265315A5 JP1998303740A JP30374098A JPH11265315A5 JP H11265315 A5 JPH11265315 A5 JP H11265315A5 JP 1998303740 A JP1998303740 A JP 1998303740A JP 30374098 A JP30374098 A JP 30374098A JP H11265315 A5 JPH11265315 A5 JP H11265315A5
Authority
JP
Japan
Prior art keywords
address
bits
bit
rank
bank
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1998303740A
Other languages
English (en)
Japanese (ja)
Other versions
JPH11265315A (ja
Filing date
Publication date
Priority claimed from US08/962,490 external-priority patent/US6108745A/en
Application filed filed Critical
Publication of JPH11265315A publication Critical patent/JPH11265315A/ja
Publication of JPH11265315A5 publication Critical patent/JPH11265315A5/ja
Pending legal-status Critical Current

Links

JP10303740A 1997-10-31 1998-10-26 様々なdramバンクサイズと複数のインターリービング機構とをサポートする高速でコンパクトなアドレスビット経路指定機構 Pending JPH11265315A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/962,490 US6108745A (en) 1997-10-31 1997-10-31 Fast and compact address bit routing scheme that supports various DRAM bank sizes and multiple interleaving schemes
US962490 1997-10-31

Publications (2)

Publication Number Publication Date
JPH11265315A JPH11265315A (ja) 1999-09-28
JPH11265315A5 true JPH11265315A5 (enExample) 2005-12-02

Family

ID=25505941

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10303740A Pending JPH11265315A (ja) 1997-10-31 1998-10-26 様々なdramバンクサイズと複数のインターリービング機構とをサポートする高速でコンパクトなアドレスビット経路指定機構

Country Status (2)

Country Link
US (1) US6108745A (enExample)
JP (1) JPH11265315A (enExample)

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US8250295B2 (en) * 2004-01-05 2012-08-21 Smart Modular Technologies, Inc. Multi-rank memory module that emulates a memory module having a different number of ranks
US7289386B2 (en) * 2004-03-05 2007-10-30 Netlist, Inc. Memory module decoder
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US7916574B1 (en) 2004-03-05 2011-03-29 Netlist, Inc. Circuit providing load isolation and memory domain translation for memory module
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US7272699B2 (en) * 2004-11-12 2007-09-18 International Business Machines Corporation Flexible sub-column to sub-row mapping for sub-page activation in XDR™ DRAMs
US7287145B1 (en) * 2004-12-13 2007-10-23 Nvidia Corporation System, apparatus and method for reclaiming memory holes in memory composed of identically-sized memory devices
US8443162B2 (en) * 2005-01-21 2013-05-14 Qualcomm Incorporated Methods and apparatus for dynamically managing banked memory
KR100712505B1 (ko) * 2005-02-12 2007-05-02 삼성전자주식회사 메모리 어드레스 생성회로 및 이를 구비하는 메모리 콘트롤러
US7339840B2 (en) * 2005-05-13 2008-03-04 Infineon Technologies Ag Memory system and method of accessing memory chips of a memory system
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US8154901B1 (en) 2008-04-14 2012-04-10 Netlist, Inc. Circuit providing load isolation and noise reduction
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EP3028153B1 (en) 2013-07-27 2019-03-06 Netlist, Inc. Memory module with local synchronization
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US9837135B2 (en) * 2016-03-03 2017-12-05 Samsung Electronics Co., Ltd. Methods for addressing high capacity SDRAM-like memory without increasing pin cost
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US10789405B2 (en) 2016-03-04 2020-09-29 Montana Systems Inc. Event-driven design simulation
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CN109783395B (zh) * 2017-11-15 2023-03-31 阿里巴巴集团控股有限公司 内存访问方法、交换芯片、内存模组及电子设备
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