JPH11261032A - Dram element and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the capacity of a capacitor, by bringing the capacitor into contact with a second junction area, and containing the impurity area of a first conduction type forming the junction capacitor with the second junction area of a second conduction type. SOLUTION: A second interlayer insulating film 36 whose surface is flattened is formed on a first interlayer insulating film 32 containing a bit line 34. The second interlayer insulating film 36 and the first interlayer insulating film 32 are selectively etched and second contact holes 38 from which sources 28 are exposed are formed. Contact hole spacers 40 are formed on the inner walls of the second contact holes 38 for insulating a word line and a capacitor. The capacitor which is brought into contact with the sources 28 through the second contact holes is formed on the second interlayer insulating film 36 adjacent to the second contact holes. Thus, the capacity of the capacitor in a unit cell can securely be secured.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a DRAM device, and more particularly, to a DRAM device using an SOI (Silicon-On-Insulator) wafer and a method of manufacturing the same.

[0002]

2. Description of the Related Art In general, a DRAM (Dynamic Random Acce
(ss Memory) element is a unit cell composed of one transistor and one capacitor, a cell array unit arranged in a matrix, and driving the cell array unit to store data in each cell, or And a peripheral circuit unit that plays a role of reading data stored in the cell.

From the above, a capacitor has a structure in which a dielectric substance is interposed between two electrodes called a storage electrode and a plate electrode, and the larger the capacity, the better. The capacitance of a capacitor is generally inversely proportional to the distance between the electrodes, and is proportional to the product of the area of the electrodes and the dielectric constant of the dielectric material. Therefore, to increase the capacitance of the capacitor,
It is necessary to reduce the distance between the electrodes, increase the area of the electrodes, or use a dielectric material having a large dielectric constant.

However, there is a limit in reducing the distance between the electrodes, and research on manufacturing a high-capacitance capacitor has been carried out by using a dielectric material having a large dielectric constant,
Alternatively, a method of increasing the area of the electrode has been used. For example, a capacitor manufactured with a three-dimensional structure such as a pin (Fin) structure, a stack (Stack) structure, and a cylinder (Cylinder) structure has one form in which the electrode area is increased to increase the capacitance of the capacitor. is there.

[0005]

However, the above-mentioned 3)
The three-dimensional structure of the capacitor has disadvantages in that the shape thereof is complicated, the manufacturing process is difficult, and a step with the surrounding area is caused, so that the subsequent process is difficult.

An object of the present invention is to provide a DRAM device having an improved capacitor capacitance. Another object of the present invention is to provide a method of manufacturing a DRAM device having an improved capacitor capacitance.

[0007]

According to a first aspect of the present invention, there is provided a DRAM device comprising: an SOI wafer having a buried oxide film interposed between a supporting substrate and a device substrate of a first conductivity type; A word line formed on the device substrate of an SOI wafer; first and second bonding regions of a second conductivity type formed on the device substrate on both sides of the word line; and a contact with the first bonding region. A bit line, a capacitor in contact with the second junction region, and a second capacitor formed below the second junction region of the second conductivity type and forming a junction capacitor with the second junction region of the second conductivity type. And an impurity region of one conductivity type.

A method of manufacturing a DRAM device according to another aspect of the present invention includes providing an SOI wafer having a support substrate and a device substrate of a first conductivity type stacked with an oxide film interposed therebetween. Forming a field oxide film on the device substrate of the SOI wafer to define an active region, forming a word line in the active region of the device substrate, and activating the device substrate on both sides of the word line. Forming first and second junction regions of a second conductivity type in a region; forming a first interlayer insulating film on the device substrate including the word line; and selectively etching the first interlayer insulating film. Forming a first contact hole exposing the first junction region, and forming a first contact hole on the first contact hole and a first interlayer insulating film adjacent to the first contact hole. Forming a bit line in contact with the first junction region through the first contact hole; forming a second interlayer insulating film on the first interlayer insulating film including the bit line; Selectively etching a first interlayer insulating film to form a second contact hole exposing the second junction region drain; and ion-implanting a first conductivity type impurity into an active region of the device substrate. Forming an impurity region in contact with the second junction region below the second junction region; Forming a capacitor in contact with the two junction regions.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings. 1 to 4 are cross-sectional views illustrating a method of manufacturing a DRAM device according to an embodiment of the present invention. Referring to FIG. 1, an SOI (Silicon) in which a buried oxide film (Buried Oxide) 12 is interposed between a supporting substrate 10 for supporting the whole and a device substrate 14 for forming a device.
-ON-Insulator (hereinafter referred to as SOI). Here, the device substrate 14 is of a first conductivity type, for example, a P-type substrate.

An active region is defined by forming a field oxide film 22 on the device substrate 14. A gate oxide film and a polycrystalline silicon film are sequentially deposited on the device substrate 14, and the polycrystalline silicon film and the gate oxide film 24 are patterned to form a gate electrode 26 in an active region of the device substrate 14. The gate electrode 26 is a word line of a DRAM device.

Using the gate electrode 26 as a mask, an impurity of the second conductivity type, for example, arsenic (As) or phosphorus (P) is added to the active region of the device substrate 14 on both sides of the exposed gate electrode 26 at 1 × 10 ¹³ ions /. Ions are implanted in an amount of not more than ² cm ^2, and N − drains and
To form As a result, an N-type MOSFET is formed.

Referring to FIG. 2, spacer oxide films 30 are formed on both side walls of the gate electrode 26. MOSFE
A first interlayer insulating film 32 having a planarized surface is formed on the device substrate 14 on which the T is formed. Subsequently, the first interlayer insulating film 32 is selectively etched to form the drain 27.
Is formed to expose the first contact hole 33. Thereafter, a bit line 34 that contacts the drain 27 through the first contact hole is formed on the first contact hole and the first interlayer insulating layer 32 adjacent to the first contact hole. The bit line 34 is preferably formed in a polycide structure.

Referring to FIG. 3, the bit line 34
A second interlayer insulating film 36 having a planarized surface is formed on the first interlayer insulating film 32 including
Then, the first interlayer insulating film 32 is selectively etched to form a second contact hole 38 exposing the source 28. A contact hole spacer 40 is formed on the inner wall of the second contact hole 38 to insulate a word line and a capacitor to be formed later.

Next, impurities of the first conductivity type, for example, boron (B) are implanted into the source 28 exposed by the second contact hole 38 by ion implantation energy of 20 to 30 keV.
Ions are implanted at a dose of 1 × 10 ¹³ to 1 × 10 ¹⁴ ions / cm ² . Along with this, as shown, a P-type impurity region 42 is formed below and in contact with the source 28, so that a junction capacitor is formed between the source 28 and the impurity region 42.

Referring to FIG. 4, a second contact hole and a capacitor contacting the source 28 through the second contact hole are formed on the second interlayer insulating layer 36 adjacent to the second contact hole. The capacitor includes a storage electrode 44, a dielectric material 46 and a plate electrode 48 as is known.

[0016]

According to the DRAM device of the present invention, since a junction capacitor is further formed, when such a junction capacitor is connected in parallel with an existing capacitor, the capacitance of the unit cell is increased only by the capacitance due to the junction capacitor. can get. Therefore, it is possible to sufficiently secure the capacitance of the capacitor in the unit cell without changing the area and structure of the capacitor.
A RAM device can be manufactured.

Further, since the SOI wafer is used, the electrical characteristics of the device can be improved, and at the same time, it can be very advantageously applied to the manufacture of a highly integrated device.

On the other hand, in the embodiment of the present invention described in detail, N-
Although the case where the P impurity region is formed below the source has been described as an example, the present invention can be applied to a case where the conductivity type of the impurity is changed.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it should be understood that various changes, substitutions, and alterations can be made without departing from the technical spirit of the present invention. It will be apparent to those of ordinary skill in the art to which the invention pertains.

[Brief description of the drawings]

FIG. 1 is a manufacturing process diagram of a DRAM device according to an embodiment of the present invention.

FIG. 2 is a manufacturing process diagram of the DRAM device following FIG. 1;

FIG. 3 is a manufacturing process diagram of the DRAM device following FIG. 2;

FIG. 4 is a manufacturing process diagram of the DRAM device following FIG. 3;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Support substrate 12 Buried oxide film 14 Debaisse substrate 20 SOI wafer 22 Field oxide film 24 Gate oxide film 26 Gate electrode 27 Drain 28 Source 30 Spacer oxide film 32 First interlayer insulating film 33 First contact hole 34 Bit line 36 Second interlayer Insulating film 38 Second contact hole 40 Contact hole spacer 42 Impurity region 44 Storage electrode 46 Dielectric material 48 Plate electrode

Claims (9)

[Claims] An SOI wafer having a buried oxide film interposed between a supporting substrate and a device substrate of a first conductivity type;
A word line formed on the device substrate of the SOI wafer; first and second bonding regions of a second conductivity type formed on the device substrate on both sides of the word line; and a contact with the first bonding region. A bit line, a capacitor in contact with the second junction region, and a second junction formed below the second junction region of the second conductivity type and forming a junction capacitor with the second junction region of the second conductivity type. A DRAM device comprising: one conductivity type impurity region. 2. The DRAM device according to claim 1, wherein said device substrate and said impurity region are of a P-type conductivity type, and said first and second junction regions are of an N- type conductivity type. 3. The DRAM device according to claim 2, wherein said second junction region and said impurity region form a PN junction capacitor. 4. The semiconductor device according to claim 1, wherein said device substrate and said impurity region are N-type.
2. The DRAM device of claim 1, wherein the first and second junction regions have a P-type conductivity. 5. An SOI wafer having a support substrate and a device substrate of a first conductivity type stacked with an oxide film interposed therebetween, and forming a field oxide film on the device substrate of the SOI wafer to form an active region. Limiting the
Forming a word line in an active region of the device substrate; forming first and second junction regions of a second conductivity type in active regions of the device substrate on both sides of the word line; Forming a first interlayer insulating film on the device substrate, and selectively etching the first interlayer insulating film to form a first contact hole exposing the first junction region; Forming a bit line in contact with the first junction region through the first contact hole on the hole and the first interlayer insulating film adjacent to the hole, and forming a bit line on the first interlayer insulating film including the bit line. A second interlayer insulating film is formed, and a second contact hole exposing the second junction region is formed by selectively etching the second and first interlayer insulating films. Performing ion implantation of a first conductivity type impurity into an active region of the device substrate to form an impurity region in contact with the second junction region below the second junction region; and 2 contact hole and the second contact hole on the second interlayer insulating film adjacent thereto.
Forming a capacitor in contact with the second junction region through a contact hole.
A method for manufacturing an AM element. 6. The DRAM device according to claim 5, wherein said device substrate and said impurity region are of P-type conductivity, and said first and second junction regions are of N-type conductivity. 7. The method as claimed in claim 5, wherein the first and second junction regions are formed by implanting boron or phosphorus ions at a dose of 1 × 10 ¹³ ions / cm ² or less. Method. 8. The semiconductor device according to claim 7, wherein said device substrate and said impurity region are N-type.
6. The method of claim 5, wherein the first and second junction regions are of a P-type conductivity type. 9. The method according to claim 1, wherein the impurity region contains boron in an amount of 1 × 10 ¹³ to
6. The method according to claim 5, wherein ions are implanted at a dose of 1 × 10 ¹⁴ ions / cm ² .