^3706 8 濟 部 t 央 標 準 局 員 X. 消 費 合 作 社 印 製^ 3706 8 Member of the Central Bureau of Standards of the Ministry of Economic Affairs X. Printed by the Consumer Cooperative
A7 ---____B7 '五、發明説明（/ ) 發明之背景 、本4 ^係關於製作動態隨機存取記憶體(dram)的方 法特別疋使用絕緣層上有矽基板0〇1)之動態隨機存取記 憶體(dram)之方法。 半導體記憶元件包括記憶體晶胞陣列部分，其#包含-電晶體及電容器轉财式安排並搭喊周邊電路來驅動 記憶體晶胞陣列部分的記憶體晶胞來完成寫人及讀取儲存 曰曰月的資Λ電谷器之結構含一儲存電極、平板電極及介 於儲存=之_介頓，並且要求平板電極之電容值很 大°電容㈣電容值與平板電極之間的距離成反比，且儲 存電，f比於介電常數與電極面積之乘積。因此，為了增 加電容器之電容，可縮短電極之間的距離，增加電極之^ 積，或是使用介電常數大的介電膜。由於平板電極之間的 距離有極限，建議採用增加電極之面積，或是使用介電常· 數大的介電膜之方式。利用增加電極之面積來增加電容的 例子為製作一翼狀、堆疊形狀或是圓柱狀三維的電容器。 然而’三維電容器的缺點為形狀複雜，製程不簡單，且 續程序困難。 發明之鮑論 本發明之目的係提供一半導體記憶元件，包括絕緣層 上有矽基板(SOI)，其中支撐基板與元件基板之間夾入一層 掩埋氧化層’含第一導電性之元件基板；在絕緣層上有石^ 基板(SOI)之元件基板上形成之字元線；元件基板字元線兩 側形成之第一及第二接面區域；與第一接面區域接觸之位 本紙張尺度適用中國國家標华（CNS > A4規格（2丨OX297公釐）A7 ---____ B7 'Fifth, the description of the invention (/) Background of the invention, this 4 ^ is about the method of making dynamic random access memory (dram), especially the use of dynamic random on the insulation layer with a silicon substrate 0〇1) How to access the memory (dram). The semiconductor memory element includes a memory cell array part, which includes a transistor and a capacitor-type wealth transfer arrangement and calls a peripheral circuit to drive the memory cell of the memory cell array part to complete writing and reading storage. The structure of the electric valley device of Yueyue includes a storage electrode, a plate electrode, and a storage medium, and requires that the capacitance of the plate electrode is large. The capacitance ㈣ capacitance value is inversely proportional to the distance between the plate electrodes. And the stored electricity, f ratio is the product of the dielectric constant and the electrode area. Therefore, in order to increase the capacitance of the capacitor, the distance between the electrodes may be shortened, the electrode area may be increased, or a dielectric film having a large dielectric constant may be used. Since the distance between the plate electrodes is limited, it is recommended to increase the electrode area or use a dielectric film with a large dielectric constant. Examples of increasing the capacitance by increasing the electrode area are making a three-dimensional capacitor in the shape of a wing, a stack, or a cylinder. However, the disadvantages of the three-dimensional capacitor are that the shape is complicated, the manufacturing process is not simple, and the procedure is difficult. The invention aims to provide a semiconductor memory device including a silicon substrate (SOI) on an insulating layer, wherein a buried oxide layer is sandwiched between the support substrate and the device substrate, and the device substrate includes a first conductivity; Character lines formed on an element substrate with a stone substrate (SOI) on the insulating layer; first and second junction areas formed on both sides of the element substrate's character lines; a paper sheet in contact with the first junction area Standards apply to China National Standard (CNS > A4 specifications (2 丨 OX297 mm)
43706 8 經濟部中央棣準局員工消費合作社印製 A7 B7 主、發明説明（>) > 元線；與第二接面區域接觸之電容；以及在第二接面區域 上面形成第一導電性之雜質區域以構成與第二接面區域之 接面電容。 根據本發明另一目的，可提供製作動態隨機存取記憶 體方法，其步驟如下：準備一絕緣層上有矽基板(s〇I)， 其中支樓基板與元件基板之間夾入一層掩埋氧化層；在絕 緣層上有矽基板(SOI)之元件基板上形成絕緣膜以定義元件 基板之作用區；在元件基板之作用區形成位元線；在位元 線兩側作用區形成第一接面區域及第二接面區域，其中第 一接面區域及第二接面區域為第二第導電性；在元件基板 上形成包括字元件之第一中間絕緣層；將第一中間絕緣層 蝕刻以形成使第一接面區域裸露之第一接觸孔；在包含第 一接觸孔的第一中間絕緣層上形成位元線，位元線可經由 第一接觸孔與裸露的第一接面區域接觸；在包含第一接觸 孔的第一中間絕緣層上形成第二中間絕緣層.；將第.一及第 一中間絕緣層餘刻以形成使第二接面區域裸露之第二接觸 孔；利用植入第一導電性雜質於元件基板之作用區在第二 接面區域形成雜質區域；並在包含第二接觸孔的第二中間 絕緣層上形成電容，此電容器可經由第二接简孔與裸露的 第二接面區域接觸。 本發明之另一目的、優點及新穎特色可於下面中詳述， 然而其描述並非用以限定本發明。任何熟習此技術者，皆 可參考此描述而更清楚了解此描述實施例之不同的改良及 結合及其它發明之實施例。因此，亦欲以所附的申請專利 4 本紙張尺度適用中國國家標準（CNS > A4規格（210X：297公釐） (請先閲讀背面之注意事項再填寫本頁) 一裝. 訂 A7 43706 8 B7 五、發明説明（岑） , 範圍來包含本發明任何的改良或實施例。 圖式之簡述 (請先閱讀背面之注意事項再填寫本頁〕 第1A圖至第1D圖為根據本發明動態隨機存取記憶體製 程之截面圖。 圖示之參考數字 20 :絕緣層上有矽基板(SOI) 10 :支撐基板 14 :元件基板 12 :掩埋氧化層 22 :絕緣膜 24:閘極氧化層 26 :閘極電極、字元線 28 :源極 經濟部中央標準局員工消費合作社印製 27 :汲極 30 :隔離氧化層 32 :第一中間絕緣層 33:第一接觸孔 34:位元線 36:第二中間絕緣層 40:接觸孔間距 38:第二接觸孔 42 : P型雜質區域 44 :儲存電極 46 :介電膜 5 本紙張尺度適用中國國家標準（CNS ) A4規格（2丨OX29?公釐） 8 .經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（ 48 :平板電極 發明之詳細描述 參考第1A圖，準備一絕緣層上有矽基板(s〇I)2()，其中 支#基板10與元件基板14之間夾入一層掩埋氧化層12 ; 元件基板為第一導電性，例如P型導電性。在元件基板14 上形成絕緣膜22以疋義元件基板14之^作用區。氧化膜及 多晶層可在兀件基板14上形成並接著上圖案形成閘極氧化 層24及動態隨機存取記憶體(DRAM)字元線之閘極電極 26。第一導電性的雜質，例如;e申(as)或鱗(p)可植入使用閘 極電極26為植入罩之元件基板14的裸露作用區域來形成 元件基板作用區域内閘極電極26兩側源極28及波極27之 第一接面區域及第一接面區域^及極及源極雜質之濃度為 IX 1〇13離子/平方公分以下且源極及汲極區域為低濃度的N-型雜質。因此可在元件基板14上形成MOS電晶體。 參考第1B圖，在閘極電極26兩侧壁形成隔離氧化層30 且第一中間絕緣層32可在含MOS電晶體的元件基板14上 形成’並接著以傳統光顯影技術形成第一接觸孔33，使得 汲極區域27裸露。位元線34可在包含第一接觸孔33的第 一中間絕緣層32上形成使其可經由第一接觸孔33與裸露 區域接觸。位元線34最好使用多晶矽化金屬（p〇iicide)。 參考第〗C圖，第二中間絕緣層36可在包含位元線34 的第間絕緣層32上形成，並接著以傳統光顯影技術將 第一中間絕緣層32及第二中間絕緣層36蝕刻形成第二接 觸孔38 ’使得源極區域28裸露。接著，接觸孔間距40可 泰紙張尺度適用中國國家操準（CNS ) A视格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁343706 8 Printed A7 B7 main and invention descriptions by the Consumer Cooperatives of the Central Government Bureau of the Ministry of Economic Affairs; > meta wires; capacitors in contact with the second interface area; and first conductive formation on the second interface area The impurity region is formed as a junction capacitance with the second junction region. According to another object of the present invention, a method for manufacturing a dynamic random access memory can be provided. The steps are as follows: preparing an insulating layer with a silicon substrate (s0I), wherein a buried oxide is sandwiched between the supporting substrate and the element substrate. Layer; forming an insulating film on an element substrate having a silicon substrate (SOI) on the insulating layer to define the active area of the element substrate; forming bit lines in the active area of the element substrate; forming first contacts on the active areas on both sides of the bit line Surface area and second interface area, wherein the first interface area and the second interface area are second and second conductive; a first intermediate insulating layer including a word element is formed on the element substrate; and the first intermediate insulating layer is etched A first contact hole is formed to expose the first contact area; a bit line is formed on the first intermediate insulating layer including the first contact hole, and the bit line can contact the exposed first contact area through the first contact hole. Contacting; forming a second intermediate insulating layer on the first intermediate insulating layer including the first contact hole; leaving the first and first intermediate insulating layers to leave a second contact hole exposing the second interface area; Use of implants A conductive impurity forms an impurity region in a second contact area of an active region of the element substrate; and a capacitor is formed on a second intermediate insulating layer including a second contact hole, and the capacitor can pass through the second contact hole and the exposed first contact hole. Contact between two junction areas. Another object, advantages and novel features of the present invention can be detailed below, but the description is not intended to limit the present invention. Anyone skilled in the art can refer to this description to better understand the different improvements and combinations of the embodiments described and other embodiments of the invention. Therefore, I also intend to apply the Chinese paper standard (CNS > A4 size (210X: 297 mm)) with the attached application patent 4 paper sizes (Please read the precautions on the back before filling this page). Pack A7 43706 8 B7 V. Description of the invention (cen), the scope includes any improvements or embodiments of the invention. Brief description of the drawings (please read the precautions on the back before filling out this page) Figures 1A to 1D are based on this A cross-sectional view of the invention of the dynamic random access memory system. Reference numeral 20 shown in the figure: a silicon substrate (SOI) on an insulating layer 10: a supporting substrate 14: a component substrate 12: a buried oxide layer 22: an insulating film 24: a gate oxide Layer 26: Gate electrode, character line 28: Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Source Economy 27: Drain 30: Isolation oxide layer 32: First intermediate insulating layer 33: First contact hole 34: Bit Line 36: Second intermediate insulating layer 40: Contact hole pitch 38: Second contact hole 42: P-type impurity region 44: Storage electrode 46: Dielectric film 5 This paper is applicable to the Chinese National Standard (CNS) A4 specification (2 丨OX29? Mm) 8. Consumers of the Central Bureau of Standards of the Ministry of Economic Affairs Cooperative printed A7 B7 V. Description of the invention (48: Detailed description of the invention of the flat electrode Refer to Figure 1A, prepare an insulating layer with a silicon substrate (s〇I) 2 (), in which the substrate # 10 and the component substrate 14 A buried oxide layer 12 is sandwiched between the elements; the element substrate is of first conductivity, such as P-type conductivity. An insulating film 22 is formed on the element substrate 14 to define the active region of the element substrate 14. The oxide film and the polycrystalline layer may be A gate oxide layer 24 and a gate electrode 26 of a dynamic random access memory (DRAM) word line are formed on the element substrate 14 and then patterned. A first conductive impurity, for example; Or the scale (p) can be implanted using the gate electrode 26 as the exposed area of the element substrate 14 of the implant cover to form the first interface between the source electrode 28 and the wave electrode 27 on both sides of the gate electrode 26 in the region of the element substrate. N-type impurities in the region and the first junction region ^ and the electrode and source impurities are IX 1013 ions / cm 2 or less, and the source and drain regions have low concentrations. Therefore, they can be formed on the element substrate 14 MOS transistor. Referring to FIG. 1B, an isolation oxide layer 3 is formed on both side walls of the gate electrode 26. 0, and the first intermediate insulating layer 32 may be formed on the element substrate 14 containing the MOS transistor, and then the first contact hole 33 is formed by a conventional photo development technology, so that the drain region 27 is exposed. The bit line 34 may be A contact hole 33 is formed on the first intermediate insulating layer 32 so that it can be in contact with the exposed area through the first contact hole 33. The bit line 34 is preferably made of polysilicon. Refer to FIG. The two intermediate insulating layers 36 may be formed on the first insulating layer 32 including the bit lines 34, and then the first intermediate insulating layer 32 and the second intermediate insulating layer 36 are etched to form a second contact hole 38 ′ using a conventional photo development technique. The source region 28 is exposed. Next, the contact hole spacing is 40 kt. The paper size is applicable to China National Standards (CNS) A viewing grid (210X297 mm) (Please read the precautions on the back before filling in this page 3
ώ3^〇6Β 五 經濟部中央梯準局貝工消費合作社印掣 、發明説明（f) 在第一接觸孔38的辟卜报&他a ·_ ώ 成的電容。拯# &土形成使子70線26與後續的程序形 ⑽電各接耆’濃度1χι〇13至W 第-導電性雜質.，例如 離子千方^刀的 件基板之作用區域。因此，植入凡 以下报忐η少、、e ”為區域42可在源極28 容。此時，雜質:=28及雜質區域42構成Μ接面電 化層保持-S域2可形成與源極區域接觸姆 搞4: 圖’包含儲存電極44、介電膜46及平板電 =2利用傳統電容器形成之方法在包含第二接 接㈣3請―中間絕緣層％上形成。電容器可經由第二 接觸孔38與裸露區域28接觸。 、根據本發明，P型雜質區域可另外在N-型源極區域下形 成以構成ρη接面電谷以及源極區域。如果接面電容可平 行連接至含财電極、介f膜及平板電極之械隨機存取 §己憶體兀件的傳統電容器，可藉由增加動態隨機存取記憶 體晶胞接面電容器之電容來增加其電容。因此，不須改變 電容器結構之面積，就可以有效地確定單位晶胞之電容， 藉此製造大電容之動態隨機存取記憶體元件。此外，由於 動態隨機存取記憶體元件所使用的基板為絕緣層上有矽基 板(SOI)，可改良動態隨機存取記憶體元件的電性，進而製 造高積體化之動態隨機存取記憶體元件β在較佳實施例中， 即使構成接面電容的雜質區域及源極區域分別含ρ型及Ν 型導電，也可改變成Ν型及Ρ型導電》 先前描述僅顯示此發明之較佳實施例。任何熟習此技術 本紙琴尺度適用中國國家梯準（CNS ) Α4规格（210X297公釐） (請先閲請背面之注項再填寫本頁) -訂_ 5. Λ3"^°6 8 Α7 Β7 五、發明説明（从） 丨 者，皆可參考此描述而更清楚了解此描述實施例之不同的 改良及結合.及其它發明之實施例。因此，上述實施例為作 描述，而非限制此發明。 (請先閲讀背面之注意事項再填窝本頁} 經濟部中央標準局員工消費合作社印製 8 本紙張尺度適用中國國家標準（CNS ) Α4规格（210Χ297公釐）FREE 3 ^ 〇6Β 5 Printed by the Central Laboratories of the Ministry of Economic Affairs, Shellfish Consumer Cooperatives, Invention Description (f) Bibliography in the first contact hole 38 & he a capacitor. The life-saving soil formation line 70 and the subsequent program are electrically connected to each other ’and have a concentration of 1 × 13 to Wth-conducting impurities, such as an active area of a substrate of an ion source. Therefore, the implanted regions where the following reports are small, and e "are the regions 42 that can be contained in the source 28. At this time, the impurity: = 28 and the impurity regions 42 constitute the M-junction electrochemical layer retention-S domain 2 can be formed with the source The contact area of the polar region is shown in Figure 4: Figure 'Contains storage electrode 44, dielectric film 46, and flat panel = 2 using conventional capacitor formation method on the second connection interface 3-the middle insulation layer%. The capacitor can be The contact hole 38 is in contact with the exposed region 28. According to the present invention, a P-type impurity region may be additionally formed under the N-type source region to constitute a pn junction valley and a source region. If the junction capacitor can be connected in parallel to the The traditional capacitors of mechanical random access devices such as financial electrodes, dielectric films, and flat electrodes can be increased by increasing the capacitance of the dynamic random access memory cell-to-surface capacitors. Therefore, there is no need to By changing the area of the capacitor structure, the capacitance of the unit cell can be effectively determined, thereby manufacturing a large-capacity dynamic random access memory element. In addition, since the substrate used for the dynamic random access memory element is an insulating layer, Silicon Substrate (SOI), which can improve the electrical properties of the dynamic random access memory element, and then manufacture a highly integrated dynamic random access memory element β In a preferred embodiment, even the impurity regions and sources constituting the junction capacitance The polar region contains ρ-type and N-type conductivity, respectively, and can be changed to N-type and P-type conductivity. The previous description only shows the preferred embodiment of this invention. Anyone familiar with this technology can use the Chinese National Standard (CNS) A4 Specifications (210X297 mm) (please read the note on the back before filling this page) -Order_ 5. Λ3 " ^ ° 6 8 Α7 Β7 V. Description of the invention (from) 丨 For those who can refer to this description and more A clear understanding of the different improvements and combinations of the described embodiments and embodiments of other inventions. Therefore, the above embodiments are described instead of limiting the invention. (Please read the notes on the back before filling in this page} Economy Printed by the Consumer Standards Cooperative of the Ministry of Standards of the Ministry of Foreign Affairs of the People's Republic of China 8 paper sizes are applicable to China National Standard (CNS) Α4 specifications (210 × 297 mm)