KR19990057854A - Semiconductor memory device with increased cell capacitance and manufacturing method thereof - Google Patents
Semiconductor memory device with increased cell capacitance and manufacturing method thereof Download PDFInfo
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- KR19990057854A KR19990057854A KR1019970077933A KR19970077933A KR19990057854A KR 19990057854 A KR19990057854 A KR 19990057854A KR 1019970077933 A KR1019970077933 A KR 1019970077933A KR 19970077933 A KR19970077933 A KR 19970077933A KR 19990057854 A KR19990057854 A KR 19990057854A
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- H—ELECTRICITY
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H—ELECTRICITY
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- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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Abstract
본 발명은 반도체 제조 분야에 관한 것으로, 특히 반도체 메모리 장치 제조 공정에 관한 것이며, 캐패시터의 면적 및 구조의 변화 없이 단위 셀의 캐패시턴스를 증가시킨 반도체 메모리 장치 및 그 제조방법을 제공하는데 그 목적이 있다. 본 발명은 하나의 칩 상에서 셀 어레이 내의 트랜지스터의 드레인 영역 하부에 드레인 영역에 도핑된 불순물과 다른 도전형 불순물을 도핑하여 PN 접합(junction)을 형성하여 접합 캐패시터를 더 형성함으로써 반도체 메모리 소자의 단위 면적당 셀 캐패시턴스를 증가시키는 기술이다. 상술한 본 발명의 기술적 원리로부터 제공되는 특징적인 반도체 메모리 장치는 반도체 기판 상에 제공된 워드라인; 상기 반도체 기판에 제공된 제1 도전형 소오스/드레인; 상기 제1 도전형 소오스에 콘택되는 비트라인; 상기 제1 도전형 드레인에 콘택되는 캐패시터; 및 상기 제1 도전형 드레인 하부에 제공되어 상기 제1 도전형 드레인과 접합 캐패시터를 이루는 제2 도전형 불순물 영역을 포함하여 이루어진다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor memory device manufacturing process, and an object thereof is to provide a semiconductor memory device and a method of manufacturing the same in which the capacitance of a unit cell is increased without changing the area and structure of the capacitor. According to an embodiment of the present invention, a PN junction is formed by doping an impurity doped in a drain region and another conductive dopant under a drain region of a transistor in a cell array on a single chip to further form a junction capacitor. It is a technique of increasing cell capacitance. Characteristic semiconductor memory devices provided from the above-described technical principles of the present invention include word lines provided on a semiconductor substrate; A first conductivity type source / drain provided in the semiconductor substrate; A bit line in contact with the first conductivity type source; A capacitor in contact with the first conductivity type drain; And a second conductivity type impurity region provided under the first conductivity type drain to form a junction capacitor with the first conductivity type drain.
Description
본 발명은 반도체 제조 분야에 관한 것으로, 특히 반도체 메모리 장치 제조 공정에 관한 것이다.TECHNICAL FIELD The present invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor memory device manufacturing process.
반도체 메모리 장치는 단위 셀이 매트릭스 모양으로 배열되고, 각 셀들의 워드라인이 서로 연결되어 있는 셀 어레이(cell array)부와 셀 어레이를 구동하여 각 셀에 데이터(data)를 저장하거나 전송하는 역할을 하는 주변회로부로 이루어져 있다.The semiconductor memory device drives a cell array unit and a cell array in which unit cells are arranged in a matrix and word lines of the cells are connected to each other, thereby storing or transmitting data in each cell. It consists of a peripheral circuit part.
DRAM(Dynamic Random Access Memory)의 단위 셀은 셀을 구동하기 위한 하나의 트랜지스터와 전하를 저장하는 하나의 캐패시터로 구성된다. 이때, 셀 캐패시터의 캐패시턴스(정전용량)가 클수록 유리하다. 셀 캐패시터의 캐패시턴스는 캐패시터의 양 전극간의 거리에 반비례하고, 전극의 면적과 유전물질의 유전상수의 곱에 비례한다. 따라서, 양 전극간의 거리를 좁히거나, 전극의 면적을 넓히거나 또는 유전상수가 큰 물질을 사용함으로써 셀 캐패시터의 캐패시턴스를 증가시킬 수 있다. 그러나, 전극간의 거리를 줄이는 데에는 한계가 있으므로 대개 유전상수가 높은 절연물질을 찾거나 전극의 면적을 넓히는 방향으로 많은 시도가 이루어지고 있다.The unit cell of a DRAM (Dynamic Random Access Memory) is composed of one transistor for driving a cell and one capacitor for storing charge. At this time, the larger the capacitance (capacitance) of the cell capacitor is, the more advantageous it is. The capacitance of the cell capacitor is inversely proportional to the distance between both electrodes of the capacitor, and is proportional to the product of the area of the electrode and the dielectric constant of the dielectric material. Therefore, the capacitance of the cell capacitor can be increased by narrowing the distance between the two electrodes, increasing the area of the electrode, or using a material having a high dielectric constant. However, since there is a limit to reducing the distance between the electrodes, many attempts have been made to find an insulating material having a high dielectric constant or to increase the area of the electrode.
특히, 전극의 면적을 넓히기 위해서 핀(Fin) 구조, 단순 스택(Stack) 구조, 원통(cylinder)형 구조 등 전극의 형태를 변형시켜 셀에서 차지하는 면적을 증가시키는 등 수 많은 3 차원적 구조가 시도되고 있다. 그러나, 이러한 3 차원 구조의 캐패시터는 캐패시터의 모양이 복잡하므로 제조 공정 또한 까다롭고 주변 지역과의 단차를 유발하여 후속 공정을 어렵게 하는 한계를 지니고 있다.In particular, in order to increase the area of the electrode, a number of three-dimensional structures have been attempted such as increasing the area occupied by the cell by modifying the shape of the electrode such as a fin structure, a simple stack structure, and a cylindrical structure. It is becoming. However, since the three-dimensional capacitor has a complicated shape of the capacitor, the manufacturing process is also difficult, and there is a limitation in that a subsequent process is difficult by causing a step with the surrounding area.
본 발명은 캐패시터의 면적 및 구조의 변화 없이 단위 셀의 캐패시턴스를 증가시킨 반도체 메모리 장치 및 그 제조방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device and a method of manufacturing the same in which the capacitance of the unit cell is increased without changing the area and structure of the capacitor.
도 1a 내지 도 1d는 본 발명의 일실시예에 따른 DRAM 제조 공정도.1A-1D are diagrams of a DRAM manufacturing process in accordance with one embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
10 : 하부 실리콘 기판 11 : 매몰 산화막10 lower silicon substrate 11: buried oxide film
12 : 상부 실리콘층 13 : 필드 산화막12: upper silicon layer 13: field oxide film
14 : 게이트 산화막 15 : 게이트 전극14 gate oxide film 15 gate electrode
16 : 포토레지스트 패턴 17 : 소오스16 photoresist pattern 17 source
18 : 드레인 19 : 스페이서 산화막18 drain 19 spacer oxide film
20, 22 : 층간절연막 21 : 비트라인20, 22: interlayer insulating film 21: bit line
23 : 콘택홀 스페이서 24 : P0불순물 영역23 contact hole spacer 24 P 0 impurity region
25 : 스토리지 노드 26 : 유전체 박막25: storage node 26: dielectric thin film
27 : 플레이트 전극27: plate electrode
본 발명은 하나의 칩 상에서 셀 어레이 내의 트랜지스터의 드레인 영역 하부에 드레인 영역에 도핑된 불순물과 다른 도전형 불순물을 도핑하여 PN 접합(junction)을 형성하여 접합 캐패시터를 더 형성함으로써 반도체 메모리 소자의 단위 면적당 셀 캐패시턴스를 증가시키는 기술이다.According to an embodiment of the present invention, a PN junction is formed by doping an impurity doped in a drain region and another conductive dopant under a drain region of a transistor in a cell array on a single chip to further form a junction capacitor. It is a technique of increasing cell capacitance.
상술한 본 발명의 기술적 원리로부터 제공되는 특징적인 반도체 메모리 장치는 반도체 기판 상에 제공된 워드라인; 상기 반도체 기판에 제공된 제1 도전형 소오스/드레인; 상기 제1 도전형 소오스에 콘택되는 비트라인; 상기 제1 도전형 드레인에 콘택되는 캐패시터; 및 상기 제1 도전형 드레인 하부에 제공되어 상기 제1 도전형 드레인과 접합 캐패시터를 이루는 제2 도전형 불순물 영역을 포함하여 이루어진다.Characteristic semiconductor memory devices provided from the above-described technical principles of the present invention include word lines provided on a semiconductor substrate; A first conductivity type source / drain provided in the semiconductor substrate; A bit line in contact with the first conductivity type source; A capacitor in contact with the first conductivity type drain; And a second conductivity type impurity region provided under the first conductivity type drain to form a junction capacitor with the first conductivity type drain.
또한, 상술한 본 발명의 기술적 원리로부터 제공되는 특징적인 반도체 메모리 장치 제조방법은 반도체 기판에 워드라인 및 제1 도전형 소오스/드레인을 형성하는 단계; 상기 제1 도전형 소오스에 콘택되는 비트라인을 형성하는 단계; 전체구조 상부에 층간절연막을 형성하는 단계; 상기 층간절연막을 선택 식각하여 상기 제1 도전형 드레인을 노출시키는 콘택홀을 형성하는 단계; 상기 제1 도전형 드레인 하부에 제2 도전형 불순물 영역을 형성하는 단계; 및 상기 제1 도전형 드레인에 콘택되는 캐패시터를 형성하는 단계를 포함하여 이루어진다.In addition, the characteristic semiconductor memory device manufacturing method provided from the above-described technical principles of the present invention comprises the steps of: forming a word line and a first conductivity type source / drain on a semiconductor substrate; Forming a bit line in contact with the first conductivity type source; Forming an interlayer insulating film on the entire structure; Selectively etching the interlayer insulating layer to form a contact hole exposing the first conductive drain; Forming a second conductivity type impurity region under the first conductivity type drain; And forming a capacitor in contact with the first conductivity type drain.
이하, 본 발명의 실시예를 소개한다.Hereinafter, embodiments of the present invention will be introduced.
첨부된 도면 도 1a 내지 도 1d는 본 발명의 일실시예에 따른 DRAM 제조 공정을 도시한 것으로, 이하 이를 참조하여 그 공정을 설명한다.1A to 1D illustrate a DRAM manufacturing process according to an exemplary embodiment of the present invention, which will be described below with reference to the drawing.
우선, 도 1a에 도시된 바와 같이 하부 실리콘 기판(10), 매몰 산화막(11) 및 상부 실리콘층(12)으로 이루어진 실리콘-온-인슐레이터(Silicon-On-Insulator, 이하 SOI라 함) 기판 상에, 즉 상부 실리콘층(12)에 필드 산화막(13)을 형성하여 활성 영역을 정의하고, 활성 영역에 게이트 산화막(14)을 성장시킨 다음, 전체구조 상부에 폴리실리콘막을 증착하고, 그 상부에 게이트 전극 형성을 위한 포토레지스트 패턴(16)을 형성한다. 계속하여, 포토레지스트 패턴(16)을 식각 마스크로 사용하여 폴리실리콘막을 선택 식각하여 게이트 전극(15)을 형성하고, 1×1013ions/㎠ 이하의 도즈량으로 비소(As) 이온주입을 실시하여 N-소오스/드레인(17, 18)을 형성한다.First, as shown in FIG. 1A, a silicon-on-insulator (hereinafter referred to as SOI) substrate including a lower silicon substrate 10, an buried oxide film 11, and an upper silicon layer 12. That is, the field oxide film 13 is formed on the upper silicon layer 12 to define an active region, the gate oxide film 14 is grown on the active region, a polysilicon film is deposited on the entire structure, and the gate is formed thereon. A photoresist pattern 16 for forming an electrode is formed. Subsequently, the polysilicon film is selectively etched using the photoresist pattern 16 as an etching mask to form the gate electrode 15, and arsenic (As) ion implantation is performed at a dose of 1 × 10 13 ions / cm 2 or less. To form N - source / drain 17, 18.
다음으로, 도 1b에 도시된 바와 같이 게이트 전극(15) 측벽에 스페이서 산화막(19)을 형성하고, 전체구조 상부에 평탄화된 층간절연막(20)을 형성한 다음, 이를 선택 식각하여 소오스(17)를 노출시키는 비트라인(bit line) 콘택홀을 형성한다. 계속하여, 폴리사이드 구조의 비트라인(21)을 형성한다.Next, as shown in FIG. 1B, a spacer oxide layer 19 is formed on the sidewalls of the gate electrode 15, a planarized interlayer dielectric layer 20 is formed on the entire structure, and then selectively etched to form a source 17. A bit line contact hole is formed to expose the bit line. Subsequently, the bit line 21 of the polyside structure is formed.
이어서, 도 1c에 도시된 바와 같이 전체구조 상부에 평탄화된 층간절연막(22)을 형성하고, 이를 선택 식각하여 스토리지 노드(storage node) 콘택홀을 형성한 다음, 게이트 전극(15)과의 단락을 방지하기 위하여 콘택홀 측벽에 콘택홀 스페이서(23)를 형성하고, 20∼30keV의 이온주입 에너지와 1×1013∼1×1014ions/㎠의 도즈량을 사용하여 붕소(B) 이온주입을 실시하여 드레인(18) 하부에 P0불순물 영역(24)을 형성한다.Subsequently, as shown in FIG. 1C, the planarized interlayer insulating layer 22 is formed on the entire structure, and selectively etched to form a storage node contact hole, and then a short circuit with the gate electrode 15 is removed. In order to prevent this, contact hole spacers 23 are formed on the sidewalls of the contact holes, and boron (B) ion implantation is performed using ion implantation energy of 20 to 30 keV and dose amount of 1x10 13 to 1x10 14 ions / cm 2. performed to form a bottom drain (18) P 0 impurity region 24.
끝으로, 도 1d에 도시된 바와 같이 통상적인 방식으로 스토리지 노드(25), 유전체 박막(26) 및 플레이트 전극(27)을 구비하는 캐패시터를 형성한다.Finally, as shown in FIG. 1D, a capacitor having a storage node 25, a dielectric thin film 26 and a plate electrode 27 is formed in a conventional manner.
이러한 공정을 통해 제조된 DRAM은 기존의 셀 캐패시터와 그에 병렬로 연결된 접합 캐패시터에 의해 셀 캐패시턴스를 향상시킬 수 있다.DRAM manufactured through such a process can improve cell capacitance by using a conventional cell capacitor and a junction capacitor connected in parallel thereto.
상술한 일실시예에서는 N-드레인 하부에 P0불순물 영역을 형성하는 경우를 예로 들어 설명하였으나, 본 발명은 불순물의 도전형을 바꾸는 경우에도 적용할 수 있다.In the above-described embodiment, the case where the P 0 impurity region is formed below the N - drain has been described as an example, but the present invention can be applied to the case of changing the conductivity type of the impurity.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
이상에서와 같이 본 발명을 실시하면 기존의 캐패시터에 병렬로 연결된 접합 캐패시터만큼의 셀 캐패시턴스 증가 효과를 얻을 수 있으므로 캐패시터의 면적 및 구조의 변경 없이도 단위 셀 캐패시턴스를 충분히 확보할 수 있는 장점이 있다.As described above, according to the present invention, since the cell capacitance increases as much as the junction capacitors connected in parallel with the existing capacitors, the unit cell capacitance can be sufficiently secured without changing the area and structure of the capacitors.
Claims (9)
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970077933A KR19990057854A (en) | 1997-12-30 | 1997-12-30 | Semiconductor memory device with increased cell capacitance and manufacturing method thereof |
| TW087121252A TW437068B (en) | 1997-12-30 | 1998-12-19 | Dynamic random access memory device and method of manufacturing the same |
| JP10364673A JPH11261032A (en) | 1997-12-30 | 1998-12-22 | Dram element and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970077933A KR19990057854A (en) | 1997-12-30 | 1997-12-30 | Semiconductor memory device with increased cell capacitance and manufacturing method thereof |
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| Publication Number | Publication Date |
|---|---|
| KR19990057854A true KR19990057854A (en) | 1999-07-15 |
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| Application Number | Title | Priority Date | Filing Date |
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| KR1019970077933A KR19990057854A (en) | 1997-12-30 | 1997-12-30 | Semiconductor memory device with increased cell capacitance and manufacturing method thereof |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JPH11261032A (en) |
| KR (1) | KR19990057854A (en) |
| TW (1) | TW437068B (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100450671B1 (en) * | 2002-02-26 | 2004-10-01 | 삼성전자주식회사 | Method for fabricating semiconductor device having storage node contact plugs |
| KR100949874B1 (en) | 2003-07-22 | 2010-03-25 | 주식회사 하이닉스반도체 | A method for forming a storage node of a semiconductor device |
-
1997
- 1997-12-30 KR KR1019970077933A patent/KR19990057854A/en not_active Application Discontinuation
-
1998
- 1998-12-19 TW TW087121252A patent/TW437068B/en not_active IP Right Cessation
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| TW437068B (en) | 2001-05-28 |
| JPH11261032A (en) | 1999-09-24 |
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