JPH11251353A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JPH11251353A JPH11251353A JP5053098A JP5053098A JPH11251353A JP H11251353 A JPH11251353 A JP H11251353A JP 5053098 A JP5053098 A JP 5053098A JP 5053098 A JP5053098 A JP 5053098A JP H11251353 A JPH11251353 A JP H11251353A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- hole
- circuit board
- polyimide
- solder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、スルーホールにテ
ーパーを設けた半導体装置およびその製造方法に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a tapered through hole and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】従来、半導体素子を回路基板に電気的に
接合することにより構成される半導体装置のパッケージ
としては、ＱＦＰ（ Quad Flat Package ）、ＴＣＰ（
TapeCarrier Package ）、ＢＧＡ（ Ball Grid Array
）、ＣＳＰ（ Chip Scale orSize Package ）、ＣＣＢ
（ Controlled Collapsed Bonding）などが既に知られ
ている。この中でも、最近、多ピン化、小型化が進ん
で、注目されているものはＢＧＡ、ＣＳＰ、ＣＣＢであ
る。2. Description of the Related Art Conventionally, a semiconductor device package formed by electrically bonding a semiconductor element to a circuit board includes a QFP (Quad Flat Package) and a TCP (TCP).
Tape Carrier Package), BGA (Ball Grid Array)
), CSP (Chip Scale or Size Package), CCB
(Controlled Collapsed Bonding) is already known. Among them, recently, with increasing number of pins and miniaturization, BGA, CSP and CCB have attracted attention.
【０００３】ＢＧＡによる方法は、米国特許第５，２３
９，１９８号、米国特許第５，２８５，３５２号、米国
特許第５，３８１，３０７号、米国特許第５，３９７，
９２１号などに記載されている。このＢＧＡに関する標
準化はＪＥＤＥＣ、ＥＩＡＪで行われている。これらの
代表例を、図３および図４を参照して、具体的に説明す
る。なお、図３の（ａ）はＢＧＡの断面図であり、同じ
く、（ｂ）はＢＧＡを回路基板に接合した状態の断面図
であり、図４は図３の（ｂ）に用いた回路基板を示して
いる。[0003] The BGA method is disclosed in US Pat.
9,198, U.S. Patent No. 5,285,352, U.S. Patent No. 5,381,307, U.S. Patent No. 5,397,
No. 921 and the like. The standardization of the BGA is performed by JEDEC and EIAJ. These representative examples will be specifically described with reference to FIGS. 3A is a cross-sectional view of the BGA, FIG. 3B is a cross-sectional view of a state in which the BGA is joined to a circuit board, and FIG. 4 is a circuit board used in FIG. Is shown.
【０００４】先ず、図３の（ａ）に示すように、回路基
板１０１上にＩＣチップ１０２をダイボンディング、ワ
イヤボンディングし、これを樹脂などで覆うように封止
するが、ＩＣチップ１０２の搭載面とは反対側の、回路
基板１０１の面にある電極部１０３には、金属ボール、
具体的には、半田ボール１０４を接合し、符号１０５で
示すような半導体素子（ＢＧＡ）を組み立てる。この場
合の回路基板１０１の電極部１０３のピッチは１．２７
ｍｍである。First, as shown in FIG. 3A, an IC chip 102 is die-bonded and wire-bonded on a circuit board 101 and sealed so as to be covered with a resin or the like. On the electrode portion 103 on the surface of the circuit board 101 opposite to the surface, a metal ball,
Specifically, the solder balls 104 are joined to assemble a semiconductor device (BGA) as indicated by reference numeral 105. In this case, the pitch of the electrode portions 103 of the circuit board 101 is 1.27.
mm.
【０００５】次に、半導体装置（ＢＧＡ）１０５の電極
部１０３と対応して、電極部１０６が位置する回路基板
１０７を用意する。なお、図４には、電極部１０６側か
ら拡大して見た回路基板１０７を示す。この電極部１０
６のピッチも１．２７ｍｍである。この事例の回路基板
１０７では、１０×１０個の電極部１０６を有し、外周
２列は、表面に配線パターンがあるが、その他の電極部
は、スルーホール（図示せず）を通して、内層あるいは
裏層の表面に対して導通するように臨んでおり、電極部
１０６以外は半田レジストで絶縁されている。[0005] Next, a circuit board 107 on which the electrode section 106 is located corresponding to the electrode section 103 of the semiconductor device (BGA) 105 is prepared. FIG. 4 shows the circuit board 107 in an enlarged view from the electrode section 106 side. This electrode part 10
The pitch of No. 6 is also 1.27 mm. The circuit board 107 of this case has 10 × 10 electrode portions 106, and the outer two rows have wiring patterns on the surface, but the other electrode portions are formed through inner layers or through through holes (not shown). It faces the surface of the back layer so as to be conductive, and portions other than the electrode portion 106 are insulated by a solder resist.
【０００６】次に、回路基板１０７の電極部１０６上
に、所望のクリーム半田を塗布し、回路基板１０７の電
極１０６と半導体装置１０５の電極１０３とを相対向す
るように位置決めして、融着手段で、半田付けを行う。
図３の（ｂ）は、半田付け後の断面を示す。Next, desired cream solder is applied on the electrode portion 106 of the circuit board 107, and the electrode 106 of the circuit board 107 and the electrode 103 of the semiconductor device 105 are positioned so as to face each other, and are fused. By means of soldering.
FIG. 3B shows a cross section after soldering.
【０００７】ＣＳＰによる方法は、米国特許第５，３４
６，８６１号、米国特許第５，５９２，０２５号などに
記載されている。また、月刊誌［ Semiconductor World
］1995. 5. PP103-131 の特集「本流となるのはＣＳ
Ｐかベアチップか」に、各社のＣＳＰが紹介されてい
る。[0007] The CSP method is disclosed in US Pat.
No. 6,861, and U.S. Pat. No. 5,592,025. In addition, monthly magazine [Semiconductor World
] 1995. 5. Special feature on PP103-131 "CS is the mainstream
CSP of each company is introduced in "P or bare chip?"
【０００８】次に、ＣＳＰによる方法を、図５の（ａ）
および（ｂ）を参照して説明する。図５の（ａ）はＣＳ
Ｐの断面図であり、（ｂ）はＣＳＰを回路基板に接合し
た断面図である。ここで、フレキシブル回路基板１１３
を構成するのに、銅箔１１１（部分的に表面に金メッキ
が施こされている）の裏面にポリイミド層１１２をラミ
ネートし、これに開口を形成するが、また、ポリイミド
層１１２とは反対側の、銅箔１１１の表面に絶縁処理１
１４を施している。フレキシブル回路基板１１３上で
は、その絶縁処理１１４側にＩＣチップ１１５をダイボ
ンディング、ワイヤボンディングし、これを樹脂などで
覆うように封止する。Next, the method using the CSP will be described with reference to FIG.
This will be described with reference to FIGS. FIG. 5A shows CS.
It is sectional drawing of P, (b) is sectional drawing which joined CSP to the circuit board. Here, the flexible circuit board 113
Is formed by laminating a polyimide layer 112 on the back surface of the copper foil 111 (partially gold plated on the surface) and forming an opening in the polyimide layer 112. Insulation treatment 1 on the surface of copper foil 111
14 is given. On the flexible circuit board 113, the IC chip 115 is die-bonded and wire-bonded on the insulating treatment 114 side, and the IC chip 115 is sealed so as to be covered with a resin or the like.
【０００９】その後、レジストにて形成された、ポリイ
ミド層１１２の開口に臨んでいる銅箔１１１の電極部１
１６にクリーム半田を印刷し、ここに半田ボール１１７
を搭載した後、リフローして、クリーム半田、半田ボー
ルを溶融させることで、半田ボール１１７を銅箔１１１
に接合させ、これによって、図５の（ａ）に示すような
半導体装置（ＣＳＰ）１１８を形成する。なお、この電
極部１１６のピッチは０．８ｍｍであって、２５ｐｉｎ
のＣＳＰを構成している。Thereafter, the electrode portion 1 of the copper foil 111 facing the opening of the polyimide layer 112 formed of a resist.
16 is printed with cream solder, and solder balls 117
After mounting, the solder balls 117 are melted to melt the cream solder and the solder balls, so that the solder balls 117 are
Then, a semiconductor device (CSP) 118 as shown in FIG. 5A is formed. Note that the pitch of the electrode portion 116 is 0.8 mm,
Of the CSP.
【００１０】一方、同じく、０．８ｍｍピッチで、２５
ｐｉｎの電極部１２０を有する回路基板１２１を用意す
る。そして、クリーム半田を電極部１２０上に印刷し、
電極部１２０とＣＳＰ１１８の電極部１１６とを相対す
るように位置決めし、その後にリフローで、ＣＳＰ１１
８の半田ボール１１７を、電極部１２０に接合する。こ
の接合された状態が図５の（ｂ）に示されている。On the other hand, similarly, at a pitch of 0.8 mm, 25
A circuit board 121 having a pin electrode section 120 is prepared. Then, cream solder is printed on the electrode section 120,
The electrode unit 120 and the electrode unit 116 of the CSP 118 are positioned so as to face each other, and then the CSP 11 is reflowed.
The eight solder balls 117 are joined to the electrode part 120. This joined state is shown in FIG.
【００１１】[0011]
【発明が解決しようとする課題】しかしながら、上記従
来の半導体装置であるＢＧＡ、ＣＳＰを、半田ボールを
介して、回路基板の電極部へ接合することによって得ら
れる半導体装置の接合構造に関しては、次のような問題
点がある。However, with respect to the bonding structure of a semiconductor device obtained by bonding the above-mentioned conventional semiconductor devices BGA and CSP to an electrode portion of a circuit board via solder balls, the following is described. There is a problem as follows.
【００１２】１）ＢＧＡによる方法の場合 図３の（ａ）および（ｂ）で説明すると、半導体装置
（ＢＧＡ）１０５は、複合材料で、即ち、熱膨張係数が
異なる材料の複合で構成されており、各熱膨張係数は、
シリコンで構成されるＩＣチップ１０２で、２〜３ｐｐ
ｍ／℃であり、ＢＴレジンとガラスで構成されている回
路基板１０１で、１３〜１７ｐｐｍ／℃程度であり、ま
た、封止材１０８はＩＣチップ１０２の熱膨張係数に近
くなるように、合成樹脂にＳｉＯ2 などのフィラーを含
有させてある。1) Method using BGA Referring to FIGS. 3A and 3B, the semiconductor device (BGA) 105 is composed of a composite material, that is, a composite of materials having different thermal expansion coefficients. And each coefficient of thermal expansion is
IC chip 102 made of silicon, 2-3pp
m / ° C., about 13 to 17 ppm / ° C. in the circuit board 101 made of BT resin and glass, and the sealing material 108 is synthesized so as to be close to the thermal expansion coefficient of the IC chip 102. The resin contains a filler such as SiO 2 .
【００１３】従って、半導体装置（ＢＧＡ）１０５の回
路基板１０１側の全体としての熱膨張係数は、本来の回
路基板１０１の材料の熱膨張係数とは異っている。例え
ば、ＮＥＭＡ規格のＦＲ−４の回路基板１０７の熱膨張
係数は１３〜１７ｐｐｍ／℃程度であるから、半導体装
置（ＢＧＡ）１０５を、半田ボールを介して、回路基板
１０７の電極部に接合してなる接合体（パッケージ）
を、ヒートサイクル試験にかけると、その半田接合部
に、可成りの熱応力ストレスを受けることになる。即
ち、熱応力ストレスは、回路基板の中心部の半田接合部
よりも、周辺部の半田接合部に大きくかかる。Therefore, the overall thermal expansion coefficient of the semiconductor device (BGA) 105 on the circuit board 101 side is different from the original thermal expansion coefficient of the material of the circuit board 101. For example, since the thermal expansion coefficient of the FR-4 circuit board 107 of the NEMA standard is about 13 to 17 ppm / ° C., the semiconductor device (BGA) 105 is joined to the electrode portion of the circuit board 107 via solder balls. Joint (package)
Is subjected to a heat cycle test, the solder joint is subjected to considerable thermal stress. That is, the thermal stress is applied more to the solder joints in the peripheral part than in the central part of the circuit board.
【００１４】これを式で表すと Δｌ＝Ｌ×Δα×
ΔＴ （ここで、Δｌは伸び、Ｌは中立点または拘束点からの
距離、Δαは熱膨張係数差、ΔＴは温度差である）。This can be expressed by the following equation: Δl = L × Δα ×
ΔT (where Δl is elongation, L is distance from neutral or constrained point, Δα is thermal expansion coefficient difference, ΔT is temperature difference).
【００１５】また、半田ボール１０４の形状は、半田
量、半導体装置（ＢＧＡ）１０５の重量によっても異な
るが、概して、樽状になっている。更に、レジストにて
形成された電極部１０３の開口の形状は、半田ボールの
方向に向けてストレート（角度＝０度）であり、このた
め、図３の（ｂ）に示すように、電極部１０３の接合面
よりも、半田ボール側の上部くびれ１０９や、電極部１
０６の接合面近傍の下部１１０に熱応力ストレスが集中
し、クラックが生じたり、最悪の場合には、破断するこ
とになる。つまり、接合寿命が短くなり、市場でのトラ
ブルの原因となった。特に、上部くびれ１０９は、電極
部の開口に位置し、その開口縁に当たるので、これによ
って、回路基板の面に沿って、せん断応力が集中し易
い。The shape of the solder ball 104 varies depending on the amount of solder and the weight of the semiconductor device (BGA) 105, but is generally barrel-shaped. Further, the shape of the opening of the electrode portion 103 formed of a resist is straight (angle = 0 degrees) toward the direction of the solder ball. Therefore, as shown in FIG. The upper constriction 109 on the solder ball side with respect to the bonding surface 103 and the electrode portion 1
Thermal stress stress concentrates on the lower part 110 near the joint surface of No. 06, causing cracks or, in the worst case, breaking. That is, the bonding life was shortened, causing troubles in the market. In particular, since the upper constriction 109 is located at the opening of the electrode portion and hits the opening edge, the shear stress tends to concentrate along the surface of the circuit board.
【００１６】２）ＣＳＰによる方法の場合 図５の（ａ）および（ｂ）で説明すると、ＣＳＰによる
方法は、上述のＢＧＡよりも顕著となる。その第一点
は、半導体装置（ＢＧＡ）１０５の場合よりも、半導体
装置（ＣＳＰ）１１８の方が、シリコンＩＣチップ１１
５の熱膨張係数に近づくことである。即ち、ＣＳＰ１１
８は、ＢＧＡ１０５よりも外形寸法が小さくて、シリコ
ンＩＣチップ１１５の大きさに近くなる。また、ＣＳＰ
１１８の回路基板１１３もＢＧＡ１０５の回路基板１０
１よりも薄くなる傾向がある。2) In the case of the method using the CSP Referring to FIGS. 5A and 5B, the method using the CSP is more remarkable than the above-mentioned BGA. The first point is that the semiconductor device (CSP) 118 is more suitable for the silicon IC chip 11 than the semiconductor device (BGA) 105.
5 approaching the coefficient of thermal expansion. That is, CSP11
8 has a smaller outer dimension than the BGA 105 and is close to the size of the silicon IC chip 115. Also, CSP
The circuit board 113 of the BGA 105 and the circuit board 113 of the BGA 105
It tends to be thinner than 1.
【００１７】また、その第二点は、ＢＧＡ１０５のボー
ルピッチよりもＣＳＰ１１８のボールピッチが小さいた
め、ＢＧＡ１０５の電極１０３の面積よりも、ＣＳＰ１
１８の電極１１６の面積が小さく、従って、ボール径も
小さくて、接合強度が弱くなることである。即ち、ＢＧ
Ａ１０５のボールピッチは、ＪＥＤＥＣ、ＥＩＡＪで述
べられているように、１ｍｍ、１．２７ｍｍ、１．５ｍ
ｍとなっているけれども、ＣＳＰ１１８のピッチは１ｍ
ｍよりも小さい（電極部の直径は、概略、配列ピッチの
１／２の径である故に、電極面積が小さい）ので、従っ
て、接合強度も弱くなる。The second point is that, since the ball pitch of the CSP 118 is smaller than the ball pitch of the BGA 105, the area of the electrode 103 of the BGA 105 is smaller than the area of the electrode 103 of the BGA 105.
18 is that the area of the electrode 116 is small, so that the ball diameter is also small, and the bonding strength is weakened. That is, BG
The ball pitch of A105 is 1 mm, 1.27 mm, 1.5 m as described in JEDEC, EIAJ.
m, but the pitch of CSP118 is 1m
m (the diameter of the electrode portion is approximately 径 of the arrangement pitch, so the electrode area is small), and therefore, the bonding strength is also weakened.
【００１８】更に、小径の穴明け作業となると、レーザ
を用いることが多くなり、電極部の開口もストレート
（テーパ角度が０度）にならざるを得ない。また、ポリ
イミド１１２と半田とは、相互接着性がないために、電
極部の開口内での、半田ボール１１７の部分１１９は、
くびれて、凹形状となる。従って、半田ボール１１７の
上部くびれ１２２と下部１２３に対して熱応力ストレス
が集中し、クラックが生じたり、最悪の場合、破断にな
ることがある。Further, in the case of a small-diameter drilling operation, a laser is frequently used, and the opening of the electrode portion must be straight (the taper angle is 0 degree). In addition, since the polyimide 112 and the solder have no mutual adhesiveness, the portion 119 of the solder ball 117 in the opening of the electrode portion is
It becomes constricted and concave. Therefore, thermal stress stress concentrates on the upper constriction 122 and the lower part 123 of the solder ball 117, which may cause cracks or, in the worst case, breakage.
【００１９】これらの問題点を回避する策として、回路
基板１１３と回路基板１２１との間で、半田ボール１１
７相互の空隙に、アンダーフィル材として、樹脂を注入
し、半田ボール１１７にかかる熱応力ストレスを分散さ
せる方法が提唱されたが、樹脂の硬化後に、半導体装置
（ＣＳＰ）１１８を交換する、つまり、リペアーするこ
とが難しくなる。As a measure for avoiding these problems, a solder ball 11 is provided between the circuit board 113 and the circuit board 121.
A method has been proposed in which a resin is injected as an underfill material into the voids of each other to disperse the thermal stress applied to the solder balls 117. However, after the resin is cured, the semiconductor device (CSP) 118 is replaced. , It becomes difficult to repair.
【００２０】本発明は、上記事情に基づいてなされたも
ので、半田ボールなどの金属ボールの括れが発生する箇
所での、絶縁部材のスルーホールに簡単な加工上の工夫
を施し、これによって、熱応力ストレスによる金属ボー
ルのクラック、破断などを回避できるようにした半導体
装置およびその製造方法を提供することを目的とする。The present invention has been made on the basis of the above circumstances, and a simple processing device is applied to a through hole of an insulating member at a place where a metal ball such as a solder ball is constricted. It is an object of the present invention to provide a semiconductor device capable of avoiding cracks, breakage, and the like of a metal ball due to thermal stress and a method of manufacturing the same.
【００２１】[0021]
【課題を解決するための手段】この目的の実現のため、
本発明では、絶縁部材と、前記絶縁部材の片面に配置さ
れた半導体チップと、前記片面に配置され且つ前記半導
体チップと接合する配線パターンと、前記絶縁部材に設
けられたスルーホールと、前記半導体チップ及び前記配
線パターンを封止する封止材を有する半導体装置におい
て、前記片面の反対面における前記スルーホールの開口
径は前記片面における開口径よりも大きいことを特徴と
する。In order to achieve this object,
In the present invention, an insulating member, a semiconductor chip disposed on one surface of the insulating member, a wiring pattern disposed on the one surface and joined to the semiconductor chip, a through hole provided in the insulating member, In a semiconductor device having a sealing material for sealing a chip and the wiring pattern, an opening diameter of the through hole on a surface opposite to the one surface is larger than an opening diameter on the one surface.
【００２２】また、本発明では、半導体装置の製造方法
において、絶縁部材の片面に配線パターンと半導体チッ
プとを配置する工程と、前記配線パターンと前記半導体
チップとを接合する工程と、前記片面と反対の面におけ
る開口径が前記片面における開口径よりも大きくなるよ
うに前記絶縁部材にスルーホールを設ける工程と、前記
絶縁部材の前記片面と前記半導体チップと前記配線パタ
ーンとを封止材で封止する工程とを有することを特徴と
する。Further, according to the present invention, in the method of manufacturing a semiconductor device, a step of arranging a wiring pattern and a semiconductor chip on one surface of an insulating member, a step of joining the wiring pattern and the semiconductor chip, Providing a through hole in the insulating member such that the opening diameter on the opposite surface is larger than the opening diameter on the one surface; and sealing the one surface of the insulating member, the semiconductor chip, and the wiring pattern with a sealing material. And a stopping step.
【００２３】従って、半導体装置およびその接合構造に
おいて、アンダーフィルなしでも、耐クラック性が良
く、接合寿命が十分に得られるという効果を奏する。Therefore, in the semiconductor device and the bonding structure thereof, there is an effect that the crack resistance is good and the bonding life can be sufficiently obtained without the underfill.
【００２４】[0024]
【発明の実施の形態】（第１の実施の形態）以下、本発
明の第１の実施の形態を図１を参照して具体的に説明す
る。図１の（ａ）は、本発明の半導体装置（ＣＳＰ）の
断面図である。該半導体装置２０９は、フレキシブル回
路基板２０１と、フレキシブル回路基板２０１の片側面
にマウントされたＩＣ（半導体）チップ２０６と、フレ
キシブル回路基板を構成する配線パターンである銅箔２
０２とＩＣチップ２０６とを電気的に接続するボンディ
ングワイヤ２１３と、該ＩＣチップ２０６をマウントす
るフレキシブル回路基板２０１の片側面をＩＣチップご
とに封止する封止材２０７とから構成されている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) A first embodiment of the present invention will be specifically described below with reference to FIG. FIG. 1A is a cross-sectional view of a semiconductor device (CSP) of the present invention. The semiconductor device 209 includes a flexible circuit board 201, an IC (semiconductor) chip 206 mounted on one side of the flexible circuit board 201, and a copper foil 2 serving as a wiring pattern forming the flexible circuit board.
The bonding wire 213 electrically connects the IC chip 206 to the IC chip 206 and a sealing material 207 for sealing one side of the flexible circuit board 201 on which the IC chip 206 is mounted for each IC chip.
【００２５】またフレキシブル回路基板２０１は、導電
性の回路パターンである銅箔２０２と絶縁部材であるポ
リイミド２０３とから構成されている。ポリイミドの膜
厚は６０μｍである。また、ポリイミド２０３は銅箔２
０２側では狭く、反対側に向かって広くなるテーパー上
のスルーホール２１４が設けられている。この時、スル
ーホール２１４の側壁部と銅箔２０２を保持するポリイ
ミド２０３の面との間の角度θは６０゜である。またポ
リイミド２０３のスルーホール２１４における銅箔２０
２は電極部２０５として半田ボール２０８と電気的に接
合している。この時の銅箔２０２の膜厚は１８μｍであ
る。半田ボール２０８はフレキシブル回路基板２０１か
ら突出した略球形状でかつスルーホール２１４内でスル
ーホール２１４のテーパー形状にならい、そして電極部
２０５と電気的に接合されている。The flexible circuit board 201 is composed of a copper foil 202 as a conductive circuit pattern and a polyimide 203 as an insulating member. The thickness of the polyimide is 60 μm. The polyimide 203 is made of copper foil 2
The through-hole 214 on the taper that is narrow on the 02 side and widens toward the opposite side is provided. At this time, the angle θ between the side wall of the through hole 214 and the surface of the polyimide 203 holding the copper foil 202 is 60 °. The copper foil 20 in the through hole 214 of the polyimide 203
2 is electrically connected to the solder ball 208 as an electrode portion 205. At this time, the film thickness of the copper foil 202 is 18 μm. The solder ball 208 has a substantially spherical shape protruding from the flexible circuit board 201, follows the tapered shape of the through hole 214 in the through hole 214, and is electrically connected to the electrode portion 205.
【００２６】また、（ｂ）は、その半導体装置を回路基
板２１０に接合した断面図である。マザーボードである
回路基板２１０は片側面に電極部２１１を有している。
図１の（ａ）を用いて説明した本発明の半導体装置２０
９は回路基板２１０と半田ボール２０８を介して接合す
る。半田ボール２０８は回路基板２１０の電極部２１１
と電気的に接合される。また半導体装置２０９と対向す
る回路基板２１０の面は半田レジスト２１２によって覆
われている。ここで、先ず、図１の（ａ）に示す半導体
装置（ＣＳＰ）２０９の製法から説明する。FIG. 2B is a cross-sectional view of the semiconductor device joined to a circuit board 210. A circuit board 210 as a motherboard has an electrode portion 211 on one side.
The semiconductor device 20 of the present invention described with reference to FIG.
9 is joined to the circuit board 210 via the solder balls 208. The solder balls 208 are connected to the electrode portions 211 of the circuit board 210.
Electrically connected to The surface of the circuit board 210 facing the semiconductor device 209 is covered with the solder resist 212. Here, a method of manufacturing the semiconductor device (CSP) 209 shown in FIG.
【００２７】フレキシブル回路基板２０１は、厚さ：１
８μｍの銅箔２０２と、厚さ：６０μｍのポリイミド２
０３とをラミネートしたものを準備し、その銅箔２０２
をエッチングした後に、銅箔２０２上にＮｉメッキある
いはＡｕメッキを施す。その後、絶縁層２０４を設け
る。次に、配線パターンである銅箔２０２の裏面で、Ｃ
Ｏ2 レーザを用いて、ポリイミド２０３に、直径：ａ＝
０．４ｍｍで、ストレートに穴明けし、銅箔２０２を露
出させ、電極部２０５とする。The flexible circuit board 201 has a thickness of 1
8 μm copper foil 202 and 60 μm thick polyimide 2
03 and a copper foil 202
Is etched, Ni plating or Au plating is performed on the copper foil 202. After that, an insulating layer 204 is provided. Next, on the back surface of the copper foil 202 as the wiring pattern, C
Using an O 2 laser, a diameter: a =
A hole is made straight at 0.4 mm to expose the copper foil 202 to form an electrode portion 205.
【００２８】その後、除々に、レーザの出力を下げ、あ
るいは、照射時間を短くして、順次に、０．４３ｍｍの
直径で、０．４５の直径で、また、最終的にｂ＝０．４
７ｍｍの直径で、段々に下向きのテーパを、例えば、約
３０度のテーパー角で穴明け加工し、開口の内周壁を形
成する。なお、ここでの電極部２０５の配列ピッチは
０．８ｍｍ、そのピン数は２５ｐｉｎである。Thereafter, the output of the laser is gradually reduced, or the irradiation time is shortened, so that the diameter is 0.43 mm, the diameter is 0.45, and finally b = 0.4.
With a diameter of 7 mm, a downward taper is gradually drilled, for example, at a taper angle of about 30 degrees to form an inner peripheral wall of the opening. Here, the arrangement pitch of the electrode portions 205 is 0.8 mm, and the number of pins thereof is 25 pins.
【００２９】このような構成のフレキシブル回路基板２
０１を用い、ＩＣチップ２０６をダイボンディング、ワ
イヤボンディングした後、フィラー入りエポキシ樹脂な
どの封止材２０７で、回路基板２０１の表面をトランス
ファーモールドする。その後に、回路基板２０１の裏面
の電極部２０５上にクリーム半田を印刷し、その後に直
径：０．４５ｍｍの半田塊を当該電極部２０５に搭載し
て、リフローで、半田を溶融させ、半田ボール２０８と
して、半導体装置（ＣＳＰ）２０９を構成するのであ
る。The flexible circuit board 2 having such a configuration
Then, the IC chip 206 is die-bonded and wire-bonded, and then the surface of the circuit board 201 is transfer-molded with a sealing material 207 such as a filler-containing epoxy resin. Thereafter, cream solder is printed on the electrode portion 205 on the back surface of the circuit board 201, and then a solder lump having a diameter of 0.45 mm is mounted on the electrode portion 205, and the solder is melted by reflow to form a solder ball. A semiconductor device (CSP) 209 is configured as 208.
【００３０】次に、上述の半導体装置（ＣＳＰ９２０９
を、別に用意した回路基板２１０に接合するプロセスに
ついて、図１の（ｂ）を用いて説明する。ここでは、Ｃ
ＳＰ２０９の電極部２０５に対応した回路基板２１０上
の位置に、電極部２１１を設けている。この回路基板２
１０の電極部２１１の配列ピッチは０．８ｍｍ、そのピ
ン数は２５である。電極部２１１は、銅箔の一部が露出
した部分であり、その表面には、耐熱プリフラックスが
塗布されており、また、電極部２１１以外の銅箔の部分
は半田レジスト２１２で覆われている。Next, the above-described semiconductor device (CSP 9209)
Will be described with reference to FIG. 1B. Here, C
An electrode unit 211 is provided at a position on the circuit board 210 corresponding to the electrode unit 205 of the SP 209. This circuit board 2
The arrangement pitch of the ten electrode portions 211 is 0.8 mm, and the number of pins is 25. The electrode portion 211 is a portion where a part of the copper foil is exposed, a heat-resistant pre-flux is applied to the surface thereof, and a portion of the copper foil other than the electrode portion 211 is covered with a solder resist 212. I have.
【００３１】そして、回路基板２１０の電極部２１１上
にクリーム半田を印刷し、半導体装置（ＣＳＰ）２０９
側に固定された半田ボール２０８と、電極部２１１とを
位置合わせし、当接した後に、リフローし、半田ボール
２０８と電極部２１１とを、接合する。Then, cream solder is printed on the electrode section 211 of the circuit board 210, and the semiconductor device (CSP) 209 is printed.
After the solder ball 208 fixed to the side and the electrode portion 211 are aligned and brought into contact, reflow is performed, and the solder ball 208 and the electrode portion 211 are joined.
【００３２】このように構成された半導体装置の接合構
造は、その後、温度が−２５℃および＋１２５℃に設定
された２つの温度領域内で、ヒートサイクル試験（各３
０分間隔で、交互に１，０００サイクル）を行う。その
耐久試験において、上述の半導体装置およびその接合構
造では、半田ボールにクラックなどの亀裂が認められ
ず、良好な半田付けが行なわれたことを示している。Thereafter, the junction structure of the semiconductor device thus configured is subjected to a heat cycle test (3 each) in two temperature ranges where the temperature is set to -25 ° C. and + 125 ° C.
(1,000 cycles alternately at 0 minute intervals). In the durability test, no crack such as a crack was found in the solder ball in the above-described semiconductor device and the joint structure thereof, indicating that good soldering was performed.
【００３３】なお、この実施の形態では、厚さ：１８μ
ｍの銅箔を用いたが、それが１０〜５０μｍの範囲なら
差し支えなく、また、厚さ：６０μｍのポリイミドを半
田レジストとして用いたが、４０〜１００μｍの間なら
有効であり、更に、レジストの材質としては、ポリイミ
ド以外に、エポキシ樹脂、ウレタン樹脂、フッ素樹脂、
シリコン樹脂、などの樹脂を用いても良い。In this embodiment, the thickness is 18 μm.
Although a copper foil having a thickness of 60 m was used, a polyimide having a thickness of 60 m was used as a solder resist, but it was effective if the thickness was between 40 and 100 m. As materials, besides polyimide, epoxy resin, urethane resin, fluororesin,
A resin such as a silicon resin may be used.
【００３４】また、レジストにて形成された電極部の開
口には、その穴明け手段として、レーザ以外に、エッチ
ャントによるウェットエッチング、あるいは、プラズマ
エッチングなどのドライエッチングを用いても良い。ま
た、ここでは、ＣＯ2 レーザを用いたが、ＣＯ2 以外
に、ＹＡＧ、エキシマレーザなどの高エネルギーレーザ
を用いても良く、また、これらの方法をＭｉｘして採用
しても良い。In addition, in addition to the laser, a wet etching using an etchant or a dry etching such as a plasma etching may be used as a means for making a hole in the opening of the electrode portion formed of the resist. Although a CO 2 laser is used here, a high-energy laser such as a YAG laser or an excimer laser may be used in addition to CO 2 , or these methods may be mixed and adopted.
【００３５】今回、テーパ状の形状は、前述のように、
階段式に穴明けを行って、全体として、すり鉢式の穴形
状にしたが、他の連続式の穴明けで形成しても良い。ま
た、今回は、開口部のテーパには、６０゜のテーパ角を
付けたが、本発明はその他に樽形の半田ボール２０８の
形状を阻外しない範囲、つまり４５度ないし６０度の範
囲で、そのテーパ角度を設定してもよい。This time, the tapered shape is, as described above,
Drilling is performed stepwise to form a mortar type hole as a whole, but it may be formed by other continuous type drilling. Also, in this case, the taper of the opening has a taper angle of 60 °. However, the present invention also has a taper angle in a range that does not obstruct the shape of the barrel-shaped solder ball 208, that is, in a range of 45 degrees to 60 degrees. , The taper angle may be set.
【００３６】また、本発明のスルーホール２１４の側壁
部に半田ボール２０８と濡れ性のよい導電材料を配置す
ることも好ましい。この場合導電材料として、例えば、
銅や錫を用いることが好ましい。その結果、半田ボール
２０８がくびれることなく、スルーホール２１４の形状
にならい、半導体装置の接合信頼性が向上する。また、
本発明はＢＧＡに用いることもできる。It is also preferable to dispose a conductive material having good wettability with the solder ball 208 on the side wall of the through hole 214 of the present invention. In this case, as the conductive material, for example,
It is preferable to use copper or tin. As a result, the solder ball 208 does not become constricted and follows the shape of the through hole 214, and the bonding reliability of the semiconductor device is improved. Also,
The present invention can also be used for BGA.
【００３７】（第２の実施の形態）本発明の第２の実施
の形態を、図２の（ａ）および（ｂ）を参照して、具体
的に説明する。なお、図２の（ａ）は半導体装置（ＣＳ
Ｐ）の断面図であり、その（ｂ）は前記ＣＳＰを回路基
板に接合した断面図を示す。この実施の形態が、第１の
実施の形態と異なる点は、フレキシブル回路基板２０１
のポリイミド２０３にて明けた電極部の開口のテーパ角
と、半田ボール径とが異なるのであって、他は、同じ構
成である。(Second Embodiment) A second embodiment of the present invention will be specifically described with reference to FIGS. 2 (a) and 2 (b). FIG. 2A shows a semiconductor device (CS).
It is sectional drawing of P), and (b) is sectional drawing which joined the said CSP to the circuit board. This embodiment is different from the first embodiment in that a flexible circuit board 201 is provided.
The difference is that the taper angle of the opening of the electrode portion made with the polyimide 203 differs from the solder ball diameter, and the other configuration is the same.
【００３８】テーパ角の形成は、ＣＯ2 レーザを用い
て、α＝０．４ｍｍの径でストレートに穴明けするまで
は同じであるが、その後、公知の方法によって、Ｃ＝
０．５２ｍｍの径内部以外に、レジストを塗布し、エチ
レンジアミンとヒドラジンの混合溶液で、ポリイミド２
０３をエッチングした後に、レジストを剥離して、フレ
キシブル回路基板２０１に、４５度のテーパ角を構成す
る。The formation of the taper angle is the same until a straight hole is formed with a diameter of α = 0.4 mm using a CO 2 laser.
A resist is applied to the inside of the inside of the diameter of 0.52 mm, and polyimide 2 is mixed with a mixed solution of ethylenediamine and hydrazine.
After etching 03, the resist is peeled off to form a 45 ° taper angle on the flexible circuit board 201.
【００３９】なお、ボール塊には直径：０．５ｍｍのも
のを用いるので、第１の実施の形態よりも、半田ボール
が大きくなり、若干の信頼性向上が認められる。他は、
第一の実施の形態と同様であり、その後、−２５℃と＋
１２５℃との２つの温度領域での各３０分で１，０００
サイクルのヒートサイクル試験が行われたが、半田ボー
ルにクラックなどの亀裂は認められなかった。更に、
１，０００サイクル以上の試験も行ったが、１，２００
サイクルまでは、全く亀裂の発生が見られないことが確
認された。Since a ball mass having a diameter of 0.5 mm is used, the solder ball becomes larger than in the first embodiment, and a slight improvement in reliability is recognized. Others
It is the same as the first embodiment.
1,000 in 30 minutes each in two temperature ranges of 125 ° C
A heat cycle test of the cycle was performed, and no cracks such as cracks were found in the solder balls. Furthermore,
Tests over 1,000 cycles were also performed, but 1,200
It was confirmed that no cracks were observed until the cycle.
【００４０】[0040]
【発明の効果】本発明は以上詳述したようになり、半導
体装置のスルーホールに、所要のテーパを付けることに
より、半導体装置と、前記金属ボールを介して接合され
る回路基板との間の熱膨張係数差による熱応力ストレス
の集中を避け、耐クラック性を向上し、接合箇所の長寿
命化を達成することができる。The present invention has been described in detail above. By forming a through hole of a semiconductor device with a required taper, the through hole between the semiconductor device and the circuit board joined via the metal ball is formed. Concentration of thermal stress due to a difference in thermal expansion coefficient can be avoided, crack resistance can be improved, and a longer life of a joint can be achieved.
【図面の簡単な説明】[Brief description of the drawings]
【図１】本発明の第１の実施の形態を（ａ）および
（ｂ）で示す縦断側面図である。FIG. 1 is a longitudinal sectional side view showing a first embodiment of the present invention in (a) and (b).
【図２】同じく、第２の実施の形態を（ａ）および
（ｂ）で示す縦断側面図である。FIG. 2 is a vertical sectional side view showing the second embodiment in (a) and (b).
【図３】従来の実施の形態を（ａ）および（ｂ）で示す
縦断側面図である。FIG. 3 is a longitudinal sectional side view showing a conventional embodiment in (a) and (b).
【図４】同じく、回路基板の平面図である。FIG. 4 is a plan view of the circuit board.
【図５】従来の別の実施の形態を（ａ）および（ｂ）で
示す縦断側面図である。FIG. 5 is a longitudinal sectional side view showing another conventional embodiment in (a) and (b).
１０１ 回路基板 １０２ ＩＣチップ １０３ 電極部 １０４ 半田ボール（金属ボール） １０５ 半導体装置（ＢＧＡ） １０６ 電極部 １０７ 回路基板 １１１ 銅箔 １１２ ポリイミド １１３ フレキシブル回路基板 １１４ 絶縁処理 １１５ ＩＣチップ １１６ 電極部 １１７ 半田ボール（金属ボール） １１８ 半導体装置（ＣＳＰ） １１９ 部分 １２１ 回路基板 １２２ 上部くびれ １２３ 下部 １２４ 空隙 ２０１ 回路基板 ２０２ 銅箔 ２０３ ポリイミド ２０４ 絶縁層 ２０５ 電極部 ２０６ ＩＣチップ ２０７ 封止材 ２０８ 半田ボール（金属ボール） ２０９ 半導体装置（ＣＰＳ） ２１０ 回路基板 ２１１ 電極部 ２１２ レジスト ２１３ ボンディングワイヤ ２１４ スルーホール DESCRIPTION OF SYMBOLS 101 Circuit board 102 IC chip 103 Electrode part 104 Solder ball (metal ball) 105 Semiconductor device (BGA) 106 Electrode part 107 Circuit board 111 Copper foil 112 Polyimide 113 Flexible circuit board 114 Insulation processing 115 IC chip 116 Electrode part 117 Solder ball ( 118 semiconductor device (CSP) 119 part 121 circuit board 122 upper constriction 123 lower part 124 air gap 201 circuit board 202 copper foil 203 polyimide 204 insulating layer 205 electrode part 206 IC chip 207 sealing material 208 solder ball (metal ball) 209 Semiconductor device (CPS) 210 Circuit board 211 Electrode part 212 Resist 213 Bonding wire 214 Through hole
Claims (17)
された半導体チップと、前記片面に配置され且つ前記半
導体チップと接合する配線パターンと、前記絶縁部材に
設けられたスルーホールと、前記半導体チップ及び前記
配線パターンを封止する封止材を有する半導体装置にお
いて、 前記片面の反対面における前記スルーホールの開口径は
前記片面における開口径よりも大きいことを特徴とする
半導体装置。An insulating member, a semiconductor chip disposed on one surface of the insulating member, a wiring pattern disposed on the one surface and joined to the semiconductor chip, a through hole provided in the insulating member, A semiconductor device having a sealing material for sealing a semiconductor chip and the wiring pattern, wherein an opening diameter of the through hole on a surface opposite to the one surface is larger than an opening diameter on the one surface.
ールの外へ突出する突起電極を有することを特徴とする
請求項１に記載の半導体装置。2. The semiconductor device according to claim 1, further comprising a protruding electrode projecting from the inside of the through hole to the outside of the through hole.
とする請求項２に記載の半導体装置。3. The semiconductor device according to claim 2, wherein said protruding electrode has a substantially spherical shape.
ることを特徴とする請求項２に記載の半導体装置。4. The semiconductor device according to claim 2, wherein said semiconductor device is bonded to a circuit board via said projecting electrode.
有することを特徴とする請求項１に記載の半導体装置。5. The semiconductor device according to claim 1, wherein the through hole has a conductive material on a side wall.
の間の角度が４５度ないし６０度の範囲にあることを特
徴とする請求項１に記載の半導体装置。6. The semiconductor device according to claim 1, wherein an angle between the one surface and a side wall of the through hole is in a range of 45 degrees to 60 degrees.
を特徴とする請求項５に記載の半導体装置。7. The semiconductor device according to claim 5, wherein said conductive material is made of copper or tin.
とする請求項２に記載の半導体装置。8. The semiconductor device according to claim 2, wherein the protruding electrodes are made of solder.
離れるに連れて大きくなることを特徴とする請求項１に
記載の半導体装置。9. The semiconductor device according to claim 1, wherein the diameter of the through hole increases as the distance from the one surface increases.
体チップとを配置する工程と、前記配線パターンと前記
半導体チップとを接合する工程と、前記片面と反対の面
における開口径が前記片面における開口径よりも大きく
なるように前記絶縁部材にスルーホールを設ける工程
と、前記絶縁部材の前記片面と前記半導体チップと前記
配線パターンとを封止材で封止する工程とを有する半導
体装置の製造方法。10. A step of arranging a wiring pattern and a semiconductor chip on one surface of an insulating member, a step of joining the wiring pattern and the semiconductor chip, and a step of opening an opening on a surface opposite to the one surface to an opening on the one surface. A method of manufacturing a semiconductor device, comprising: providing a through hole in the insulating member so as to be larger than a diameter; and sealing the one surface of the insulating member, the semiconductor chip, and the wiring pattern with a sealing material. .
ホールの外に向かって突出する突起電極を設ける工程を
有することを特徴とする請求項１０に記載の半導体装置
の製造方法。11. The method for manufacturing a semiconductor device according to claim 10, further comprising the step of providing a protruding electrode projecting from inside of said through hole to outside of said through hole.
徴とする請求項１１に記載の半導体装置の製造方法。12. The method according to claim 11, wherein the protruding electrodes are substantially spherical.
を有する工程を含むことを特徴とする請求項１０に記載
の半導体装置の製造方法。13. The method according to claim 10, wherein the through hole includes a step of having a conductive material on a side wall.
との間の角度が４５度ないし６０度の範囲とする工程を
有することを特徴とする請求項１０に記載の半導体装置
の製造方法。14. The method according to claim 10, further comprising the step of setting an angle between the one surface and a side wall of the through hole in a range of 45 degrees to 60 degrees.
とを特徴とする請求項１３に記載の半導体装置の製造方
法。15. The method according to claim 13, wherein the conductive material is made of copper or tin.
徴とする請求項１０に記載の半導体装置の製造方法。16. The method according to claim 10, wherein the protruding electrodes are made of solder.
ら離れるに連れて大きくなることを特徴とする請求項１
０に記載の半導体装置の製造方法。17. The device according to claim 1, wherein the diameter of the through hole increases with increasing distance from the one surface.
0. A method for manufacturing a semiconductor device according to item 0.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5053098A JPH11251353A (en) | 1998-03-03 | 1998-03-03 | Semiconductor device and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5053098A JPH11251353A (en) | 1998-03-03 | 1998-03-03 | Semiconductor device and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH11251353A true JPH11251353A (en) | 1999-09-17 |
Family
ID=12861557
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5053098A Pending JPH11251353A (en) | 1998-03-03 | 1998-03-03 | Semiconductor device and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH11251353A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1087440A2 (en) * | 1999-09-22 | 2001-03-28 | Texas Instruments Incorporated | Modeling technique to increase device reliability |
| JP2002033417A (en) * | 2000-07-17 | 2002-01-31 | Rohm Co Ltd | Semiconductor device |
| JP2005026650A (en) * | 2003-07-01 | 2005-01-27 | Northrop Grumman Corp | Electronic device package assembly |
| JP2005280044A (en) * | 2004-03-29 | 2005-10-13 | Brother Ind Ltd | Process of manufacturing inkjet head |
| JP2012069984A (en) * | 1999-09-20 | 2012-04-05 | Texas Instr Inc <Ti> | Method for increasing device reliability by selectively depopulating solder balls from foot print of ball grid array package |
| JP2017201677A (en) * | 2016-05-06 | 2017-11-09 | 旭徳科技股▲ふん▼有限公司 | Method for manufacturing circuit board |
-
1998
- 1998-03-03 JP JP5053098A patent/JPH11251353A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012069984A (en) * | 1999-09-20 | 2012-04-05 | Texas Instr Inc <Ti> | Method for increasing device reliability by selectively depopulating solder balls from foot print of ball grid array package |
| EP1087440A2 (en) * | 1999-09-22 | 2001-03-28 | Texas Instruments Incorporated | Modeling technique to increase device reliability |
| JP2002033417A (en) * | 2000-07-17 | 2002-01-31 | Rohm Co Ltd | Semiconductor device |
| JP2005026650A (en) * | 2003-07-01 | 2005-01-27 | Northrop Grumman Corp | Electronic device package assembly |
| JP4714814B2 (en) * | 2003-07-01 | 2011-06-29 | ノースロップ グラマン システムズ コーポレーション | Electronic device package assembly |
| JP2005280044A (en) * | 2004-03-29 | 2005-10-13 | Brother Ind Ltd | Process of manufacturing inkjet head |
| US7467468B2 (en) | 2004-03-29 | 2008-12-23 | Brother Kogyo Kabushiki Kaisha | Method for manufacturing an ink-jet head |
| JP2017201677A (en) * | 2016-05-06 | 2017-11-09 | 旭徳科技股▲ふん▼有限公司 | Method for manufacturing circuit board |
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