JP2001044319A - Wiring board and mounting structure thereof - Google Patents

Wiring board and mounting structure thereof

Info

Publication number
JP2001044319A
JP2001044319A JP21278399A JP21278399A JP2001044319A JP 2001044319 A JP2001044319 A JP 2001044319A JP 21278399 A JP21278399 A JP 21278399A JP 21278399 A JP21278399 A JP 21278399A JP 2001044319 A JP2001044319 A JP 2001044319A
Authority
JP
Japan
Prior art keywords
connection terminal
terminal
solder
wiring board
connection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21278399A
Other languages
Japanese (ja)
Inventor
Shinya Kawai
信也 川井
Masahiko Azuma
昌彦 東
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP21278399A priority Critical patent/JP2001044319A/en
Publication of JP2001044319A publication Critical patent/JP2001044319A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • H01L2924/15172Fan-out arrangement of the internal vias
    • H01L2924/15174Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Combinations Of Printed Boards (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

PROBLEM TO BE SOLVED: To improve mechanical strength of the bases of connection terminals for jointing by brazing and hence improve their long-term connection reliability, by relaxing thermal stress, mechanical stress, impact, and stress concentration caused during mounting or at use. SOLUTION: A metallized interconnection layer 2 is formed on the surface and/or in the interior of an insulating substrate, and a plurality of terminal electrodes 3 which are in electrical conduction with the layer 2 are formed on the main surface of the substrate. A connection terminal 14, having the shape of a truncated cone or of a truncated polygonal pyramid, whose top is smaller than its base 14a for joint, is jointed to the corresponding electrode 3 via a solder.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、セラミックス,ガ
ラスセラミックスあるいは合成樹脂等の絶縁体から成る
半導体素子収納用パッケージ等の配線基板に関し、また
その配線基板を、セラミックス,ガラスセラミックスあ
るいは合成樹脂等の絶縁体から成るマザーボード等の回
路基板の表面にロウ付けした、半導体素子搭載用の配線
基板の実装構造に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board such as a package for housing a semiconductor element made of an insulator such as ceramics, glass ceramics or synthetic resin. The present invention relates to a mounting structure of a wiring board for mounting a semiconductor element, which is brazed to a surface of a circuit board such as a motherboard made of an insulator.

【0002】[0002]

【従来の技術】従来、セラミックス配線基板は、絶縁基
板の表面および/または内部にメタライズ配線層が配設
された構造からなる。その代表例として、半導体素子、
特にLSI(大規模集積回路素子)等の半導体集積回路
素子を収容するための半導体素子収納用パッケージ(以
下、半導体パッケージという)があり、一般に半導体パ
ッケージは、アルミナセラミックス等のセラミックス,
ガラスセラミックス,有機樹脂等から成る。特にアルミ
ナセラミックスを用いた半導体パッケージでは、絶縁基
板の表面および内部に、タングステン(W),モリブデ
ン(Mo)等の高融点金属から成る複数のメタライズ配
線層が配設され、表面に実装される半導体素子と電気的
に接続される。
2. Description of the Related Art Conventionally, a ceramic wiring substrate has a structure in which a metallized wiring layer is provided on the surface and / or inside of an insulating substrate. Typical examples are semiconductor devices,
Particularly, there is a semiconductor device housing package (hereinafter, referred to as a semiconductor package) for housing a semiconductor integrated circuit device such as an LSI (large-scale integrated circuit device). Generally, a semiconductor package is made of ceramics such as alumina ceramics.
It consists of glass ceramics, organic resin, etc. Particularly, in a semiconductor package using alumina ceramics, a plurality of metallized wiring layers made of a refractory metal such as tungsten (W) and molybdenum (Mo) are provided on the surface and inside of an insulating substrate, and a semiconductor mounted on the surface is provided. It is electrically connected to the element.

【0003】また、絶縁基板の下面または側面には、外
部の回路基板と電気的に接続するための接続用端子電極
(以下、端子電極と略す)が備えられ、この端子電極は
メタライズ配線層と電気的に接続される。さらに、その
絶縁基板の上面中央部には、半導体素子との接続用電極
が形成され、半導体素子を載置した後、樹脂接着剤等に
より封止される。あるいは、絶縁基板の上面中央部に、
半導体素子を収容するためのキャビティが形成され、そ
のキャビティに半導体素子を載置収容した後、蓋体によ
って気密封止する。
[0003] A connection terminal electrode (hereinafter abbreviated as terminal electrode) for electrically connecting to an external circuit board is provided on the lower surface or side surface of the insulating substrate. The terminal electrode is connected to a metallized wiring layer. Electrically connected. Further, an electrode for connection to the semiconductor element is formed at the center of the upper surface of the insulating substrate, and after the semiconductor element is mounted, it is sealed with a resin adhesive or the like. Alternatively, at the center of the upper surface of the insulating substrate,
A cavity for accommodating the semiconductor element is formed, and the semiconductor element is placed and accommodated in the cavity, and hermetically sealed with a lid.

【0004】一般に、半導体素子の集積度が高まるほ
ど、それに形成される電極数も増大するが、これに伴い
半導体素子を収納する半導体パッケージにおいて、外部
の回路基板と接続するための端子電極数も増大する。ま
た、外部の回路基板は、一般にガラス−エポキシ樹脂等
から成る所謂プリント基板である。ところが、端子電極
数を増大させるとパッケージの大型化を招くため、パッ
ケージの小型化への要求と相まって、パッケージの端子
電極の形成密度を高くする必要がある。
In general, as the degree of integration of a semiconductor device increases, the number of electrodes formed on the semiconductor device also increases. With this, in a semiconductor package containing the semiconductor device, the number of terminal electrodes for connecting to an external circuit board also increases. Increase. The external circuit board is generally a so-called printed board made of glass-epoxy resin or the like. However, when the number of terminal electrodes is increased, the size of the package is increased. Therefore, it is necessary to increase the formation density of the terminal electrodes of the package in combination with the demand for downsizing of the package.

【0005】そして、従来、半導体パッケージにおける
端子電極の構造として、パッケージの下面にコバール
(Fe−Ni−Co合金)などの金属ピンを接続したピ
ングリッドアレイ(PGA)が一般的であり製品化され
ているが、最近、パッケージの4つの側面に導出された
メタライズ配線層にガルウイング状(L字状)の金属ピ
ンが接続されたタイプのクワッドフラットパッケージ
(QFP)、パッケージの4つの側面に電極パッドを備
え、リードピンがないリードレスチップキャリア(LC
C)、Siチップをフリップチツプ実装したチップサイ
ズパッケージ(CSP)、さらに絶縁基板の下面に半田
からなる球状端子を多数配置したボールグリッドアレイ
(BGA)等があり、これらの中でもBGAが最も高密
度化が可能である。
Conventionally, as a structure of a terminal electrode in a semiconductor package, a pin grid array (PGA) in which metal pins such as Kovar (Fe-Ni-Co alloy) are connected to the lower surface of the package is generally and commercialized. Recently, a quad flat package (QFP) in which gull-wing (L-shaped) metal pins are connected to metallized wiring layers led out on four sides of the package, and electrode pads on four sides of the package With lead pins and leadless chip carrier (LC
C), a chip size package (CSP) in which a Si chip is flip-chip mounted, and a ball grid array (BGA) in which a number of spherical terminals made of solder are arranged on the lower surface of an insulating substrate. Of these, BGA has the highest density. Is possible.

【0006】このボールグリッドアレイ(BGA)の端
子電極は、その端子電極パッドに半田などの金属ロウ材
(以下、ロウ材ともいう)からなる球状端子をロウ付け
することにより構成される。この球状端子を外部の回路
基板の配線導体上に載置当接させ、しかる後、球状端子
を約200〜400℃で加熱溶融し、配線導体に接合さ
せることによって回路基板上に実装する。このような実
装構造により、半導体パッケージの内部に収容されてい
る半導体素子は、その各電極がメタライズ配線層および
端子電極を介して外部の回路基板に電気的に接続され
る。
The terminal electrodes of the ball grid array (BGA) are formed by brazing spherical terminals made of a metal brazing material such as solder (hereinafter also referred to as brazing material) to the terminal electrode pads. The spherical terminal is placed and abutted on a wiring conductor of an external circuit board, and thereafter, the spherical terminal is heated and melted at about 200 to 400 ° C. and bonded to the wiring conductor to be mounted on the circuit board. With such a mounting structure, each electrode of the semiconductor element housed inside the semiconductor package is electrically connected to an external circuit board via the metallized wiring layer and the terminal electrode.

【0007】[0007]

【発明が解決しようとする課題】しかしながら、配線基
板を有する半導体パッケージに半導体素子を収容し、プ
リント基板等の回路基板に実装した場合、半導体素子動
作時に発する熱が配線基板と回路基板の両方に繰り返し
伝熱され、これにより配線基板と回路基板との熱膨張差
に起因する大きな熱応力が発生する。特に、接続端子数
が300を超える半導体パッケージや大型の半導体パッ
ケージでは、その熱応力の影響が大きくなり、そのため
半導体素子の作動および停止の繰り返しによって、熱応
力が配線基板下面の端子電極の外周部および回路基板の
配線導体と接続端子との接合界面に作用し、その結果端
子電極が配線基板から剥離する、接続端子が配線導体か
ら剥離する、あるいは配線基板本体が破壊されるといっ
た事態が生じ、半導体パッケージ用の配線基板とプリン
ト基板等の回路基板とを長期にわたり安定に電気的接続
させることができないという問題点があった。
However, when a semiconductor element is housed in a semiconductor package having a wiring board and mounted on a circuit board such as a printed board, heat generated during operation of the semiconductor element is applied to both the wiring board and the circuit board. Heat is repeatedly transmitted, thereby generating a large thermal stress due to a difference in thermal expansion between the wiring board and the circuit board. In particular, in the case of a semiconductor package having a number of connection terminals exceeding 300 or a large semiconductor package, the influence of the thermal stress increases. Therefore, the thermal stress is repeatedly applied to the outer peripheral portion of the terminal electrode on the lower surface of the wiring board by repeatedly operating and stopping the semiconductor element. And acts on the bonding interface between the wiring conductor of the circuit board and the connection terminal, and as a result, a situation occurs in which the terminal electrode peels off from the wiring board, the connection terminal peels off from the wiring conductor, or the wiring board body is destroyed, There has been a problem that a wiring board for a semiconductor package and a circuit board such as a printed board cannot be stably electrically connected for a long period of time.

【0008】また、このような半導体パッケージに使用
される配線基板として、セラミックス,ガラスセラミッ
クスを用いた場合、強度や気密封止性およびメタライズ
配線層等との多層化技術などの点で、有機樹脂を用いる
場合に比べ高い信頼性が得られている。しかし、セラミ
ックス,ガラスセラミックスから成る配線基板の熱膨張
係数は約4〜7×10-6/℃程度であるのに対して、半
導体パッケージを実装する回路基板として多用されてい
るプリント基板の熱膨張係数は11〜18×10-6/℃
と非常に大きいため、両者間の大きな熱膨張係数差によ
って大きな熱応力が発生する。その結果、半導体パッケ
ージ用の配線基板を回路基板に、長期にわたり安定に接
続させることが困難であった。
Further, when ceramics or glass ceramics are used as a wiring board used for such a semiconductor package, an organic resin is used in view of strength, hermetic sealing properties, and a technique of forming a multilayer with a metallized wiring layer. High reliability is obtained as compared with the case of using. However, the thermal expansion coefficient of a wiring board made of ceramics and glass ceramics is about 4 to 7 × 10 −6 / ° C., whereas the thermal expansion coefficient of a printed board often used as a circuit board for mounting a semiconductor package. The coefficient is 11-18 × 10 -6 / ° C.
Is very large, a large thermal stress is generated due to a large difference in thermal expansion coefficient between the two. As a result, it has been difficult to stably connect a wiring board for a semiconductor package to a circuit board for a long time.

【0009】そして、従来のBGA型の半導体パッケー
ジを回路基板に実装する際のプロセスとその実装構造を
図9に、従来のBGA型の半導体パッケージを回路基板
に実装したときの接続端子部の断面図を図10に示す。
FIG. 9 shows a process of mounting a conventional BGA type semiconductor package on a circuit board and its mounting structure. FIG. 9 shows a cross section of a connection terminal portion when the conventional BGA type semiconductor package is mounted on a circuit board. The figure is shown in FIG.

【0010】図9(a)によれば、半導体パッケージA
は、配線基板1とメタライズ配線層2と接続用の端子電
極3を有し、配線基板1の上面中央部には半導体素子4
がガラスフリット,樹脂等の接着剤を介して接着固定さ
れ、半導体素子4はメタライズ配線層2とボンディング
ワイヤ5により電気的に接続され、さらに半導体素子4
上を合成樹脂6等により覆う(マウントする)ことによ
り封止する。
FIG. 9A shows that the semiconductor package A
Has a wiring board 1, a metallized wiring layer 2 and a terminal electrode 3 for connection, and a semiconductor element 4
Are bonded and fixed via an adhesive such as glass frit or resin, and the semiconductor element 4 is electrically connected to the metallized wiring layer 2 by bonding wires 5.
The top is sealed by covering (mounting) with a synthetic resin 6 or the like.

【0011】そして、図9(b)に示すように、端子電
極3上に、Pbを37重量%,Snを63重量%含有す
るPb37−Sn63共晶半田等から成る半田層8をス
クリーン印刷法等により印刷塗布し、その上に同じPb
37−Sn63共晶半田等から成る半田ボール7を接合
し、実装時にリフローすることにより、図9(c)に示
すように半田ボール7を端子電極3上に接合し固定させ
る。尚、12は半田ボール7がリフロー及び接合時に溶
融し半田層8と相互拡散し、自重により偏平になった接
続端子である。
Then, as shown in FIG. 9B, a solder layer 8 made of Pb37-Sn63 eutectic solder containing 37% by weight of Pb and 63% by weight of Sn is screen-printed on the terminal electrode 3. Etc., and apply the same Pb
Solder balls 7 made of 37-Sn63 eutectic solder or the like are joined and reflowed during mounting, so that the solder balls 7 are joined and fixed on the terminal electrodes 3 as shown in FIG. 9C. Reference numeral 12 denotes a connection terminal in which the solder ball 7 is melted at the time of reflow and bonding and diffuses with the solder layer 8 to be flattened by its own weight.

【0012】一方、図9(c)に示すように、回路基板
B上の配線導体10上にも、上記と同様にしてPb37
−Sn63共晶半田等から成る半田層9を形成し、その
後接続端子12を半田層9上に位置合わせして当接する
ように載置した後、図9(d)に示すように、リフロー
して半導体パッケージAを回路基板Bに実装する。
On the other hand, as shown in FIG. 9C, Pb 37 is also formed on the wiring conductor 10 on the circuit board B in the same manner as described above.
After forming the solder layer 9 made of -Sn63 eutectic solder or the like, the connection terminal 12 is positioned on the solder layer 9 so as to be in contact therewith, and then reflowed as shown in FIG. 9D. Then, the semiconductor package A is mounted on the circuit board B.

【0013】このように、従来のBGA型の半導体パッ
ケージAの実装構造において、半田ボール7と、半田ボ
ール7を配線基板1上の端子電極3に接合するための半
田層8と、回路基板Bの配線導体10上に形成する半田
層9とは、全て同じ材質、例えばPb37−Sn63共
晶半田から成る。そのため、半田ボール7は、リフロー
時に半田層8,9と相互に溶融拡散し、自重により偏平
につぶれるため元の形状を保つことができず、図10の
ような略楕円形状の接続端子12が形成される。
As described above, in the mounting structure of the conventional BGA type semiconductor package A, the solder ball 7, the solder layer 8 for joining the solder ball 7 to the terminal electrode 3 on the wiring board 1, and the circuit board B The solder layer 9 formed on the wiring conductor 10 is made of the same material, for example, Pb37-Sn63 eutectic solder. Therefore, the solder ball 7 melts and diffuses with the solder layers 8 and 9 at the time of reflow and is flattened by its own weight, so that the solder ball 7 cannot maintain its original shape, and the connection terminal 12 having a substantially elliptical shape as shown in FIG. It is formed.

【0014】また、上記熱応力は主に接続端子12と端
子電極3との界面に集中し、図10中のW方向に働く。
尚、図10中では右側が半導体パッケージの外側(点線
の矢印)となる。また、この熱応力は剪断方向のX方向
成分と引張り方向のY方向成分との2方向成分に分ける
ことができる。一般的には、この熱応力のX方向成分が
大きいため、接続端子12と端子電極3との界面に沿っ
て、半導体パッケージの外側から中心側に向けてクラッ
クが進行するモードの破壊が最も多い。あるいは接続端
子12本体にクラックが進行する場合もある。他には、
熱応力のY方向成分により、配線基板1と端子電極3と
の界面が剥解したり、配線基板1本体が破壊する場合も
ある。
The thermal stress is mainly concentrated on the interface between the connection terminal 12 and the terminal electrode 3 and acts in the direction W in FIG.
In FIG. 10, the right side is the outside of the semiconductor package (dotted arrow). Further, this thermal stress can be divided into two components of an X-direction component in the shear direction and a Y-direction component in the tensile direction. Generally, since the X-direction component of the thermal stress is large, the mode in which the crack progresses from the outside of the semiconductor package toward the center side along the interface between the connection terminal 12 and the terminal electrode 3 is most frequently destroyed. . Alternatively, cracks may progress in the connection terminal 12 body. aside from that,
The interface between the wiring board 1 and the terminal electrode 3 may be exfoliated or the main body of the wiring board 1 may be broken due to the Y-direction component of the thermal stress.

【0015】このとき、接続端子12の形状が図10の
ような略楕円形状であると、接続端子12と端子電極3
の接続部の界面にくびれが生じ、この界面に沿って大き
な応力集中が生じ、その結果前記界面でクラックが急速
に進行し易くなる。また、半導体パッケージAと回路基
板Bとの接続部の高さhが不十分であると、熱応力のせ
ん断方向のX方向成分が増加し、接続端子12と端子電
極3との界面でのクラックの進行がさらに促進される。
At this time, if the shape of the connection terminal 12 is substantially elliptical as shown in FIG.
At the interface of the connection portion, necking occurs, and a large stress concentration occurs along the interface. As a result, cracks easily progress at the interface. Further, if the height h of the connection between the semiconductor package A and the circuit board B is insufficient, the X-direction component of the thermal stress in the shear direction increases, and the crack at the interface between the connection terminal 12 and the terminal electrode 3 is increased. Progress is further promoted.

【0016】さらには、半田層8,9と半田ボール7
が、リフロー時に互いに溶融、拡散するのに伴い、半田
および特に半田ペースト中に含まれる不純物成分や空気
が拡散して上昇し、接続端子12と端子電極3との界面
にボイド等の欠焔を生成し、界面の機械的強度を低下さ
せる。また、半田層8,9と半田ボール7にPb37−
Sn63共晶半田を用いると、リフロー時に接続端子1
2全体が溶融するため、実装時に半導体パッケージAと
回路基板Bとの平行度を保つのが難しく、その結果局所
的に機械的強度の低い箇所ができ易いといった問題も生
じる。
Furthermore, the solder layers 8 and 9 and the solder balls 7
However, as they melt and diffuse with each other at the time of reflow, the solder and especially the impurity components and air contained in the solder paste diffuse and rise, and a flame such as a void is generated at the interface between the connection terminal 12 and the terminal electrode 3. Produces and reduces the mechanical strength of the interface. In addition, Pb37-
When the Sn63 eutectic solder is used, the connection terminals 1
Since the whole 2 is melted, it is difficult to maintain the parallelism between the semiconductor package A and the circuit board B at the time of mounting, and as a result, there is a problem that a portion having low mechanical strength is easily formed locally.

【0017】さらには、熱応力以外にも、半導体パッケ
ージAを実装した回路基板Bを、各種電子機器本体にに
ネジ,ピン,接着剤等を用いて実装する際に発生する機
械的応力や回路基板Bのたわみ,変形等による機械的応
力、電子機器本体の落下時等に加わる衝撃などの様々な
応力が、配線基板1下面の端子電極3の外周部および回
路基板Bの配線導体10と接続端子12との接合界面に
作用する。その結果、端子電極3が配線基板1から剥離
したり、接続端子12が配線導体10から剥離し、半導
体パッケージAを回路基板Bに長期にわたり安定に接続
させることが困難であった。
Further, besides the thermal stress, there are mechanical stresses and circuit stresses generated when the circuit board B on which the semiconductor package A is mounted is mounted on various electronic device bodies by using screws, pins, adhesives and the like. Various stresses such as mechanical stress due to bending and deformation of the board B and impact applied when the electronic device body falls down are connected to the outer peripheral portion of the terminal electrode 3 on the lower surface of the wiring board 1 and the wiring conductor 10 of the circuit board B. It acts on the joint interface with the terminal 12. As a result, the terminal electrode 3 peels off from the wiring board 1 or the connection terminal 12 peels off from the wiring conductor 10, and it has been difficult to stably connect the semiconductor package A to the circuit board B for a long time.

【0018】このような問題を改善する為に、例えば図
11に示すように、高融点半田から成る半田ボール13
と、低融点のPb37−Sn63共晶半田から成る半田
層8,9を用いた実装構造が一般的である。この構成で
は、リフロー時に半田ボール13が溶融しない温度で実
装するため、半導体パッケージAと回路基板Bとの接続
部の間隔hを高く保つことができ、応力集中をある程度
媛和することができる。しかし、この構成においても、
接続部界面が応力集中の起こり易いくびれのある構造と
なるため、長期信頼性に関して更なる改善が要求されて
いた。
In order to solve such a problem, for example, as shown in FIG.
And a mounting structure using solder layers 8 and 9 made of low melting point Pb37-Sn63 eutectic solder. In this configuration, since the solder balls 13 are mounted at a temperature at which the solder balls 13 do not melt during reflow, the distance h between the connecting portions between the semiconductor package A and the circuit board B can be kept high, and stress concentration can be reduced to some extent. However, even in this configuration,
Since the connection interface has a constricted structure in which stress concentration is likely to occur, further improvement in long-term reliability has been required.

【0019】また、さらに配線密度が向上した場合に、
接続部界面の応力集中を緩和する為に接続部の高さhを
確保しようとすると、端子電極3同士の間隔が半田ボー
ル7の直径に制限されるため、端子電極3同士の間隔以
上の高さを確保することができないとともに、高密度実
装化への大きな障害となっていた。
Further, when the wiring density is further improved,
If the height h of the connection portion is to be ensured in order to reduce the stress concentration at the interface of the connection portion, the distance between the terminal electrodes 3 is limited to the diameter of the solder ball 7, so that the height between the terminal electrodes 3 is higher than the distance between the terminal electrodes 3. In addition, it was not possible to secure the high density, and it was a big obstacle to high density mounting.

【0020】上記種々の問題を解消するために、半田ボ
ールとロウ材を用いて半導体パッケージを回路基板上に
実装する実装技術に関し、以下のような改良技術が提案
されている。半導体チップの表面に形成された複数の端
子を導電体を通じて実装基板の導電部に導通させる半導
体装置において、導電体は実装時溶融しない導電球から
なるものであって、さらに導電球の表面に半田等の導電
層を付着したものが公知である(従来例1:特開平8−
115997号公報参照)。しかしながら、この従来例
1においても、上記応力集中の緩和等の点で十分なもの
とはいえず、従って上記種々の問題を十分に解消する構
成は未だ見い出されていない。
In order to solve the above-mentioned various problems, the following improved techniques have been proposed for a mounting technique for mounting a semiconductor package on a circuit board using solder balls and brazing material. In a semiconductor device for conducting a plurality of terminals formed on the surface of a semiconductor chip to a conductive portion of a mounting board through a conductor, the conductor is made of conductive spheres that do not melt at the time of mounting, and is further soldered to the surface of the conductive spheres. (See, for example, Japanese Unexamined Patent Publication No.
No. 115997). However, even in the conventional example 1, it cannot be said that it is sufficient in terms of relaxation of the stress concentration and the like, and therefore, a configuration which sufficiently solves the above various problems has not been found yet.

【0021】従って、本発明は上記事情に鑑みて完成さ
れたものであり、その目的は、例えば熱膨張係数の小さ
いセラミックス,ガラスセラミックスから成る半導体パ
ッケージ用の配線基板を、ガラス−エポキシ樹脂等から
成り前記配線基板よりも熱膨張係数が大きい外部の回路
基板上に実装するにあたり、強固かつ長期にわたり安定
した接続状態を維持できるため高い信頼性を有し、また
高密度実装に対応できる配線基板およびその実装構造を
提供することである。
Accordingly, the present invention has been completed in view of the above circumstances, and an object of the present invention is to provide a wiring board for a semiconductor package made of, for example, ceramics or glass ceramics having a small coefficient of thermal expansion by using glass-epoxy resin or the like. When mounting on an external circuit board having a larger coefficient of thermal expansion than the wiring board, the wiring board has high reliability because it can maintain a strong and stable connection state for a long time, and a wiring board capable of supporting high-density mounting. It is to provide the mounting structure.

【0022】[0022]

【課題を解決するための手段】本発明の配線基板は、配
線導体層が表面および/または内部に形成された絶縁基
板の主面に前記配線導体層と導通する複数の端子電極が
設けられ、接合基部より先端部が小さい円錐台形状また
は多角錐台形状の接続端子を前記端子電極上にロウ材を
介して接合したことを特徴とする。
According to the present invention, there is provided a wiring board having a plurality of terminal electrodes provided on the main surface of an insulating substrate having a wiring conductor layer formed on the surface and / or inside thereof, the terminal electrodes being electrically connected to the wiring conductor layer. A connection terminal having a truncated cone shape or a truncated polygonal pyramid shape having a tip portion smaller than a joining base portion is joined to the terminal electrode via a brazing material.

【0023】本発明は、上記構成により、半導体パッケ
ージ等用の配線基板をプリント基板等の他の回路基板上
に実装するにあたり、実装時または使用時に生じる熱応
力、様々な機械的応力、衝撃を緩和低減し、また応力集
中を緩和し、さらにロウ付けされる接合基部の機械的強
度を向上させて、接続の長期信頼性を向上させる。また
本発明において、配線基板の接続端子が設置される主面
の少なくとも四隅の接続端子を本発明のように構成すれ
ば良く、接続部の長期信頼性向上に効果がある。
According to the present invention, when a wiring board for a semiconductor package or the like is mounted on another circuit board such as a printed circuit board by the above configuration, thermal stress, various mechanical stresses and impacts generated during mounting or use are reduced. It reduces the relaxation, reduces the stress concentration, and improves the mechanical strength of the joint base to be brazed, thereby improving the long-term reliability of the connection. In the present invention, the connection terminals at least at the four corners of the main surface on which the connection terminals of the wiring board are installed may be configured as in the present invention, which is effective in improving the long-term reliability of the connection portion.

【0024】本発明において、好ましくは、前記円錐台
形状または多角錐台形状の接続端子に代えて、中央部が
括れた鼓型の接続端子としたことを特徴とする。これに
より、接続端子による接続部の高さを十分に保持でき、
熱応力の剪断方向成分を減少させ、クラック等の発生を
抑制できる。
In the present invention, preferably, instead of the truncated cone-shaped or polygonal truncated pyramid-shaped connection terminal, a drum-shaped connection terminal having a constricted central portion is provided. Thereby, the height of the connection part by the connection terminal can be sufficiently maintained,
It is possible to reduce the shear stress component of the thermal stress and suppress the occurrence of cracks and the like.

【0025】また本発明において、好ましくは、前記接
続端子の接合基部の底角が60°〜85°、接合基部の
最大径R1と先端部の最小径R2との比R2/R1が
0.4〜0.95であることを特徴とする。また好まし
くは、鼓型の接続端子の場合、その接合基部の底角が4
5°〜85°、接合基部の最大径R3と括れ部の最小径
R4との比R4/R3が0.3〜0.95であることを
特徴とする。底角を上記範囲内とすることにより、接続
部の高さを十分に保持するとともに応力集中を緩和する
ことができる。また、最大径と最小径との比を上記範囲
内とすることで、接続端子の先端部の大きさを保持して
実装時の強度を維持し、応力集中を緩和することができ
る。
In the present invention, preferably, the base angle of the joint base of the connection terminal is 60 ° to 85 °, and the ratio R2 / R1 of the maximum diameter R1 of the joint base to the minimum diameter R2 of the tip is 0.4. 0.90.95. Preferably, in the case of a drum-shaped connection terminal, the base angle of the joint base is 4 mm.
5 ° to 85 °, and the ratio R4 / R3 of the maximum diameter R3 of the joining base portion and the minimum diameter R4 of the constricted portion is 0.3 to 0.95. By setting the base angle within the above range, the height of the connection portion can be sufficiently maintained and stress concentration can be reduced. By setting the ratio between the maximum diameter and the minimum diameter within the above range, the size of the tip of the connection terminal can be maintained, the strength at the time of mounting can be maintained, and stress concentration can be reduced.

【0026】また、本発明の前記接続端子は、前記ロウ
材よりも高融点の金属若しくは合金、または前記ロウ材
の融点よりも熱分解温度が高い導電性樹脂から成ること
が好適である。このような構成により、接続端子の初期
形状が保持されるため、接続端子と端子電極の接合部の
界面に生じるくびれを小さくすることができ、この界面
に沿って生じる応力集中が緩和され、界面でクラックが
急速に進行するのを抑制することができる。さらに、配
線基板と回路基板との接続部の高さが十分に保持され、
熱応力の剪断方向成分が増加するのを防止することがで
きる。本発明では、この導電性樹脂は、導電性に優れた
樹脂、または導電性物質を含有することにより導電性を
付与された絶縁性樹脂を意味する。
The connection terminal of the present invention is preferably made of a metal or an alloy having a higher melting point than the brazing material, or a conductive resin having a higher thermal decomposition temperature than the melting point of the brazing material. With such a configuration, the initial shape of the connection terminal is maintained, so that the necking generated at the interface between the connection terminal and the terminal electrode can be reduced, and the stress concentration generated along this interface is alleviated. Thus, it is possible to suppress the crack from advancing rapidly. Furthermore, the height of the connection between the wiring board and the circuit board is sufficiently maintained,
It is possible to prevent the shear stress component of the thermal stress from increasing. In the present invention, the conductive resin means a resin excellent in conductivity or an insulating resin provided with conductivity by containing a conductive substance.

【0027】前記導電性樹脂は、Au,Ag,Cu,A
l,Ni,Fe,Pd,Pt,W,Mo,Mn,Pd,
Sn,Bi,Sb,In,Cのうちの1種以上の元素を
含有することが好ましく、これらの元素は導電性に優
れ、化学的安定性も高い。前記導電性樹脂は、熱硬化性
樹脂または紫外線硬化型樹脂を含有することが望まし
い。
The conductive resin is made of Au, Ag, Cu, A
1, Ni, Fe, Pd, Pt, W, Mo, Mn, Pd,
It preferably contains at least one element of Sn, Bi, Sb, In, and C, and these elements have excellent conductivity and high chemical stability. The conductive resin desirably contains a thermosetting resin or an ultraviolet curable resin.

【0028】また、前記導電性樹脂のヤング率は前記配
線導体のヤング率よりも低いことが好ましい。前記導電
性樹脂のヤング率は60GPa(ギガパスカル)以下が
良く、接続端子をある程度変形し易くすることで応力緩
和に有効である。
Preferably, the conductive resin has a Young's modulus lower than that of the wiring conductor. The conductive resin preferably has a Young's modulus of 60 GPa (gigapascal) or less, and is effective in reducing stress by making the connection terminal easily deformable to some extent.

【0029】本発明の配線基板の実装構造は、上記配線
基板を、前記接続端子を介して他の回路基板の配線導体
上にロウ材により接合させたことを特徴とする。これに
より、半導体素子等が搭載される配線基板を、熱応力、
機械的応力、衝撃等のストレスに対する耐久性に優れた
実装構造により他の回路基板に実装でき、従って長期に
わたり高い信頼性でもって半導体素子等を使用し得る。
A mounting structure of a wiring board according to the present invention is characterized in that the wiring board is joined to a wiring conductor of another circuit board by a brazing material via the connection terminal. As a result, the wiring board on which the semiconductor element and the like are mounted is reduced in thermal stress,
A mounting structure having excellent durability against stresses such as mechanical stress and impact can be mounted on another circuit board, so that a semiconductor element or the like can be used with high reliability for a long time.

【0030】そして、本発明の配線基板は、基本的に、
セラミックス,ガラスセラミックスまたは樹脂等の絶縁
基板の一主面に半導体素子が載置固定され、その表面お
よび/または内部に配線導体層としてのメタライズ配線
層が形成され、他方主面に接続用の端子電極(パッド)
が設けてあり、その端子電極上に突起状の接続端子をロ
ウ材としての半田を介して接合した構成である。
The wiring board of the present invention basically comprises
A semiconductor element is mounted and fixed on one main surface of an insulating substrate such as ceramics, glass ceramics or resin, and a metallized wiring layer as a wiring conductor layer is formed on the surface and / or inside, and connection terminals are formed on the other main surface. Electrode (pad)
Is provided, and a protruding connection terminal is joined to the terminal electrode via solder as a brazing material.

【0031】[0031]

【発明の実施の形態】本発明の配線基板およびその実装
構造について以下に説明する。図1は本発明の第一の実
施形態を示し、半導体パッケージAを構成する配線基板
の断面図、図2は図1の配線基板の接続端子部の拡大断
面図、図3は配線基板を他の回路基板Bに実装した実装
構造の断面図、図4は図3の接続端子部の拡大断面図で
ある。また、図5は本発明の第二の実施形態を示し、半
導体パッケージAを構成する配線基板の断面図、図6は
図5の配線基板の接続端子部の拡大断面図、図7は図5
の配線基板を他の回路基板Bに実装した実装構造の断面
図、図8は図7の接続端子部の拡大断面図である。
DESCRIPTION OF THE PREFERRED EMBODIMENTS A wiring board and a mounting structure thereof according to the present invention will be described below. FIG. 1 shows a first embodiment of the present invention, and is a cross-sectional view of a wiring board constituting a semiconductor package A, FIG. 2 is an enlarged cross-sectional view of a connection terminal portion of the wiring board of FIG. 1, and FIG. FIG. 4 is an enlarged sectional view of the connection terminal portion shown in FIG. 5 shows a second embodiment of the present invention, and is a cross-sectional view of a wiring board constituting the semiconductor package A, FIG. 6 is an enlarged cross-sectional view of a connection terminal portion of the wiring board of FIG. 5, and FIG.
8 is a cross-sectional view of a mounting structure in which this wiring board is mounted on another circuit board B, and FIG. 8 is an enlarged cross-sectional view of the connection terminal portion of FIG.

【0032】図1に示すように、本発明の第一の実施形
態による半導体パッケージAは配線基板1を本体とし、
その表面および/または内部に配線導体層としてのメタ
ライズ配線層2が形成され、その実装用の下面に、メタ
ライズ配線層2に導通しかつ接続端子14を接合させる
端子電極3が設けられ、配線基板1の上面中央部には半
導体素子4がガラス,樹脂等の接着剤を介して接着固定
される。半導体素子4は、メタライズ配線層2とボンデ
ィングワイヤ5により電気的に接続され、その上から合
成樹脂6等により覆う(マウントする)ことにより封止
する。また、半導体素子4を配線基板1上に載置し電気
的に接続する構成としては、他に配線基板1上面中央部
に半田バンプ等を用いて直接載置するフリップチップ実
装や、配線基板1上面にキャビティを形成し、キャビテ
ィ内に載置しその上から蓋体により気密封止する構成等
がある。
As shown in FIG. 1, a semiconductor package A according to a first embodiment of the present invention has a wiring board 1 as a main body,
A metallized wiring layer 2 as a wiring conductor layer is formed on the surface and / or inside thereof, and a terminal electrode 3 that is electrically connected to the metallized wiring layer 2 and joins the connection terminal 14 is provided on a lower surface for mounting the wiring board. A semiconductor element 4 is adhered and fixed to the center of the upper surface of 1 via an adhesive such as glass or resin. The semiconductor element 4 is electrically connected to the metallized wiring layer 2 by a bonding wire 5, and is sealed by covering (mounting) it with a synthetic resin 6 or the like. In addition, as a configuration in which the semiconductor element 4 is mounted on the wiring board 1 and electrically connected thereto, other examples include flip-chip mounting in which the semiconductor element 4 is directly mounted on a central portion of the upper surface of the wiring board 1 using a solder bump or the like; There is a configuration in which a cavity is formed on the upper surface, placed in the cavity, and hermetically sealed with a lid from above.

【0033】また、配線基板1の表面および/または内
部にはメタライズ配線層2が形成され、半導体素子4と
配線基板1下面の端子電極3とを電気的に接続する。こ
の端子電極3には、ロウ材としての半田を介して接続端
子14が接合される。そして、本発明の端子電極14
は、図2に示すように、接合基部14aより先端部14
bが小さい円錐台形状または多角錐台形状である。ま
た、図1,図2のように、配線基板1下面には多数の端
子電極3が形成され、これに接続端子14が半田8を介
して接合される。
Further, a metallized wiring layer 2 is formed on the surface and / or inside of the wiring board 1 to electrically connect the semiconductor element 4 to the terminal electrodes 3 on the lower surface of the wiring board 1. The connection terminal 14 is joined to the terminal electrode 3 via solder as a brazing material. And the terminal electrode 14 of the present invention
2, as shown in FIG.
b is a small truncated cone or a truncated polygon. Also, as shown in FIGS. 1 and 2, a large number of terminal electrodes 3 are formed on the lower surface of the wiring board 1, and connection terminals 14 are joined to the terminal electrodes 3 via solder 8.

【0034】このような本発明の接続端子14は以下の
ようにして設置する。配線基板1の端子電極3上に、半
田8をスクリーン印刷法,グラビア印刷法等の各種印刷
塗布法、あるいはディスペンサー法,ディップ法等によ
り形成し、その上に予め所定形状に成形した接続端子1
4を、その先端部14bよりも断面形状の大きい接合基
部14aが配線基板1下面側となるようにして載置す
る。その後、リフロー炉,赤外線炉等により、半田8は
溶融するが接続端子14は溶融しない温度あるいは分解
しない温度に加熱して半田8を溶融させ、接続端子14
を配線基板1下面に接着固定させる。そして、図3,図
4のように、半導体パッケージAの接続端子14を、回
路基板Bの配線導体10上に半田9を介して半田付け
(ロウ付け)により接合し実装する。
The connection terminal 14 of the present invention is installed as follows. Solder 8 is formed on terminal electrode 3 of wiring board 1 by various printing application methods such as screen printing method, gravure printing method, or dispenser method, dip method, and the like, and connection terminal 1 previously formed into a predetermined shape thereon.
4 is mounted such that the joint base 14 a having a larger cross-sectional shape than the tip 14 b is on the lower surface side of the wiring board 1. Thereafter, the solder 8 is melted by a reflow oven, an infrared oven, or the like to a temperature at which the solder 8 is melted but the connection terminal 14 is not melted or decomposed.
Is adhered and fixed to the lower surface of the wiring board 1. Then, as shown in FIGS. 3 and 4, the connection terminals 14 of the semiconductor package A are joined and mounted on the wiring conductors 10 of the circuit board B via solder 9 by soldering (brazing).

【0035】このような本発明の実装構造は、回路基板
Bの配線導体10の表面に半田9を形成し、半導体パッ
ケージAの接続端子14が回路基板B上の半田9に当接
するように位置合わせして載置し、半田9を溶融させ接
続端子14を回路基板B上に接合固定させることにより
得られる。本発明において、接続端子14の接続手順は
前記手順に限定するものではなく、回路基板Bの配線導
体10上に接続端子14を接合固定した後、半導体パッ
ケージA側に接続端子14を接合しても構わない。
In such a mounting structure of the present invention, the solder 9 is formed on the surface of the wiring conductor 10 of the circuit board B, and the connection terminals 14 of the semiconductor package A are positioned so as to contact the solder 9 on the circuit board B. It is obtained by mounting together, melting the solder 9 and bonding and fixing the connection terminal 14 on the circuit board B. In the present invention, the connection procedure of the connection terminal 14 is not limited to the above procedure. After the connection terminal 14 is bonded and fixed on the wiring conductor 10 of the circuit board B, the connection terminal 14 is bonded to the semiconductor package A side. No problem.

【0036】また、本発明の第二の実施形態は、図5に
示すように、図1と同様の半導体パッケージAの下面の
端子電極3に、中央部が括れた鼓型の接続端子15を接
合させる。この接続端子15は、2つの接続端子15
a,15bより構成される複合型のものであり、円錐台
形状または多角錘台形状の接続端子15aの接合基部を
半導体パッケージA下面側にして端子電極3上にロウ付
けされ、円錐台形状または多角錘台形状の接続端子15
bの先端部と接続端子15aの先端部が接合されるよう
に、接続端子15bをロウ付けする。そして、配線基板
1の下面に多数の端子電極3が形成され、図6に示すよ
うに、接続端子15aの接合基部(底部)を端子電極3
上に半田8を介して接合し、接続端子15bの先端部を
接続端子15aの先端部に半田16を介して接合して接
続端子15が形成される。また、接続端子15は、全体
を一体的に作製したものであっても良い。
In the second embodiment of the present invention, as shown in FIG. 5, a drum-shaped connection terminal 15 having a central portion is attached to a terminal electrode 3 on the lower surface of a semiconductor package A similar to that of FIG. Join. This connection terminal 15 has two connection terminals 15
a, 15b, and is brazed onto the terminal electrode 3 with the connection base of the connection terminal 15a in the shape of a truncated cone or a truncated polygonal pyramid facing the lower surface of the semiconductor package A, and is shaped like a truncated cone or Frustum-shaped connection terminal 15
The connection terminal 15b is brazed so that the front end of the connection terminal 15b and the front end of the connection terminal 15a are joined. Then, a large number of terminal electrodes 3 are formed on the lower surface of the wiring board 1, and as shown in FIG.
The connection terminal 15 is formed by bonding the upper end of the connection terminal 15b to the upper end of the connection terminal 15a with the solder 16 via the solder 16. Further, the connection terminal 15 may be integrally formed as a whole.

【0037】このような本発明の接続端子15は以下の
ようにして設置される。接続端子15a部は、上記第一
の実施形態の接続端子14と同様に接合する。そして、
接続端子15aの先端部に、半田16をスクリーン印刷
法,グラビア印刷法等の各種印刷塗布法、あるいはディ
スペンサー法,ディップ法等により形成し、その上に接
続端子15bの先端部を当接させる。次いで、半田16
は溶融するが接続端子15a,15bは溶融しない温
度、または半田16は溶融するが接続端子15a,15
bは分解しない温度に、上記と同様の手段で加熱し、接
続端子15a上に接続端子15bを接合固定することに
より、接続端子15が得られる。
The connection terminal 15 of the present invention is installed as follows. The connection terminal 15a is joined in the same manner as the connection terminal 14 of the first embodiment. And
The solder 16 is formed on the tip of the connection terminal 15a by various printing coating methods such as screen printing and gravure printing, or by a dispenser method, dipping method, or the like, and the tip of the connection terminal 15b is brought into contact with the solder 16. Next, solder 16
Is melted but the connection terminals 15a and 15b are not melted, or the solder 16 is melted but the connection terminals 15a and 15b are melted.
b is heated to a temperature at which it does not decompose by the same means as described above, and the connection terminal 15b is joined and fixed on the connection terminal 15a, whereby the connection terminal 15 is obtained.

【0038】そして、図5の半導体パッケージAの接続
端子15を、回路基板Bの配線導体10上にロウ付けし
て実装する。そのとき、図8に示すように、プリント基
板等の絶縁基板11を本体とする回路基板Bの主面に
は、配線導体10が端子電極3と対応するように形成さ
れてあり、この配線導体10上に、半田8,9,16お
よび接続端子15を介して、半導体パッケージAと回路
基板Bとが電気的に接続される。このような本発明の第
二の実施形態による実装構造は、回路基板Bの配線導体
10の表面に上記と同様にして半田9を形成し、半導体
パッケージA側の接続端子15が半田9に当接するよう
に位置合わせし、半田9を上記と同様にして溶融させ、
接続端子15を配線導体10上に接合させることで得ら
れる。
Then, the connection terminals 15 of the semiconductor package A of FIG. 5 are mounted on the wiring conductors 10 of the circuit board B by brazing. At this time, as shown in FIG. 8, a wiring conductor 10 is formed on a main surface of a circuit board B having an insulating substrate 11 such as a printed board as a main body so as to correspond to the terminal electrode 3. The semiconductor package A and the circuit board B are electrically connected to each other via the solders 8, 9, 16 and the connection terminals 15. In such a mounting structure according to the second embodiment of the present invention, the solder 9 is formed on the surface of the wiring conductor 10 of the circuit board B in the same manner as described above, and the connection terminal 15 on the semiconductor package A side contacts the solder 9. Are aligned so that they touch each other, and the solder 9 is melted in the same manner as above.
It is obtained by joining the connection terminal 15 on the wiring conductor 10.

【0039】また、接続端子15の作製、設置プロセス
について、上記のプロセスに限らず、回路基板Bの配線
導体10上に予め接続端子15を接合しておき半導体パ
ッケージAと回路基板Bを接合する、または、接続端子
15aを配線基板1の端子電極3上に、接続端子15b
を回路基板Bの配線導体10上にそれぞれ設置した後、
接続端子15aと接続端子15bとをロウ付けする、と
いうように構成することも可能である。さらに、半田
8,9,16は必ずしも同じ材質とする必要はなく、必
要に応じて他のロウ材や導電性樹脂への変更も可能であ
る。
The process for producing and installing the connection terminals 15 is not limited to the above-described process. The connection terminals 15 are bonded in advance on the wiring conductors 10 of the circuit board B, and the semiconductor package A and the circuit board B are bonded. Alternatively, the connection terminal 15a is placed on the terminal electrode 3 of the wiring board 1,
Are placed on the wiring conductors 10 of the circuit board B, respectively.
The connection terminal 15a and the connection terminal 15b may be brazed. Furthermore, the solders 8, 9, and 16 do not necessarily need to be made of the same material, and can be changed to another brazing material or conductive resin if necessary.

【0040】本発明の第三の実施形態を図12に示す。
同図において、中央部が括れた鼓状の接続端子20を一
体的に形成したものである。尚、22はその側面であ
り、側面22は直線的または曲線的に構成しても良い。
この接続端子20の設置プロセスは、上記接続端子15
と同様である。但し、半田16が不要なことはいうまで
もない。尚、21は接続端子20の接合基部である上
面、23は回路基板Bの配線導体10に接合される下面
である。
FIG. 12 shows a third embodiment of the present invention.
In the figure, a drum-shaped connection terminal 20 having a central portion constricted is integrally formed. Incidentally, reference numeral 22 denotes the side surface, and the side surface 22 may be formed linearly or curvedly.
The installation process of the connection terminal 20 is performed according to the connection terminal 15.
Is the same as However, it goes without saying that the solder 16 is unnecessary. In addition, 21 is an upper surface which is a joining base of the connection terminal 20, and 23 is a lower surface which is joined to the wiring conductor 10 of the circuit board B.

【0041】本発明の接続端子14,15,20は、半
田8,9,16の融点よりも高い融点を有する金属若し
くは合金、または半田8,9,16の融点よりも高い熱
分解温度を有する導電牲樹脂から成ることが好ましく、
最適には、接続端子14,15,20の材料の融点,熱
分解温度がロウ付け時の熱処理温度よりも高温であるこ
とが良い。このような組み合わせの一例として、接続端
子14,15,20をPb90−Sn10(Pbを90
重量%,Snを10重量%含有する)高温半田またはA
g−エポキシ樹脂(Ag含有エポキシ樹脂)系の導電性
樹脂、半田8,9,16をPb37−Sn63共晶半田
とする構成がある。尚、Pb90−Sn10高温半田の
「高温」とは、半田8,9,16のリフロー時に溶融さ
れる半田8,9,16用の金属ロウ材に対して、接続端
子14,15,20の融点または熱分解温度が、前記金
属ロウ材の融点よりも相対的に高温であるという意味で
ある。
The connection terminals 14, 15, and 20 of the present invention have a metal or alloy having a melting point higher than the melting points of the solders 8, 9, and 16, or have a thermal decomposition temperature higher than the melting points of the solders 8, 9, and 16. Preferably, it is made of a conductive resin,
Optimally, the melting point and the thermal decomposition temperature of the material of the connection terminals 14, 15, 20 are preferably higher than the heat treatment temperature at the time of brazing. As an example of such a combination, the connection terminals 14, 15, 20 are connected to Pb90-Sn10 (Pb
Wt%, containing 10% by weight of Sn)
There is a configuration in which a g-epoxy resin (Ag-containing epoxy resin) -based conductive resin and solders 8, 9, and 16 are Pb37-Sn63 eutectic solders. The "high temperature" of the Pb90-Sn10 high-temperature solder refers to the melting point of the connection terminals 14, 15, 20 with respect to the metal brazing material for the solders 8, 9, 16 melted during reflow of the solders 8, 9, 16. Alternatively, it means that the thermal decomposition temperature is relatively higher than the melting point of the metal brazing material.

【0042】接続端子14,15,20を導電牲樹脂で
構成した場合、導電牲樹脂による応力緩和効果によりさ
らに接続部の長期信頼性が向上する上、有害物質である
Pbを含む半田を用いないので環境汚染を低減すること
ができる。しかし、この場合、溶融した半田8,9,1
6の表面張力によるセルフアライメント効果が得られな
い為、実装時の位置合わせ精度が要求される。また、接
続端子14,15,20を導電性樹脂で構成する場合、
導電性を有する樹脂または絶縁性樹脂に金属粉末,合金
粉末等の導電性粒子を含有させたものとする。導電性を
有する樹脂としては、ポリアセチレン系樹脂,ポリフェ
ニレン系樹脂,イオン性樹脂等があり、絶縁性樹脂とし
ては、エポキシ系樹脂,ウレタン系樹脂,アクリル系樹
脂,ポリイミド系樹脂,ポリエステル系樹脂,フェノ−
ル系樹脂等が良い。
When the connection terminals 14, 15, and 20 are made of a conductive resin, the long-term reliability of the connection portion is further improved by the stress relaxation effect of the conductive resin, and solder containing Pb, which is a harmful substance, is not used. Therefore, environmental pollution can be reduced. However, in this case, the molten solder 8, 9, 1
Since the self-alignment effect due to the surface tension of No. 6 cannot be obtained, positioning accuracy at the time of mounting is required. When the connection terminals 14, 15, 20 are made of conductive resin,
It is assumed that conductive resin or insulating resin contains conductive particles such as metal powder and alloy powder. Examples of the conductive resin include polyacetylene resin, polyphenylene resin, and ionic resin. Examples of the insulating resin include epoxy resin, urethane resin, acrylic resin, polyimide resin, polyester resin, and pheno resin. −
Metal-based resin is good.

【0043】絶縁性樹脂に含有させる導電性粒子として
は、Au,Ag,Cu,Al,Ni,Fe,Pd,P
t,W,Mo,Mn,Pb,Sn,Bi,Sb,In,
Cから成る元素群のうちの1種以上の元素の粉末で(例
えば金属粉末)、または前記元素群のうちの少なくとも
1種以上の元素を含む化合物で(例えば合金粉末)が良
い。これらの元素は導電性に優れ、化学的安定性が高
い。より好適には、Au,Ag,Cu,Ni,Pd,P
t,Cのうちの1種以上の元素の粉末、またはこれらの
うちの少なくとも1種以上の元素を含む化合物である。
最適には、Au,Ag,Cuのうちの1種以上の元素の
粉末、またはこれらのうちの少なくとも1種以上の元素
を含む化合物である。
The conductive particles contained in the insulating resin include Au, Ag, Cu, Al, Ni, Fe, Pd, P
t, W, Mo, Mn, Pb, Sn, Bi, Sb, In,
A powder of one or more elements of the element group consisting of C (for example, metal powder) or a compound containing at least one element of the above element group (for example, alloy powder) is preferable. These elements have excellent conductivity and high chemical stability. More preferably, Au, Ag, Cu, Ni, Pd, P
It is a powder of at least one element of t and C, or a compound containing at least one of these elements.
Most preferably, it is a powder of one or more of Au, Ag, and Cu, or a compound containing at least one of these elements.

【0044】また、上記導電性樹脂は熱硬化性樹脂また
は紫外線硬化型樹脂を含むのが良く、さらに接続端子1
4,15,20の成形時に硬化処理を施しておくことが
その初期形状を保つために望ましい。前記熱硬化性樹
脂,紫外線硬化型樹脂は、その熱分解温度が半田8,
9,16の融点よりも高いのが良く、最適には、ロウ付
け時の熱処理温度よりも高いことが望ましい。さらに、
接続端子14,15a,15bは、半導体パッケージA
上に接合する前に硬化処理を終了していることがその形
状維持のため望ましい。熱硬化性樹脂,紫外線硬化型樹
脂としては、エポキシ系樹脂,ウレタン系樹脂,アクリ
ル系樹脂,ポリイミド系樹脂,ポリエステル系樹脂,フ
ェノール系樹脂等がある。
The conductive resin preferably contains a thermosetting resin or a UV-curable resin.
It is desirable to perform a hardening treatment at the time of molding of 4, 15, and 20 in order to maintain the initial shape. The thermosetting resin and the ultraviolet curing resin have a thermal decomposition temperature of solder 8,
It is preferable that the melting point is higher than the melting points 9 and 16, and most preferably higher than the heat treatment temperature during brazing. further,
The connection terminals 14, 15a, 15b are connected to the semiconductor package A
It is desirable that the curing process be completed before joining on top to maintain its shape. Examples of the thermosetting resin and the ultraviolet curing resin include an epoxy resin, a urethane resin, an acrylic resin, a polyimide resin, a polyester resin, and a phenol resin.

【0045】また、接続端子14,15,20用の導電
性樹脂は、そのヤング率が配線導体10のヤング率より
も小さいことが良く、応力の緩和に効果的である。具体
的には、導電性樹脂のヤング率は60GPa(ギガパス
カル)以下が良く、より好適には30GPa以下、最適
には15GPa以下が良い。このような所望のヤング率
を得るには、樹脂成分と導電性粒子の選択、それらの配
合比、硬化条件等を適宜変えることにより行う。
The conductive resin for the connection terminals 14, 15, 20 preferably has a Young's modulus smaller than the Young's modulus of the wiring conductor 10, and is effective in relieving stress. Specifically, the Young's modulus of the conductive resin is preferably 60 GPa (gigapascal) or less, more preferably 30 GPa or less, and most preferably 15 GPa or less. Such a desired Young's modulus is obtained by appropriately selecting the resin component and the conductive particles, their mixing ratio, curing conditions and the like.

【0046】また、第一の実施形態による接続端子14
は、その底角αが60°〜85°、接合基部14aの最
大径R1と先端部14bの最小径R2との比R2/R1
が0.4〜0.95であることが好ましい。α<60°
の場合、接続部の高さw1を十分に保つことができず、
85°<αの場合、応力集中の緩和効果が十分得られな
い。より好ましくはα=65°〜83°、最適にはα=
70°〜80°が望ましい。また、R2/R1<0.4
の場合、配線導体10と接続端子14の界面部が小さく
なりすぎて強度が低下し、0.95<R2/R1の場
合、応力集中の緩和効果が十分得られない。より好まし
くはR2/Rl=0.45〜0、90であり、最適には
R2/Rl=0.50〜0.85である。
The connection terminal 14 according to the first embodiment
Is a ratio R2 / R1 between the maximum diameter R1 of the joining base 14a and the minimum diameter R2 of the tip 14b, the base angle α of which is 60 ° to 85 °.
Is preferably 0.4 to 0.95. α <60 °
In the case of, the height w1 of the connection portion cannot be sufficiently maintained,
If 85 ° <α, the effect of reducing stress concentration cannot be sufficiently obtained. More preferably α = 65 ° to 83 °, optimally α =
70 ° to 80 ° is desirable. Also, R2 / R1 <0.4
In the case of (1), the interface between the wiring conductor 10 and the connection terminal 14 becomes too small and the strength is reduced. When 0.95 <R2 / R1, the effect of reducing stress concentration cannot be sufficiently obtained. More preferably, R2 / R1 = 0.45 to 0, 90, and most preferably, R2 / R1 = 0.50 to 0.85.

【0047】本発明の第二の実施形態による接続端子1
5は、その底角βが45°〜85°、接合基部の最大径
R3と括れ部の最小径R4との比R4/R3が0.3〜
0.95であることが好ましい。β<45°の場合、接
続部の高さw2を十分に保つことができず、85°<β
の場合、応力集中の緩和効果が十分得られない。より好
ましくはβ=50°〜83°、最適にはβ=55°〜8
0°が望ましい。また、R4/R3<0.3の場合、配
線導体10と接続端子15の界面部が小さくなりすぎて
強度が低下し、0.95<R4/R3の場合、応力集中
の緩和効果が十分得られない。より好ましくはR4/R
3=0.45〜0、90であり、最適にはR4/R3=
0.50〜0.85である。
The connection terminal 1 according to the second embodiment of the present invention
5, the base angle β is 45 ° to 85 °, and the ratio R4 / R3 of the maximum diameter R3 of the joint base and the minimum diameter R4 of the constricted portion is 0.3 to 0.3.
It is preferably 0.95. When β <45 °, the height w2 of the connection portion cannot be sufficiently maintained, and 85 ° <β
In the case of (1), the effect of reducing stress concentration cannot be sufficiently obtained. More preferably β = 50 ° to 83 °, optimally β = 55 ° to 8
0 ° is desirable. In the case of R4 / R3 <0.3, the interface between the wiring conductor 10 and the connection terminal 15 is too small, and the strength is reduced. In the case of 0.95 <R4 / R3, the effect of relaxing stress concentration is sufficiently obtained. I can't. More preferably R4 / R
3 = 0.45-0,90, and optimally R4 / R3 =
It is 0.50 to 0.85.

【0048】尚、接続端子15において、接続端子15
aと接続端子15bは必ずしも同形状である必要はな
く、接続端子15aの底角β1が接続端子15bの底角
β2よりも小さいことが好ましく、その場合接続部の応
力集中を緩和し、接続部の高さw2をさらに確保できる
構成となる。
In the connection terminal 15, the connection terminal 15
a and the connection terminal 15b do not necessarily have to have the same shape, and it is preferable that the base angle β1 of the connection terminal 15a is smaller than the base angle β2 of the connection terminal 15b. Height w2 can be further secured.

【0049】本発明の第三の実施形態による接続端子2
0は、その底角βが45°〜85°、接合基部の最大径
R3と括れ部の最小径R4との比R4/R3が0.3〜
0.95であることが好ましい。β<45°の場合、接
続部の高さw3を十分に保つことができず、85°<β
の場合、応力集中の緩和効果が十分得られない。より好
ましくはβ=50°〜83°、最適にはβ=55°〜8
0°が望ましい。また、R4/R3<0.3の場合、配
線導体10と接続端子20の界面部が小さくなりすぎて
強度が低下し、0.95<R4/R3の場合、応力集中
の緩和効果が十分得られない。より好ましくはR4/R
3=0.55〜0、90であり、最適にはR4/R3=
0.60〜0.85である。
The connection terminal 2 according to the third embodiment of the present invention
0, the base angle β is 45 ° to 85 °, and the ratio R4 / R3 of the maximum diameter R3 of the joining base portion and the minimum diameter R4 of the constricted portion is 0.3 to
It is preferably 0.95. When β <45 °, the height w3 of the connection portion cannot be sufficiently maintained, and 85 ° <β
In the case of (1), the effect of reducing stress concentration cannot be sufficiently obtained. More preferably β = 50 ° to 83 °, optimally β = 55 ° to 8
0 ° is desirable. When R4 / R3 <0.3, the interface between the wiring conductor 10 and the connection terminal 20 becomes too small, and the strength is reduced. When 0.95 <R4 / R3, the effect of reducing stress concentration is sufficiently obtained. I can't. More preferably R4 / R
3 = 0.55-0,90, and optimally R4 / R3 =
0.60 to 0.85.

【0050】尚、接続端子20において、上面21の直
径と下面23の直径は必ずしも同一である必要はなく、
上面21の直径が下面23の直径よりも大きいことが好
ましく、その場合接続部の応力集中を緩和し、接続部の
高さw3をさらに確保できる構成となる。
In the connection terminal 20, the diameter of the upper surface 21 and the diameter of the lower surface 23 do not necessarily have to be the same.
It is preferable that the diameter of the upper surface 21 is larger than the diameter of the lower surface 23. In this case, stress concentration at the connection portion is reduced, and the height w3 of the connection portion can be further secured.

【0051】かくして、本発明は、半導体素子のオン,
オフ時等の温度変化に伴って、配線基板1と回路基板B
との間の熱膨張差により発生する熱応力が生じた場合、
接続端子14,15,20は初期形状が保持されている
ため、また接続端子14,15,20と端子電極3との
接合部の形状が界面部分に括れがないため、大きな応力
集中が生じる構造ではなく、その結果クラックの発生、
進行等が抑制され、半導体パッケージAを回路基板Bに
長期にわたり安定的に接続させることができ、高い長期
信頼性が得られる。
Thus, the present invention provides a method for turning on and off a semiconductor element.
The wiring board 1 and the circuit board B
When thermal stress occurs due to the difference in thermal expansion between
Since the initial shape of the connection terminals 14, 15, and 20 is maintained, and the shape of the joint between the connection terminals 14, 15, and 20 and the terminal electrode 3 is not constricted at the interface, a structure in which a large stress concentration occurs. But not as a result of cracking,
The progress and the like are suppressed, and the semiconductor package A can be stably connected to the circuit board B for a long time, and high long-term reliability can be obtained.

【0052】本発明の接続端子14,15,20用の材
料として、導電性樹脂を用いた場合には、半田8と端子
電極3との間に集中する応力が、ある程度の弾性を有す
る導電性樹脂によりさらに緩和される結果、クラック等
の発生が抑制され、接続部の長期信頼性がさらに向上す
る。この導電性樹脂による応力緩和効果は、熱応力のみ
ならず各種の応力に対して有効に働き、少なくとも四隅
の端子電極3上に導電性樹脂から成る接続端子14,1
5,20を設置することにより、応力緩和効果が得られ
る。
When a conductive resin is used as the material for the connection terminals 14, 15, 20 of the present invention, the stress concentrated between the solder 8 and the terminal electrode 3 is reduced to a certain level by a conductive material having some elasticity. As a result of being further alleviated by the resin, the occurrence of cracks and the like is suppressed, and the long-term reliability of the connection portion is further improved. The stress relaxation effect of the conductive resin is effective not only for thermal stress but also for various stresses, and at least the connection terminals 14 and 1 made of the conductive resin are provided on the terminal electrodes 3 at the four corners.
By providing 5 and 20, a stress relaxation effect can be obtained.

【0053】さらに、接続端子14,15,20が、半
田8,9,16より高融点の金属,合金または導電性樹
脂から成ることより、図10に示すような、Pb37−
Sn63共晶半田から成る半田ボールおよび半田8,9
とした場合と比べ、接続端子14,15,20が接合時
に軟化、溶融しないため、接続部の高さw1(図4),
w2(図8)を十分に保つことができ、熱応力の剪断方
向成分(X方向成分)を減少させることができる。さら
に、実装時の半導体パッケージAと回路基板Bとの平行
度を保つことが容易であり、局所的に強度の弱い接続部
が形成されることもなく、さらに熱応力の剪断方向(X
方向)成分を減少させることができ、クラックの発生等
が抑制される。また、半田8,9の相互拡散が接続端子
14,15,20により妨げられる結果、半田ペースト
中に含まれる不純物成分や空気が拡散して上昇し、半田
8と端子電極3との界面にボイド等の欠陥が生じ、界面
部の機械的強度を低下させるのを防止できる。その結
果、接続部の長期信頼性が向上する。
Further, since the connection terminals 14, 15, 20 are made of a metal, an alloy or a conductive resin having a higher melting point than the solders 8, 9, 16 as shown in FIG.
Solder balls made of Sn63 eutectic solder and solders 8, 9
Since the connection terminals 14, 15, and 20 do not soften or melt at the time of joining, the height w1 of the connection portion (FIG. 4),
w2 (FIG. 8) can be sufficiently maintained, and the shear direction component (X-direction component) of the thermal stress can be reduced. Furthermore, it is easy to maintain the parallelism between the semiconductor package A and the circuit board B at the time of mounting, no locally weak connection portion is formed, and the thermal stress shear direction (X
Direction) component can be reduced, and generation of cracks and the like is suppressed. Further, as a result of the mutual diffusion of the solders 8 and 9 being prevented by the connection terminals 14, 15 and 20, impurity components and air contained in the solder paste are diffused and rise, and voids are formed at the interface between the solder 8 and the terminal electrodes 3. And the like, and the mechanical strength at the interface can be prevented from lowering. As a result, the long-term reliability of the connection is improved.

【0054】さらに、従来、実装密度が向上して高融点
の半田ボール13(図11)ではその直径が実装密度に
影響し、そのため十分な接続部の高さhを確保できない
のに対し、本発明の実装構造では端子電極3の間隔に左
右されずに接続部の必要な高さw1,w2を確保するこ
とができ、高密度配線化、高密度実装化を容易に達成し
得る。
Further, conventionally, the diameter of the solder ball 13 (FIG. 11) having an improved mounting density and a high melting point has an influence on the mounting density, so that a sufficient connection portion height h cannot be ensured. In the mounting structure of the present invention, the required heights w1 and w2 of the connection portion can be secured without being influenced by the interval between the terminal electrodes 3, and high-density wiring and high-density mounting can be easily achieved.

【0055】尚、本発明の接続端子14,15,20
は、必ずしも半導体パッケージA下面全面の端子電極3
に適用する必要はなく、好ましくは最も応力の集中する
少なくとも四隅、望ましくは四隅およびその周辺に適用
することにより、応力緩和効果を発揮し得る。
The connection terminals 14, 15, 20 of the present invention
Is not necessarily the terminal electrode 3 on the entire lower surface of the semiconductor package A.
It is not necessary to apply to the four corners, preferably by applying to at least four corners where the stress is most concentrated, desirably at and around the four corners, to exert a stress relaxation effect.

【0056】本発明は上記の実施形態に限定されるもの
ではなく、本発明の要旨を逸脱しない範囲内で種々の変
更は何等差し支えない。
The present invention is not limited to the above embodiment, and various changes may be made without departing from the scope of the present invention.

【0057】[0057]

【実施例】本発明の実施例を以下に説明する。Embodiments of the present invention will be described below.

【0058】(実施例1)図3の実装構造を以下の工程
〔1〕〜〔4〕により作製した。
Example 1 The mounting structure of FIG. 3 was manufactured by the following steps [1] to [4].

【0059】〔1〕配線基板1用のアルミナを主成分と
する複数のセラミックスグリーンシートに、スルーホー
ル等用の穴を打ち抜き加工で形成し、タングステンを主
成分とする金属ペーストを前記穴部に充填し、スルーホ
ール接続する端子電極3を含むメタライズ配線層2用の
金属ペーストをセラミックスグリーンシート下面にスク
リーン印刷法により形成した。
[1] Holes for through holes and the like are formed in a plurality of ceramic green sheets mainly containing alumina for the wiring board 1 by punching, and a metal paste mainly containing tungsten is formed in the holes. A metal paste for the metallized wiring layer 2 including the filled and through-hole connected terminal electrodes 3 was formed on the lower surface of the ceramic green sheet by screen printing.

【0060】〔2〕焼成後の配線基板1の厚みが1mm
となるように、複数のセラミックスグリーンシートを加
圧積層し積層体を得、この積層体をメタライズ配線層
2、スルーホール、端子電極3とともに同時焼成した。
[2] The thickness of the fired wiring board 1 is 1 mm
Then, a plurality of ceramic green sheets were laminated under pressure to obtain a laminate, and the laminate was simultaneously fired together with the metallized wiring layer 2, through-holes and terminal electrodes 3.

【0061】〔3〕表層の配線導体および端子電極3の
表面にNi−Auめっきを施し、端子電極3上に、各種
形状,材料(表1)から成る図2の接続端子14を、P
b37−Sn63共晶半田から成る半田8により接合し
た。
[3] Ni—Au plating is applied to the surface of the surface wiring conductor and the terminal electrode 3, and the connection terminal 14 of FIG.
The bonding was performed by solder 8 made of b37-Sn63 eutectic solder.

【0062】〔4〕接続端子14の先端部を、プリント
基板の回路基板Bの配線導体10上に、Pb37−Sn
63共晶半田から成る半田9により接合した。
[4] Put the tip of the connection terminal 14 on the wiring conductor 10 of the circuit board B of the printed board by Pb37-Sn
Bonding was performed with solder 9 made of 63 eutectic solder.

【0063】上記半田8,9のリフロー温度は230℃
とし、接続端子14の材質は高融点のPb90−Sn1
0半田、またはAg粉末を含有する熱硬化性エポキシ系
樹脂とした。また、接続端子として、図10のようなP
b37−Sn63共晶半田から成る半田ボールを用い、
接合後の形状が水平方向に偏平となった略楕円形状のも
の(試料NO.1)、図11のようなPb90−Sn1
0半田から成る半田ボールを用い、接合後の形状がボー
ル形状のもの(試料NO.2)を作製し、比較例とし
た。
The reflow temperature of the solders 8 and 9 is 230 ° C.
And the material of the connection terminal 14 is Pb90-Sn1 having a high melting point.
A thermosetting epoxy resin containing no solder or Ag powder was used. As connection terminals, P as shown in FIG.
b37-Sn63 eutectic solder using a solder ball,
Pb90-Sn1 as shown in FIG. 11 having a substantially elliptical shape having a flat shape in the horizontal direction after bonding (sample No. 1).
Using a solder ball made of No. 0 solder, a ball having a ball shape after bonding (sample No. 2) was manufactured as a comparative example.

【0064】次に、これらの実装構造を各々有する半導
体パッケージA,回路基板Bを、大気雰囲気にて−40
℃と125℃の各温度に制御した恒温槽に交互に設置
し、その際双方ともに15分間づつ保持した場合を1サ
イクルとして、最高1000サイクル繰り返した。そし
て、50サイクル毎に回路基板Bの配線導体10と配線
基板1の端子電極3間の電気抵抗を測定し、電気抵抗に
変化が生じるまでのサイクル数を表1に示した。尚、表
1において、*印のものは本発明の範囲外であり、三角
印のものはα,R2/R1の好ましい範囲外のものであ
る。
Next, the semiconductor package A and the circuit board B having these mounting structures are respectively removed by -40 in the air atmosphere.
A maximum of 1,000 cycles were repeated, in which one cycle was a case where the temperature was kept alternately in a thermostat controlled at a temperature of 125 ° C. and a temperature of 125 ° C., and both were held for 15 minutes. Then, the electrical resistance between the wiring conductor 10 of the circuit board B and the terminal electrode 3 of the wiring board 1 was measured every 50 cycles, and Table 1 shows the number of cycles until the electrical resistance changed. In Table 1, those marked with * are outside the scope of the present invention, and those marked with triangles are outside the preferred ranges of α and R2 / R1.

【0065】[0065]

【表1】 [Table 1]

【0066】表1に示すように、比較例の試料NO.1
では半田ボールがリフロー中に溶融し略楕円形状となっ
たため100サイクルで抵抗変化が生じ、接続部の長期
信頼性が確保できず、高融点の半田ボールを用いた試料
NO.2でも250サイクルで電気抵抗が変化し、接続
部の長期信頼性が不十分であったのに対し、本発明品で
ある試料NO.3〜19では、電気抵抗が変化しないサ
イクル数が300以上と優れており、従ってそれらが長
期間にわたり正確かつ強固に接続され、半導体素子4の
大型化による多端子化、高密度実装化に十分対応できる
信頼性の高い実装構造を実現できた。
As shown in Table 1, the sample No. 1
In the case of Sample No. using a high melting point solder ball, the solder ball melted during reflow and became substantially elliptical, causing a change in resistance in 100 cycles, making it impossible to ensure long-term reliability of the connection portion. 2, the electrical resistance changed at 250 cycles, and the long-term reliability of the connection portion was insufficient. In Nos. 3 to 19, the number of cycles in which the electric resistance does not change is excellent at 300 or more. Therefore, they are accurately and firmly connected for a long period of time, and are sufficient for increasing the number of terminals and increasing the density of the semiconductor element 4 by increasing the size of the semiconductor element 4. A highly reliable mounting structure that can be used was realized.

【0067】また、接続端子14の底角αについては、
60〜85°の範囲内で接続端子14による応力緩和効
果が高く、接続部の信頼性が高いものであった。さら
に、接続端子14の最大径R1と最小径R2との比R2
/R1については、0.4〜0.95の範囲で応力集中
の緩和効果が高く、接続部の信頼性が高いものであっ
た。そして、α=60°〜85°,R2/R1=0.4
〜0.95の範囲内である試料NO.5,8〜10,1
3,16〜19では、サイクル数が500以上と特に優
れていた。
The base angle α of the connection terminal 14 is
Within the range of 60 to 85 °, the stress relaxation effect by the connection terminal 14 was high, and the reliability of the connection portion was high. Further, the ratio R2 between the maximum diameter R1 and the minimum diameter R2 of the connection terminal 14 is R2.
Regarding / R1, the effect of reducing stress concentration was high in the range of 0.4 to 0.95, and the reliability of the connection portion was high. Then, α = 60 ° to 85 °, R2 / R1 = 0.4
~ 0.95 sample NO. 5,8-10,1
In Nos. 3, 16 to 19, the number of cycles was particularly excellent at 500 or more.

【0068】(実施例2)図7の実装構造を実施例1と
同様に作製した。但し、端子電極3上に、各種形状,材
料(表2)から成る図6の接続端子15を、Pb37−
Sn63共晶半田から成る半田8により接合した。接続
端子15は、接続端子15a,15bをPb37−Sn
63共晶半田から成る半田16により接合して構成し、
接続端子15の先端部を、プリント基板の回路基板Bの
配線導体10上に、Pb37−Sn63共晶半田から成
る半田9により接合した。半田8,9,16のリフロー
温度は230℃とし、接続端子15の材質は高融点のP
b90−Sn10半田、またはAg粉末を含有する熱硬
化性エポキシ系樹脂とした。
(Example 2) The mounting structure shown in FIG. However, on the terminal electrode 3, the connection terminal 15 of FIG.
Bonding was performed by solder 8 made of Sn63 eutectic solder. The connection terminal 15 connects the connection terminals 15a and 15b to Pb37-Sn.
63 eutectic solder is used for joining,
The tip of the connection terminal 15 was joined to the wiring conductor 10 of the printed circuit board B by the solder 9 made of Pb37-Sn63 eutectic solder. The reflow temperature of the solders 8, 9, and 16 is 230 ° C., and the material of the connection terminals 15 is high melting point P.
b90-Sn10 solder or thermosetting epoxy resin containing Ag powder.

【0069】次に、これらの実装構造を各々有する半導
体パッケージA,回路基板Bを、大気雰囲気にて−40
℃と125℃の各温度に制御した恒温槽に交互に設置
し、その際双方ともに15分間づつ保持した場合を1サ
イクルとして、最高1000サイクル繰り返した。そし
て、50サイクル毎に回路基板Bの配線導体10と配線
基板1の端子電極3間の電気抵抗を測定し、電気抵抗に
変化が生じるまでのサイクル数を表2に示した。尚、表
2において*印のものは本発明の範囲外であり、三角印
のものはβ,R4/R3の好ましい範囲外のものであ
る。
Next, the semiconductor package A and the circuit board B each having these mounting structures are mounted in an air atmosphere at −40.
A maximum of 1,000 cycles were repeated, in which one cycle was a case where the temperature was kept alternately in a thermostat controlled at a temperature of 125 ° C. and a temperature of 125 ° C., and both were held for 15 minutes. Then, the electrical resistance between the wiring conductor 10 of the circuit board B and the terminal electrode 3 of the wiring board 1 was measured every 50 cycles, and Table 2 shows the number of cycles until the electrical resistance changed. In Table 2, those marked with * are outside the range of the present invention, and those marked with triangles are outside the preferred ranges of β and R4 / R3.

【0070】[0070]

【表2】 [Table 2]

【0071】表2に示すように、本発明品である試料N
O.20〜36では、300サイクルまで抵抗変化が見
られず、従ってそれらが長期間にわたり正確かつ強固に
接続され、半導体素子4の大型化による多端子化、高密
度実装化に十分対応できる信頼性の高い実装構造を実現
できた。
As shown in Table 2, the sample N of the present invention
O. In Nos. 20 to 36, no change in resistance was observed up to 300 cycles. Therefore, they were accurately and firmly connected for a long period of time. A high mounting structure was realized.

【0072】また、接続端子15の底角βについては、
45°〜85°の範囲内で接続端子15による応力緩和
効果が高く、接続部の信頼性が高いものであった。さら
に、接続端子15の最大径R3と最小径R4との比R4
/R3については、0.3〜0.95の範囲で応力集中
の緩和効果が高く、接続部の信頼性が高いものであっ
た。そして、β=45°〜85°,R4/R3=0.3
〜0.95の範囲内である試料NO.22,23,25
〜28,39,31,33〜36では、サイクル数が5
00以上と特に優れていた。
The base angle β of the connection terminal 15 is
Within the range of 45 ° to 85 °, the effect of relaxing the stress by the connection terminal 15 was high, and the reliability of the connection portion was high. Furthermore, the ratio R4 between the maximum diameter R3 and the minimum diameter R4 of the connection terminal 15
Regarding / R3, the effect of reducing stress concentration was high in the range of 0.3 to 0.95, and the reliability of the connection portion was high. Then, β = 45 ° to 85 °, R4 / R3 = 0.3
~ 0.95 sample NO. 22, 23, 25
For ~ 28,39,31,33 ~ 36, the number of cycles is 5
It was particularly excellent at 00 or more.

【0073】(実施例3)図12の接続端子20を用い
た実装構造を実施例1と同様に作製した。但し、端子電
極3上に、各種形状,材料(表3)から成る接続端子2
0を、Pb37−Sn63共晶半田から成る半田8によ
り接合した。接続端子20は、その先端部である下面2
3を、プリント基板の回路基板Bの配線導体10上に、
Pb37−Sn63共晶半田から成る半田9により接合
した。半田8,9のリフロー温度は230℃とし、接続
端子20の材質は高融点のPb90−Sn10半田、ま
たはAg粉末を含有する熱硬化性エポキシ系樹脂とし
た。
(Example 3) A mounting structure using the connection terminals 20 shown in FIG. However, the connection terminal 2 made of various shapes and materials (Table 3) is provided on the terminal electrode 3.
No. 0 was joined by solder 8 made of Pb37-Sn63 eutectic solder. The connection terminal 20 has a lower surface 2 which is a tip portion thereof.
3 on the wiring conductor 10 of the printed circuit board B,
Bonding was performed with solder 9 made of Pb37-Sn63 eutectic solder. The reflow temperature of the solders 8 and 9 was 230 ° C., and the material of the connection terminals 20 was a high melting point Pb90-Sn10 solder or a thermosetting epoxy resin containing Ag powder.

【0074】次に、これらの実装構造を各々有する半導
体パッケージA,回路基板Bを、大気雰囲気にて−40
℃と125℃の各温度に制御した恒温槽に交互に設置
し、その際双方ともに15分間づつ保持した場合を1サ
イクルとして、最高1000サイクル繰り返した。そし
て、50サイクル毎に回路基板Bの配線導体10と配線
基板1の端子電極3間の電気抵抗を測定し、電気抵抗に
変化が生じるまでのサイクル数を表3に示した。尚、表
3において*印のものは本発明の範囲外であり、三角印
のものはβ,R4/R3の好ましい範囲外のものであ
る。
Next, the semiconductor package A and the circuit board B having these mounting structures are respectively removed by -40 in the air atmosphere.
A maximum of 1,000 cycles were repeated, in which one cycle was a case where the temperature was kept alternately in a thermostat controlled at a temperature of 125 ° C. and a temperature of 125 ° C., and both were held for 15 minutes. Then, the electric resistance between the wiring conductor 10 of the circuit board B and the terminal electrode 3 of the wiring board 1 was measured every 50 cycles, and Table 3 shows the number of cycles until the electric resistance changed. In Table 3, those marked with * are outside the range of the present invention, and those marked with triangles are outside the preferred ranges of β and R4 / R3.

【0075】[0075]

【表3】 [Table 3]

【0076】表3に示すように、本発明品である試料N
O.37〜53では、300サイクルまで抵抗変化が見
られず、従ってそれらが長期間にわたり正確かつ強固に
接続され、半導体素子4の大型化による多端子化、高密
度実装化に十分対応できる信頼性の高い実装構造を実現
できた。
As shown in Table 3, the sample N of the present invention was used.
O. In Nos. 37 to 53, no change in resistance was observed up to 300 cycles. Therefore, they were accurately and firmly connected for a long period of time. A high mounting structure was realized.

【0077】また、接続端子20の底角βについては、
45°〜85°の範囲内で接続端子20による応力緩和
効果が高く、接続部の信頼性が高いものであった。さら
に、接続端子20の最大径R3と最小径R4との比R4
/R3については、0.3〜0.95の範囲で応力集中
の緩和効果が高く、接続部の信頼性が高いものであっ
た。
The base angle β of the connection terminal 20 is
Within the range of 45 ° to 85 °, the stress relaxation effect by the connection terminal 20 was high, and the reliability of the connection portion was high. Further, the ratio R4 between the maximum diameter R3 and the minimum diameter R4 of the connection terminal 20 is R4.
Regarding / R3, the effect of reducing stress concentration was high in the range of 0.3 to 0.95, and the reliability of the connection portion was high.

【0078】そして、β=45°〜85°,R4/R3
=0.3〜0.95の範囲内である試料NO.39,4
0,42〜45,47,48,50〜53では、サイク
ル数が500以上と特に優れていた。
Then, β = 45 ° to 85 °, R4 / R3
= 0.3 to 0.95. 39,4
In the case of 0, 42 to 45, 47, 48, 50 to 53, the number of cycles was particularly excellent at 500 or more.

【0079】以上、これらの実施例1〜3において、配
線基板1をアルミナセラミックスで構成し、回路基板B
はガラス−エポキシ樹脂の絶縁基板にCu配線導体層等
を形成したものであるが、双方の間で材料を交換するな
ど、構成する材料の種類を変えても同様の効果が得られ
る。また、本発明の実装構造は、BGA型の半導体パッ
ケージのみならず、CSP(チップスケール半導体パッ
ケージ),MCM(マルチチップモジュール)、その他
接続端子を用いて実装する各種モジュール基板等に適用
することができ、同様の効果が得られる。
As described above, in the first to third embodiments, the wiring board 1 is made of alumina ceramic, and the circuit board B
Is obtained by forming a Cu wiring conductor layer or the like on an insulating substrate of glass-epoxy resin, but the same effect can be obtained by changing the type of constituent material, such as by exchanging materials between the two. Further, the mounting structure of the present invention can be applied not only to BGA type semiconductor packages, but also to CSP (chip scale semiconductor packages), MCMs (multi-chip modules), and various module substrates mounted using connection terminals. The same effect can be obtained.

【0080】[0080]

【発明の効果】本発明は、接合基部より先端部が小さい
円錐台形状または多角錐台形状の接続端子を端子電極上
にロウ材を介して接合したことにより、半導体パッケー
ジ等用の配線基板をプリント基板等の他の回路基板上に
実装するにあたり、実装時または使用時に生じる熱応
力、様々な機械的応力、衝撃を緩和低減し、また応力集
中を緩和することにより、ロウ付けされる接続端子の接
合基部の機械的強度を向上させて、接続の長期信頼性が
向上する。
According to the present invention, a wiring substrate for a semiconductor package or the like is formed by joining a connection terminal of a truncated cone shape or a truncated polygonal pyramid shape having a tip portion smaller than a joining base portion on a terminal electrode via a brazing material. When mounted on other circuit boards such as printed circuit boards, connection terminals that are brazed by reducing and reducing thermal stress, various mechanical stresses, and shocks that occur during mounting or use, and by reducing stress concentration And the long-term reliability of the connection is improved.

【0081】また、接続端子がロウ材より高融点の金
属,合金またはロウ材の融点よりも熱分解温度が高い導
電性樹脂から成ることより、接合時に軟化、溶融しない
ため、接続部の高さを十分に保つことができ、その結果
実装時および実装後の半導体パッケージと回路基板との
平行度を保つことが容易であり、局所的に強度の弱い接
続部が形成されることもなく、さらに熱応力の剪断方向
成分を減少させることができ、クラックの発生等が抑制
される。また、ロウ材である半田の相互拡散が接続端子
により妨げられる結果、半田ペースト中に含まれる不純
物成分や空気が拡散して上昇し、半田と端子電極との界
面にボイド等の欠陥が生じ、界面部の機械的強度が低下
するのを防止できる。その結果として、接続部の長期信
頼性が向上する。
Further, since the connection terminal is made of a metal, an alloy or a conductive resin having a higher thermal decomposition temperature than the melting point of the brazing material, it does not soften or melt at the time of joining. , And as a result, it is easy to maintain the parallelism between the semiconductor package and the circuit board at the time of mounting and after mounting, without forming a locally weak connection portion, The shear direction component of the thermal stress can be reduced, and the occurrence of cracks and the like can be suppressed. In addition, as a result of the inter-diffusion of solder, which is a brazing material, being prevented by the connection terminals, impurity components and air contained in the solder paste diffuse and rise, and defects such as voids occur at the interface between the solder and the terminal electrode, A decrease in the mechanical strength of the interface can be prevented. As a result, the long-term reliability of the connection is improved.

【0082】さらに、端子電極の間隔に左右されずに接
続部の必要な高さを確保できるので、高密度配線化、高
密度実装化を容易に達成し得る。
Further, since the required height of the connection portion can be secured without being influenced by the interval between the terminal electrodes, high-density wiring and high-density mounting can be easily achieved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明のBGA型の半導体パッケージを示し、
第一の実施形態による配線基板の断面図である。
FIG. 1 shows a BGA type semiconductor package of the present invention;
FIG. 3 is a cross-sectional view of the wiring board according to the first embodiment.

【図2】図1の配線基板に設けられた接続端子部の拡大
断面図である。
FIG. 2 is an enlarged sectional view of a connection terminal portion provided on the wiring board of FIG. 1;

【図3】図1の半導体パッケージを他の回路基板上に実
装した実装構造の断面図である。
FIG. 3 is a sectional view of a mounting structure in which the semiconductor package of FIG. 1 is mounted on another circuit board.

【図4】図3の実装構造における接続端子部の拡大断面
図である。
FIG. 4 is an enlarged sectional view of a connection terminal part in the mounting structure of FIG. 3;

【図5】本発明のBGA型の半導体パッケージを示し、
第二の実施形態による配線基板の断面図である。
FIG. 5 shows a BGA type semiconductor package of the present invention;
It is sectional drawing of the wiring board by 2nd embodiment.

【図6】図5の配線基板に設けられた接続端子部の拡大
断面図である。
FIG. 6 is an enlarged sectional view of a connection terminal portion provided on the wiring board of FIG. 5;

【図7】図5の半導体パッケージを他の回路基板上に実
装した実装構造の断面図である。
FIG. 7 is a sectional view of a mounting structure in which the semiconductor package of FIG. 5 is mounted on another circuit board.

【図8】図5の実装構造における接続端子部の拡大断面
図である。
FIG. 8 is an enlarged sectional view of a connection terminal portion in the mounting structure of FIG.

【図9】従来のBGA型の半導体パッケージの実装工程
を説明するものであり、(a)は実装前の半導体パッケ
ージの断面図、(b)は配線基板の端子電極に半田ボー
ルを接合させた状態の半導体パッケージの断面図、
(c)は半田ボールを溶融させたときの半導体パッケー
ジおよび他の回路基板の断面図、(d)は半導体パッケ
ージを半田ボールを介して回路基板上に実装させた状態
の半導体パッケージおよび回路基板の断面図である。
9A and 9B are diagrams illustrating a mounting process of a conventional BGA type semiconductor package, in which FIG. 9A is a cross-sectional view of the semiconductor package before mounting, and FIG. 9B is a diagram in which solder balls are bonded to terminal electrodes of a wiring board. Sectional view of the semiconductor package in a state,
(C) is a cross-sectional view of the semiconductor package and another circuit board when the solder balls are melted, and (d) is a state of the semiconductor package and the circuit board in a state where the semiconductor package is mounted on the circuit board via the solder balls. It is sectional drawing.

【図10】従来のBGA型の半導体パッケージの実装に
用いられる半田ボール部の断面図である。
FIG. 10 is a sectional view of a solder ball portion used for mounting a conventional BGA type semiconductor package.

【図11】従来のBGA型の半導体パッケージの実装に
用いられる、高融点の半田ボール部の断面図である。
FIG. 11 is a sectional view of a high melting point solder ball portion used for mounting a conventional BGA type semiconductor package.

【図12】本発明の第三の実施形態による接続端子部の
拡大断面図である。
FIG. 12 is an enlarged sectional view of a connection terminal portion according to a third embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1:配線基板 2:メタライズ配線層 3:端子電極 4:半導体素子 5:ボンディングワイヤ 8,9,16:半田 10:配線導体 11:絶縁基板 14,15,20:接続端子 1: Wiring board 2: Metallized wiring layer 3: Terminal electrode 4: Semiconductor element 5: Bonding wire 8, 9, 16: Solder 10: Wiring conductor 11: Insulating substrate 14, 15, 20: Connection terminal

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】配線導体層が表面および/または内部に形
成された絶縁基板の主面に前記配線導体層と導通する複
数の端子電極が設けられ、接合基部より先端部が小さい
円錐台形状または多角錐台形状の接続端子を前記端子電
極上にロウ材を介して接合したことを特徴とする配線基
板。
A plurality of terminal electrodes are provided on a main surface of an insulating substrate having a wiring conductor layer formed on the surface and / or inside thereof, the terminal electrodes being electrically connected to the wiring conductor layer. A wiring substrate, wherein a connection terminal in the shape of a truncated pyramid is joined to the terminal electrode via a brazing material.
【請求項2】前記円錐台形状または多角錐台形状の接続
端子に代えて、中央部が括れた鼓型の接続端子としたこ
とを特徴とする請求項1記載の配線基板。
2. The wiring board according to claim 1, wherein the connection terminal is a drum-shaped connection terminal with a central portion instead of the truncated conical or polygonal truncated connection terminal.
【請求項3】前記接続端子の接合基部の底角が60°〜
85°、接合基部の最大径R1と先端部の最小径R2と
の比R2/R1が0.4〜0.95であることを特徴と
する請求項1記載の配線基板。
3. The connection terminal according to claim 2, wherein the base angle of the connection base is 60 ° or more.
2. The wiring board according to claim 1, wherein the ratio R2 / R1 of the maximum diameter R1 of the joining base portion and the minimum diameter R2 of the tip end portion is 0.4 to 0.95.
【請求項4】前記接続端子の接合基部の底角が45°〜
85°、接合基部の最大径R3と括れ部の最小径R4と
の比R4/R3が0.3〜0.95であることを特徴と
する請求項2記載の配線基板。
4. A base angle of a connecting base of the connection terminal is 45 ° or more.
The wiring board according to claim 2, wherein the ratio R4 / R3 of the maximum diameter R3 of the joining base portion and the minimum diameter R4 of the constricted portion is 0.3 to 0.95.
【請求項5】前記接続端子が、前記ロウ材よりも高融点
の金属若しくは合金、または前記ロウ材の融点よりも熱
分解温度が高い導電性樹脂から成ることを特徴とする請
求項1〜4のいずれかに記載の配線基板。
5. The connecting terminal is made of a metal or alloy having a higher melting point than the brazing material, or a conductive resin having a higher thermal decomposition temperature than the melting point of the brazing material. The wiring board according to any one of the above.
【請求項6】請求項1〜5のいずれかに記載の配線基板
を、前記接続端子を介して他の回路基板の配線導体上に
ロウ材により接合させたことを特徴とする配線基板の実
装構造。
6. The mounting of the wiring board according to claim 1, wherein the wiring board according to claim 1 is joined to a wiring conductor of another circuit board via the connection terminal with a brazing material. Construction.
JP21278399A 1999-07-27 1999-07-27 Wiring board and mounting structure thereof Pending JP2001044319A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21278399A JP2001044319A (en) 1999-07-27 1999-07-27 Wiring board and mounting structure thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21278399A JP2001044319A (en) 1999-07-27 1999-07-27 Wiring board and mounting structure thereof

Publications (1)

Publication Number Publication Date
JP2001044319A true JP2001044319A (en) 2001-02-16

Family

ID=16628322

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21278399A Pending JP2001044319A (en) 1999-07-27 1999-07-27 Wiring board and mounting structure thereof

Country Status (1)

Country Link
JP (1) JP2001044319A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1244172A2 (en) * 2001-03-22 2002-09-25 Kyocera Corporation Wiring board and wiring board module using the same
JP2003110061A (en) * 2001-09-28 2003-04-11 K-Tech Devices Corp Electronic component for flip-chip packaging and manufacturing method thereof, circuit plate and manufacturing method thereof, and manufacturing method of packaging body
JP2006269972A (en) * 2005-03-25 2006-10-05 Mitsumi Electric Co Ltd Semiconductor device
JP2009238900A (en) * 2008-03-26 2009-10-15 Sanyo Electric Co Ltd Structure of bump electrode, element mounting board and method of manufacturing the same, semiconductor module, and portable equipment
JP2015149459A (en) * 2014-02-10 2015-08-20 新光電気工業株式会社 Semiconductor device and manufacturing method of the same
JP2016188773A (en) * 2015-03-30 2016-11-04 日立金属株式会社 Magnetic sensor and magnetic encoder using the same, lens barrel and camera

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1244172A2 (en) * 2001-03-22 2002-09-25 Kyocera Corporation Wiring board and wiring board module using the same
JP2003110061A (en) * 2001-09-28 2003-04-11 K-Tech Devices Corp Electronic component for flip-chip packaging and manufacturing method thereof, circuit plate and manufacturing method thereof, and manufacturing method of packaging body
JP2006269972A (en) * 2005-03-25 2006-10-05 Mitsumi Electric Co Ltd Semiconductor device
JP2009238900A (en) * 2008-03-26 2009-10-15 Sanyo Electric Co Ltd Structure of bump electrode, element mounting board and method of manufacturing the same, semiconductor module, and portable equipment
JP2015149459A (en) * 2014-02-10 2015-08-20 新光電気工業株式会社 Semiconductor device and manufacturing method of the same
JP2016188773A (en) * 2015-03-30 2016-11-04 日立金属株式会社 Magnetic sensor and magnetic encoder using the same, lens barrel and camera

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