JP5609204B2 - Semiconductor device and electronic equipment - Google Patents

Description

  The present invention relates to a semiconductor device and an electronic apparatus.

Advances in microfabrication technology have led to higher integration of LSIs (Large Scale Integrated Circuits), making it possible to mount LSIs with many functions in one package. As a result, the number of electrode terminals required for one package is further increased. A corresponding mounting technique is flip-chip bonding, which is applied to many electronic devices.
Flip chip connection is a connection method in which solder (solder) bumps are formed on input / output terminals of a semiconductor package, and the solder bumps are joined to wiring pads of a circuit board.

  When the electronic device operates, the semiconductor package and the circuit board are thermally expanded due to heat generated by the electronic device. At this time, the thermal expansion coefficient is different between the semiconductor package and the circuit board, so that a thermal expansion difference is generated, thereby generating a stress at the joint.

  When the electronic device is repeatedly turned on and off, or when the electronic device is repeatedly subjected to a high load and a low load, stress is repeatedly generated at the joint, and eventually a crack called a crack is generated at the solder bump of the joint.

  If cracks spread in the solder bumps, the resistance value of the joint increases, and a correct signal cannot be sent gradually. And if a crack grows to such an extent that electrical continuity between the semiconductor package and the circuit board cannot be obtained, the electronic device may be damaged.

In particular, for a semiconductor device in an electronic device that is required to operate continuously for 24 hours, ensuring the reliability of the joint is a very important issue, and a method for suppressing an increase in resistance due to crack growth is required. .
In order to solve this problem, the following structures are known.

  The structure is such that a cylindrical container filled with a conductive liquid stands vertically on an electrode pad of a semiconductor substrate, a solder paste is printed on the electrode pad, and the solder paste is heated to form an external terminal. It is formed by the method to do. The external terminal is, for example, a solder bump, includes a container therein, and is connected to a contact pad on the circuit board by heating.

  When a crack occurs in the external terminal, and the crack breaks through the container, the conductive liquid in the container fills the crack gap. Thereby, since electrical continuity can be obtained even in the crack gap, an increase in resistance of the external terminal due to the occurrence of the crack is suppressed.

JP 2008-91926 A

  In the connection structure using the above-described container, the arrangement position of the container in the external terminal may be deviated from the crack generation position. On the other hand, although a plurality of containers may be arranged in the external terminals, it takes time to connect the containers and the electrode pads, so that the number of processing steps increases when applied to all solder bumps.

  An object of the present invention is to provide a semiconductor device and an electronic apparatus that can easily prevent electrical disconnection due to a crack generated in a solder bump.

According to one aspect of the present invention, an electrode pad formed on a substrate, a solder bump bonded to the electrode pad, and the electrode pad bonded to each other and a surface of at least a part of the solder bump There is provided a semiconductor device having a bonding portion surface treatment layer that is formed and contains a conductive filler, and becomes liquid at 80 ° C. or higher and soaks into a crack generated in the solder bump .
It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not intended to limit the invention.

According to the present invention, the surface treatment layer containing the conductive filler is formed on the surfaces of the solder bump and the electrode pad that are bonded to each other. The joint surface treatment layer is, for example, solder paste or flux.
For this reason, even if a crack occurs in the solder bump, the surface treatment material containing the conductive filler soaks into the crack, so the crack soaked in the conductive filler becomes a conductive region. Therefore, an increase in the resistance of the solder bump due to the occurrence of a crack is easily suppressed.

1A to 1D are side views (parts 1 to 4) showing a manufacturing process of the semiconductor device according to the embodiment. 1E to 1H are side views (Nos. 5 to 8) showing the manufacturing process of the semiconductor device according to the embodiment. FIG. 2 is a perspective view illustrating a method for manufacturing the surface treatment agent used for solder connection of the semiconductor device according to the embodiment. FIG. 3 is a perspective view showing the arrangement of the semiconductor device according to the embodiment and other components. FIG. 4 is a perspective view illustrating the electronic apparatus according to the embodiment. FIG. 5 is a cross-sectional view showing a solder bump having a crack in the semiconductor device according to the embodiment. FIG. 6 is a side view showing a test state of the semiconductor device according to the embodiment. FIG. 7 is a cross-sectional view showing a crack state of the solder bump generated by the test of the semiconductor device according to the embodiment based on a micrograph. FIG. 8 is a cross-sectional view showing a crack state of a solder bump generated by a test of a semiconductor device according to a comparative example based on a micrograph.

Embodiments of the present invention will be described below with reference to the drawings. In the drawings, similar components are given the same reference numerals.
1A to 1H are side views showing a method of connecting solder bumps and electrode pads in the semiconductor device according to the embodiment.

  A semiconductor package 1 shown in FIG. 1A includes a semiconductor element 3 attached to a first surface of an interposer 2 that is a package substrate. A semiconductor circuit is formed in the semiconductor element 3. The interposer 2 is made of, for example, glass epoxy or glass ceramic. Note that one semiconductor element 3 is attached on the interposer 2 in the figure, but a plurality of semiconductor elements 3 may be attached.

The semiconductor element 3 is mounted face up so that the electrode pad 4 on the upper surface thereof is exposed. That is, the electrode pad 4 on the upper surface of the semiconductor element 3 is connected to the wiring (not shown) on the first surface of the interposer 2 via the conductive wire 5, and the internal wiring (not shown) and via (not shown) of the interposer 2. Via the electrode pad 6 on the second surface of the interposer 2.

The electrode pad 6 on the interposer 2 has a laminated structure selected from, for example, a copper (Cu) layer, a gold (Au) layer, a nickel (Ni) layer, or a chromium (Cr) layer, a Cu layer, Ni It has a laminated structure of layers and tin (Sn) layers.
The semiconductor element 3 may be attached to the electrode pad 6 on the interposer 2 through a solder bump in a face-down manner.

  In order to join the solder bumps to the electrode pads 6 of the semiconductor package 1, first, the metal mask 21 is placed on the second surface of the interposer 2, and the surface treatment material 7 a is placed on the metal mask 21. To move the squeegee 22.

  As shown in FIG. 1B, the first joint surface treatment layer 7 is formed on the surface of the electrode pad 6 by screen printing like that.

  The surface treatment material 7a used as the first joint surface treatment layer 7 is a non-cleaning type solder paste or flux containing a conductive filler. The conductive filler is, for example, carbon fine powder, carbon nanotube, or conductive ceramics such as conductive zirconia, alumina-titanium carbide, silicon carbide, or titanium (Ti), molybdenum (Mo), aluminum (Al), tungsten. It is a metal that does not react with solder as in (W), and has a diameter or length of, for example, several tens to several hundreds of nanometers.

  As shown in FIG. 2, the surface treatment material 7 a is filled with a solder paste or flux liquid 31 in a container 30, and, for example, carbon fine powder as a conductive filler 32 is mixed in the liquid 31. 31 is prepared with sufficient stirring. The conductive filler 32 mixed in the liquid 31 is, for example, about 0.5 gram with respect to 40 ml of the liquid 31.

The flux used as the liquid 21 is formed from a material containing, for example, a resin, an activator, and a solvent. For example, alcohol is used as the solvent, rosin resin is used as the resin, and organic acid is used as the activator. For example, the solder paste further includes a soldering agent, a solder material such as silver (Ag) (for example, 3.0% by mass), Sn (for example, 96.5% by mass), Cu (for example, 0.5% by mass) in addition to the flux. ).
In addition, it is preferable that the surface treatment material 7a contains carbon fine powder, a carbon nanotube, etc. in the ratio of 2.5 grams or less with respect to 100 milliliters of flux.

  Next, as shown in FIG. 1C, solder bumps 8 are placed on the electrode pads 6 via the first joint surface treatment layer 7. The solder bump 8 is, for example, SnAgCu alloy solder having a melting point of about 217 ° C., and has a diameter of about 0.76 mm. Also, the solder bumps 8 are aligned and placed on the electrode pads 6 using a mounter.

Subsequently, as shown in FIG. 1D, the semiconductor package 1 is placed in a reflow furnace, where it is heated and melted at, for example, about 237 ° C., and the solder bumps 8 are melted and then cooled to room temperature.
When the solder bump 8 is heated, the first joint surface treatment layer 7 protrudes around the solder bump 8 while removing oxides and contaminants on the surfaces of the electrode pad 6 and the solder bump 8. Thereby, the solder bump 8 is joined to the electrode pad 6.

The first joint surface treatment layer 7 is mixed with oxides and contaminants at the time of solder joining, and increases in viscosity after cooling. In addition, the first joint surface treatment layer 7 clogged with the conductive filler 32 is applied to at least a part of the surfaces of the electrode pads 6 and the solder bumps 8 after the solder bumps 8 are cooled.

Next, as shown in FIG. 1E, a solder resist is applied on the second surface of the interposer 2 as the insulating coating layer 9. In this case, the solder ball 8 and the first joint surface treatment layer 7 are exposed from the insulating coating layer 9, and the periphery of the solder ball 8 and the first joint surface treatment layer 7 is surrounded by the insulating coating layer 9. .
Thus, a ball grid array (BGA) solder joint package substrate is formed.

  Here, as shown in FIG. 1F, a circuit board 11 is prepared, the first surface of the circuit board 11 and the second surface of the semiconductor package 1 are opposed to each other, and the wiring formed on the first surface of the circuit board 11 The solder bumps 8 on the interposer 2 are brought into contact with the pads 12.

  On the wiring pad 12 on the first surface of the circuit board 11, a second bonding portion surface treatment layer 13 is formed by screen printing. Note that an insulating coating layer 14 having an opening for covering the wiring (not shown) formed on the first surface and exposing the wiring pad 12 is formed on the first surface of the circuit board 11, for example, a resin layer such as a resist. Is formed.

  The wiring pad 12 has, for example, a Cu layer, an Au layer, a Ni layer, or a laminated structure selected from them, or a laminated structure of a Cr layer, a Cu layer, a Ni layer, and a Sn layer.

  The surface treatment material used as the second joint surface treatment layer 13 is a non-cleaning type solder paste or flux containing a conductive filler, like the first joint surface treatment layer 7. The conductive filler is carbon fine powder, carbon nanotubes, conductive ceramics such as conductive zirconia, alumina-titanium carbide, silicon carbide, or a metal that does not react with solder such as Ti, Mo, Al, and W. For example, it has a diameter or length of several tens nm to several hundreds nm.

Subsequently, the semiconductor package 1 and the circuit board 11 are put into a reflow furnace, for example, the temperature is raised from room temperature to 237 ° C. to melt the solder bumps 8 and then returned to room temperature. As a result, as shown in FIG. 1G, the solder bumps 8 are bonded to the wiring pads 12 on the circuit board 11, and the second bonding portion surface treatment layer 13 on the circuit board 11 is bonded to the solder bumps 8 and the wiring pads 12. Protrudes from the surface of the joint.

  The second bonding portion surface treatment layer 13 is mixed with oxides and contaminants at the time of solder bonding, increases in viscosity due to cooling, and is applied to at least a part of the surfaces of the electrode pads 6 and the solder bumps 8. . Further, the first bonding portion surface treatment layer 7 on the semiconductor package 1 side becomes a liquid state upon heating and further spreads on the surface of the solder bump 12.

Next, as shown in FIG. 1H, an underfill resin 15 is filled in the gap between the interposer 2 and the circuit board 11. The underfill resin 15 contains a solvent at the time of injection, and then the solvent volatilizes and is semi-cured. However, when the second joint surface treatment layer 13 becomes liquid by heat, the flow on the surface of the solder ball 8 is caused. I do not disturb.
A device in which the semiconductor package 1 and the circuit board 11 are connected via the solder bumps 8 may be included in the concept of the semiconductor device. Further, the wiring pad 12 may be included in the concept of the electrode pad.

As shown in FIG. 3, an electronic component 16 such as a semiconductor memory is further attached to the circuit board 11 to which the semiconductor package 1 is attached, and these are used as a system board. As shown in FIG. 4, the system board is attached to a case 42 of an electronic device 40 to which a power source 41 and the like are attached.

  In the system boat as described above, the operation of the electronic device 40 and the semiconductor element 3 generates heat inside the electronic device 40, and the internal temperature rises or falls. When such a change in temperature is repeated, the circuit board 11 and the semiconductor package 1 are repeatedly warped and returned due to the difference in thermal expansion coefficient between the circuit board 11 and the semiconductor package 1, and stress is applied to the solder bumps 8. In addition, cracks may eventually occur in the solder bumps 8.

  When the temperature is high in the electronic device 40, the temperature is 80 ° C. or higher. Therefore, the first and second joint surface treatment layers 7 and 13 attached to the surface of the solder bump 8 become liquid due to the temperature, as shown in FIG. Infiltrate into the crack 8a by capillary action. Since the first and second joint surface treatment layers 7 and 13 include a conductive filler, electrical connection is maintained in the crack 8a by the conductive filler.

Therefore, even if a crack 8a occurs in the solder bump 8, it is prevented that the resistance is increased by the conductive filler in the first and second joint surface treatment layers 7 and 13, and the operation of the electronic device 40 is kept normal. Be drunk. Further, since the structure of the solder bumps 8 is not changed and no new process is added to the joining of the solder bumps 8, a decrease in throughput is prevented.
Even if the first and second joint surface treatment layers 7 and 13 are melted by heat and the viscosity is lowered, the insulating coating layer 9 and the underfill resin 15 prevent the outflow to the outside.

After the solder bumps 8 on the electrode pads 6 of the semiconductor package 1 were bonded to the wiring pads 12 of the circuit board 11 by the above method, a fatigue test was performed.
The circuit board 11 subjected to the fatigue test is formed of glass epoxy having a length of 110 mm, a width of 110 mm, and a thickness of 1.5 mm, and the interposer 2 of the semiconductor package 1 has a length of 45 mm, a width of 45 mm, and a thickness. Has a size of 1.5 mm. The electrode pad 6 and the wiring pad 12 have a diameter of 0.6 mm and a pitch of 1.27 mm. The solder bump 8 is a SnAgCu alloy having a diameter of 0.76 mm. In this case, the Sn, Ag, and Cu contents are Sn 6.5% by mass, Ag 3.0% by mass, and Cu 0.5% by mass.

  Then, a mechanical fatigue test was performed with the bending apparatus 41 shown in FIG. 6 in a state where the electrode pads 6 of the semiconductor package 1 and the wiring pads 12 of the circuit board 11 were connected by the solder bumps 8.

  A bending apparatus 41 shown in FIG. 6 includes a pair of support bodies 42 that support regions near both sides of the first surface of the circuit board 11, and a pusher 43 that applies vertical vibration to the center region of the second surface of the circuit board 11. have. The distance α between the pair of supports 42 is set to about 90 mm.

  On the second surface of the circuit board 11 used for the test, a first terminal 12b that is electrically connected to the wiring pad 12 through the through hole 12a inside the circuit board 11 is formed. On the first surface of the interposer 2 of the semiconductor package 1, a second terminal 6 b that is electrically connected to the electrode pad 6 through the through hole 5 a inside the interposer 2 is formed.

  Then, a positive terminal and a negative terminal of the direct current generator 44 are connected to the first terminal 12b and the second terminal 6b, respectively, and a pair of test terminals of the resistance value monitor 45 are connected to the first terminal 12b and the second terminal 6b. Connected.

  In such a state, the pusher 43 is vibrated up and down, and the vibration is transmitted to the circuit board 11. In this case, the amplitude of the pusher 43 was set to 1.5 mm, the vibration frequency was set to 0.5 Hz, and the circuit board 11, the semiconductor package 1, and the solder bumps 8 were heated to 80 ° C.

  In such a state, a current is passed from the direct current generator 44 to the solder bump 8 through the first terminal 13b and the second terminal 6b, and the resistance value between the first terminal 13b and the second terminal 6b is measured by the resistance value monitor 45. As a result of measurement, the measured resistance value changed.

Then, the ratio ΔR / R of the resistance increase value ΔR to the initial resistance value R was obtained, and the vibration cycle of the pusher 43 until ΔR / R became 1% was measured. The results shown in Table 1 were obtained. Table 1 shows the results of three fatigue tests.
As the first and second joint surface treatment layers 7 and 13, carbon fine powder is mixed in a proportion of 0.5 gram in 40 milliliters of solder paste, and Sn, Ag, and Cu are the same as the solder bumps 8. Materials included in proportions were used.

On the other hand, the electrode pad 6 and the wiring pad 12 are joined by the solder bump 8 using a solder paste that does not mix the conductive filler in place of the first and second joint surface treatment layers 7 and 13, and the same conditions are used. When the fatigue test was conducted, the results shown in Table 2 were obtained.

  Comparing Table 1 and Table 2, it can be seen that the average life of the present embodiment is 100 cycles or more longer than that of the comparative example. This indicates that resistance increase is less likely to occur due to the penetration of the conductive flux into the crack 8a generated in the solder bump 8.

About the sample of this embodiment, when the circumference | surroundings of the crack 8a among the solder bumps 8 were cut | disconnected and the cut surface was observed with the microscope, it was in the state as shown in FIG.
In FIG. 7, it can be seen that the solder bumps 8 are surrounded by the black joint surface treatment layer 7. Further, as shown by hatching, conductive flux soaked into the crack region of the solder bump 8.

  On the other hand, when the periphery of the crack 8a was cut out of the solder bumps 8 in which cracks occurred in the sample according to the comparative example, and the cut surface was observed with a microscope, the state was as shown in FIG.

In FIG. 8, the solder bumps 8 are surrounded by the joint surface treatment layer 35, and the joint surface treatment material is infiltrated into the crack generation region. However, since the joint surface treatment layer 35 does not contain a conductive flux, it itself has a high resistance and does not contribute to a reduction in resistance of the crack region.
In FIG. 7, reference numeral 10 indicates a wiring connected to the electrode pad 6, and in FIG. 8, a reference numeral 19 indicates a wiring connected to the electrode pad 6.

  In the above-described embodiment, a recess may be formed around the electrode pad 6 and the wiring pad 12, and the recess may be used as a reservoir for the joint surface treatment layer. For example, in FIG. 1H, the space between the wiring pad 12 and the surrounding insulating coating layer 14 is a reservoir of the second bonding portion surface treatment layer 13.

  Further, as the solder paste or flux for solder bonding used when the semiconductor element 3 is connected to the interposer 2 face down, a joint surface treatment material containing the above conductive filler may be used. In this case, the semiconductor element 3 is a substrate as described above.

  In the above-described embodiment, the joint surface treatment layer containing the conductive filler is applied to both the electrode pad 6 on the semiconductor package 1 and the wiring pad 12 on the circuit board 11. Also good.

  All examples and conditional expressions given here are intended to help the reader understand the inventions and concepts that have contributed to the promotion of technology, such examples and It should be construed without being limited to the conditions, and the organization of such examples in the specification is not related to showing the superiority or inferiority of the present invention. Although embodiments of the present invention have been described in detail, it should be understood that various changes, substitutions and variations can be made thereto without departing from the spirit and scope of the present invention.

DESCRIPTION OF SYMBOLS 1 Semiconductor package 2 Interposer 3 Semiconductor element 6 Electrode pad 7 Junction surface treatment layer 8 Solder bump 9 Insulating coating layer 11 Circuit board 12 Wiring pad 13 Junction surface treatment layer 14 Insulation coating layer 15 Underfill resin layer 31 Liquid 32 Conductive filler 40 Electronic equipment

Claims (5)

An electrode pad formed on the substrate;
Solder bumps bonded to the electrode pads;
Surface of the joint formed on at least a part of the surfaces of the electrode pad and the solder bump bonded to each other, containing a conductive filler, and becoming liquid at 80 ° C. or higher and soaking into a crack generated in the solder bump Processing layer,
A semiconductor device.   The semiconductor device according to claim 1, wherein the conductive filler includes at least one of a metal that does not react with solder, carbon fine powder, carbon nanotube, and conductive ceramics.   The semiconductor device according to claim 1, wherein the joint surface treatment layer is either a flux or a solder paste, and includes a resin, an activator, and a solvent.   4. The semiconductor device according to claim 1, wherein at least a part of the solder bump and the joint surface treatment layer are surrounded by an insulating coating layer. 5. A semiconductor device according to any one of claims 1 to 4;
A housing for mounting the semiconductor device;
Electronic equipment having

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