JP2000036657A - Electronic device and its manufacture - Google Patents
Electronic device and its manufactureInfo
- Publication number
- JP2000036657A JP2000036657A JP10205615A JP20561598A JP2000036657A JP 2000036657 A JP2000036657 A JP 2000036657A JP 10205615 A JP10205615 A JP 10205615A JP 20561598 A JP20561598 A JP 20561598A JP 2000036657 A JP2000036657 A JP 2000036657A
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- Prior art keywords
- solder alloy
- substrate
- main surface
- electronic device
- weight
- Prior art date
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Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、ＬＳＩ素子および
電子部品を、回路基板に表面実装する方法に関する。The present invention relates to a method for surface mounting an LSI element and an electronic component on a circuit board.
【０００２】[0002]
【従来の技術】複数個のＬＳＩチップを一つのモジュー
ルに搭載して、高速化、小型化、高機能化を図るＭＣＭ
は、大型コンピュータ、人工衛星、軍事用電子機器など
のハイエンド機器から、最近では携帯電話、ノートパソ
コンなどの民生用電子機器まで応用範囲が広く、実装技
術の中枢の一つとなっている。ＭＣＭとはMulti Chip M
odule の略である。最近のＭＣＭの開発においては、機
能の増強に伴うサイズの増大、および入出力ピン（以下
Ｉ／Ｏピンという）の数の増大が生じており、これに伴
いＩ／Ｏピンのピッチを減少させる必要が生じている。2. Description of the Related Art An MCM in which a plurality of LSI chips are mounted on one module to achieve higher speed, smaller size, and higher function.
Has a wide range of applications from high-end devices such as large computers, artificial satellites, and military electronic devices to consumer electronic devices such as mobile phones and notebook personal computers, and has become one of the centers of mounting technology. MCM is Multi Chip M
odule. In the recent development of the MCM, an increase in the size and an increase in the number of input / output pins (hereinafter, referred to as I / O pins) have been caused by the enhancement of the functions, and the pitch of the I / O pins has been reduced accordingly. There is a need.
【０００３】図１（Ａ）、（Ｂ）は複数のチップ（図示
せず）を担持したＭＣＭ基板１を基板６上に実装した従
来の構造を示す。ただし、図１（Ｂ）は図１（Ａ）の一
部を拡大して示す。基板１は典型的には窒化アルミニウ
ム（ＡｌＮ）よりなり、チップをフェースダウン状態で
担持する。基板６は配線基板であり、例としてコンピュ
ータ用のマザーボードとして使用される。材質はガラス
ポリイミドである場合が多い。両基板は接続ピン４によ
り電気的に接続されるが、接続ピン４はＭＣＭ基板１に
対しては、Ａｕ−Ｓｎ系のはんだ合金３により基板１下
面上の配線電極２において、また基板６に対してはＳｎ
−Ｐｂ系のはんだ合金５により、基板６上の対応する電
極６Ａにおいて、接合されている。FIGS. 1A and 1B show a conventional structure in which an MCM substrate 1 carrying a plurality of chips (not shown) is mounted on a substrate 6. FIG. Note that FIG. 1B illustrates a part of FIG. 1A in an enlarged manner. The substrate 1 is typically made of aluminum nitride (AlN) and carries the chip in a face-down state. The board 6 is a wiring board, and is used as, for example, a motherboard for a computer. The material is often glass polyimide. The two substrates are electrically connected by connection pins 4. The connection pins 4 are connected to the MCM substrate 1 by the Au—Sn based solder alloy 3 at the wiring electrodes 2 on the lower surface of the substrate 1 and to the substrate 6. For Sn
The corresponding electrodes 6A on the substrate 6 are joined by the Pb-based solder alloy 5.
【０００４】[0004]
【発明が解決しようとする課題】このようなＭＣＭ基板
を別の基板上に保持した電子装置では、Ｉ／Ｏピンの最
大間隔が５０ｍｍ以上、ピンピッチ（格子パターン）
１．３ｍｍ以下の、例えば、大型コンピュータ用ＭＣＭ
の場合、ＭＣＭ基板（窒化アルミ）とマザーボード基板
（ガラスポリイミド）の熱膨張率差による位置ずれ、あ
るいはＭＣＭ基板のそりが深刻な問題となる。現状のＳ
ｎ−３７Ｐｂ系のはんだ合金を使用した場合、はんだ合
金をリフローさせるのに約１８０℃の温度まで加熱する
必要がある。しかし、このように高い温度まで加熱する
と、前記熱膨張率差による位置ずれが顕著となり、接合
がほとんど不可能になる。またはんだ合金の凝固後に接
合部のはんだ合金に対する永続的な応力歪みが発生し、
クリープ特性に問題のあるＳｎ−３７Ｐｂでは熱疲労特
性などの接合信頼性に問題が生じる。In an electronic device in which such an MCM substrate is held on another substrate, the maximum interval between I / O pins is 50 mm or more, and the pin pitch (lattice pattern)
1.3 mm or less, for example, MCM for large computers
In the case of (1), displacement due to a difference in thermal expansion coefficient between the MCM substrate (aluminum nitride) and the motherboard substrate (glass polyimide), or warpage of the MCM substrate becomes a serious problem. Current S
When an n-37Pb-based solder alloy is used, it is necessary to heat the solder alloy to a temperature of about 180 ° C. in order to reflow the solder alloy. However, when heating is performed to such a high temperature, the displacement due to the difference in the thermal expansion coefficient becomes remarkable, and the joining becomes almost impossible. Also, after solidification of the solder alloy, permanent stress strain occurs on the solder alloy at the joint,
Sn-37Pb, which has a problem in creep characteristics, has a problem in bonding reliability such as thermal fatigue characteristics.
【０００５】上記問題が生じる例として、Ｉ／Ｏピン４
の最大間隔ｌ、ピンピッチｐのＭＣＭ基板１を熱膨張率
差がΔεのマザーボード基板に図１のようなピングリッ
ドアレイ方式によって実装する場合、基板間の熱膨張率
差によるＩ／Ｏピンの位置ずれＤは、以下の式によって
算出される。 Ｄ＝Δε・（ｌ／２）・（Ｔsol ーＴr ）（＜ｐ／４） ここに、Ｔsol は接合部におけるはんだ合金の固相線温
度を、Ｔr は室温を表す。 例として、マザーボー
ド基板２との熱膨張率差が12×10-6、Ｉ／Ｏピンの最大
間隔が50mm、ピンピッチ1.3mm のＭＣＭ基板１を図１
（Ａ），（Ｂ）のようなピングリッドアレイ方式によっ
て接合する場合において、Ｓｎ−３７Ｐｂはんだ合金
（固相線温度183 ℃）を用いて接合した場合の、最大間
隔離れたＩ／Ｏピンのはんだ凝固後の位置ずれＤspは、 Ｄsp＝12×10-6・(25 ×104)・(183 - 25) ＝474 μm となり、ピンピッチ1300μm に対して、位置ずれが問題
となる目安である、ピンピッチの１/ ３に相当する値を
超えることになる。このずれ分がそのままはんだ合金接
合部に加わる応力となり、接合の信頼性を低下させる原
因となる。As an example where the above problem occurs, the I / O pin 4
When the MCM substrate 1 having the maximum spacing l and the pin pitch p is mounted on a motherboard substrate having a thermal expansion coefficient difference of Δε by a pin grid array method as shown in FIG. 1, the positions of the I / O pins due to the thermal expansion coefficient difference between the substrates The shift D is calculated by the following equation. D = Δε · (l / 2) · (T sol −T r ) (<p / 4) Here, T sol represents the solidus temperature of the solder alloy at the joint, and Tr represents room temperature. As an example, an MCM substrate 1 having a difference in thermal expansion coefficient from the motherboard substrate 2 of 12 × 10 −6 , a maximum interval between I / O pins of 50 mm, and a pin pitch of 1.3 mm is shown in FIG.
In the case of joining by the pin grid array method as in (A) and (B), when the joining is performed by using the Sn-37Pb solder alloy (solidus temperature: 183 ° C.), the I / O pins which are separated from each other by the maximum distance are arranged. positional deviation Dsp after solder solidification, D sp = 12 × 10 -6 · (25 × 10 4) · (183 - 25) = 474 μm , and the relative pin pitch 1300 [mu] m, is a measure misalignment is problematic , One-third of the pin pitch. This shift directly becomes a stress applied to the solder alloy joint, which causes a reduction in joint reliability.
【０００６】[0006]
【課題を解決するための手段】上記課題を解決するため
に本発明では、次に述べる各手段を講じたことを特徴と
するものである。請求項１記載の発明では、相互に対向
する第１および第２の主面を有する第１の基板と、相互
に対向する第３および第４の主面を有し、前記第１の基
板の近傍に、前記第３の主面が前記第１の基板の前記第
２主面に対面するように配設された第２の基板と、前記
第１の主面上に担持されたチップと、前記第２の主面上
に担持された、複数の導体ピンと、前記第３の主面上に
形成された導体パターンと、前記第３の主面上におい
て、前記複数の導体ピンの各々を、前記導体パターンに
電気的および機械的に接合するはんだ合金とよりなる電
子装置において、前記はんだ合金は、約１５０℃以下の
固相線温度を有することを特徴とするものである。Means for Solving the Problems In order to solve the above problems, the present invention is characterized by taking the following means. According to the first aspect of the present invention, the first substrate has first and second main surfaces opposed to each other, and third and fourth main surfaces opposed to each other. A second substrate disposed in the vicinity such that the third main surface faces the second main surface of the first substrate; and a chip carried on the first main surface; A plurality of conductor pins carried on the second main surface, a conductor pattern formed on the third main surface, and each of the plurality of conductor pins on the third main surface, An electronic device comprising a solder alloy electrically and mechanically joined to the conductive pattern, wherein the solder alloy has a solidus temperature of about 150 ° C. or less.
【０００７】また、請求項２記載の発明では、前記はん
だ合金は、Ｓｎを約４２〜５９重量％、Ｂｉを約４１〜
５８重量％含むはんだ合金よりなることを特徴とするも
のである。また、請求項３記載の発明では、前記はんだ
合金は、約１３６℃の固相線温度を有することを特徴と
するものである。According to the second aspect of the present invention, the solder alloy contains about 42 to 59% by weight of Sn and about 41 to 41% by weight of Bi.
It is made of a solder alloy containing 58% by weight. According to a third aspect of the present invention, the solder alloy has a solidus temperature of about 136 ° C.
【０００８】また、請求項４記載の発明では、前記はん
だ合金は、室温と前記はんだ合金の固相線温度との間の
温度差に対応して前記導体ピンに生じる熱歪みが、前記
導体ピンのピッチの約１/ ３以下になるように、組成を
設定されていることを特徴とするものである。また、請
求項５記載の発明では、前記はんだ合金は、Ｓｎを約４
２重量％、Ｂｉを約５９重量％、Ａｇを約１重量％含む
ことを特徴とするものである。In the invention according to claim 4, the solder alloy has a thermal strain generated in the conductor pin corresponding to a temperature difference between room temperature and a solidus temperature of the solder alloy. The composition is set so that the pitch is about 1/3 or less of the pitch of the above. Further, in the invention described in claim 5, the solder alloy contains Sn of about 4%.
It contains 2% by weight, about 59% by weight of Bi, and about 1% by weight of Ag.
【０００９】次に、請求項６記載の発明では、前記導体
ピンは、前記第２の主面上に、約１．３ｍｍ以下のピッ
チで形成されていることを特徴とするものである。ま
た、請求項７記載の発明では、前記第１の基板はＡｌＮ
よりなることを特徴とするものである。また、請求項８
記載の発明では、前記第２の基板はガラスポリイミドよ
りなることを特徴とするものである。Next, the invention according to claim 6 is characterized in that the conductor pins are formed on the second main surface at a pitch of about 1.3 mm or less. In the invention described in claim 7, the first substrate is made of AlN.
It is characterized by comprising. Claim 8
In the above invention, the second substrate is made of glass polyimide.
【００１０】また、請求項９記載の発明では、前記導体
ピンは、前記第１の基板の前記第２の主面上、一辺が約
５０ｍｍ以上の領域に形成されていることを特徴とする
ものである。また、請求項１０記載の発明では、相互に
対向する第１および第２の主面を有し、前記第１の主面
上にチップを担持し、前記第２の主面上に複数の導体ピ
ンを担持する第１の基板と、相互に対向する第３および
第４の主面を有し、前記第１の基板の近傍に、前記第３
の主面が、前記第１の基板の前記第２主面に対面するよ
うに配設され、前記第３の主面上には導体パターンが担
持され、前記第２の主面上の導体ピンが前記第３の主面
上の導体パターンに電気的および機械的に接続された電
子装置の製造方法において、前記第１および第２の基板
を、前記第２の主面上の導体ピンの各々が、前記第３の
主面上の対応する導体パターンにコンタクトするように
配設する工程と、前記第３の主面上において、前記複数
の導体ピンの各々を、対応する前記導体パターンに、は
んだ合金をリフローすることにより接続するリフロー工
程とを含み、前記リフロー工程は、前記はんだ合金とし
て、１８３℃未満の固相線温度を有するはんだ合金を用
い、前記はんだ合金をリフローする際に、実質的に前記
固相線温度に等しい温度まで加熱する工程を含むことを
特徴とするものである。[0010] In the invention according to claim 9, the conductor pin is formed in an area of one side of about 50 mm or more on the second main surface of the first substrate. It is. According to the tenth aspect of the present invention, there are provided first and second main surfaces facing each other, a chip is carried on the first main surface, and a plurality of conductors are provided on the second main surface. A first substrate carrying pins; and third and fourth main surfaces facing each other, wherein the third substrate is provided near the first substrate.
Is disposed so as to face the second main surface of the first substrate, a conductor pattern is carried on the third main surface, and a conductor pin on the second main surface is provided. Is a method of manufacturing an electronic device electrically and mechanically connected to a conductor pattern on the third main surface, wherein the first and second substrates are each connected to a conductor pin on the second main surface. Arranging each of the plurality of conductor pins on the third main surface so as to contact the corresponding conductor pattern on the third main surface, A reflow step of connecting by reflowing the solder alloy, wherein the reflow step uses a solder alloy having a solidus temperature of less than 183 ° C. as the solder alloy, and substantially reflows the solder alloy. To the solidus temperature It is characterized in that it comprises the step of heating to a temperature.
【００１１】また、請求項１１記載の発明では、前記は
んだ合金は、Ｓｎを約４２〜５９重量％、Ｂｉを約４１
〜５８重量％含むはんだ合金よりなることを特徴とする
ものである。また、請求項１２記載の発明では、前記固
相線温度として約１５０℃以下のはんだ合金を使用する
工程を含むことを特徴とするものである。According to the eleventh aspect of the present invention, the solder alloy contains about 42 to 59% by weight of Sn and about 41% by weight of Bi.
It is characterized by being made of a solder alloy containing up to 58% by weight. The twelfth aspect of the invention is characterized by including a step of using a solder alloy having a solidus temperature of about 150 ° C. or less.
【００１２】また、請求項１３記載の発明では、前記は
んだ合金は、約１３６℃の固相線温度を有し、前記リフ
ロー工程は、前記はんだ合金を約１３６℃まで加熱する
ことを特徴とするものである。また、請求項１４記載の
発明では、前記はんだ合金は、室温と前記はんだ合金の
固相線温度との間の温度差に対応して前記導体ピンに生
じる熱歪みが、前記導体ピンのピンのピッチの約１/ ３
以下になるように、組成が設定されていることを特徴と
するものである。According to a thirteenth aspect of the present invention, the solder alloy has a solidus temperature of about 136 ° C., and the reflow step heats the solder alloy to about 136 ° C. Things. Further, in the invention according to claim 14, the solder alloy has a thermal distortion generated in the conductor pin corresponding to a temperature difference between room temperature and a solidus temperature of the solder alloy, About 1/3 of pitch
It is characterized in that the composition is set as follows.
【００１３】また、請求項１５記載の発明では、前記は
んだ合金は、Ｓｎを約４２重量％、Ｂｉを約５９重量
％、Ａｇを約１重量％含むことを特徴とするものであ
る。[ 作用]以下本発明の作用を説明する。本発明で
は、図１（Ａ），（Ｂ）の構成において、ＭＣＭ基板１
を接続ピン４のピングリッドアレイにより基板６に接続
する場合、接続ピン４を基板６上の導体パターンに接続
するはんだ合金５として、固相線温度が典型的には約１
５０℃以下の組成のものを使う。この場合、配線基板６
との熱膨張率差が１２×１０-6、Ｉ／Ｏピン４の最大間
隔が５０ｍｍ、ピンピッチを１．３ｍｍとすると、固相
線温度１５０℃のはんだ合金で行った場合の、はんだ合
金凝固後の位置ずれＤlsは、先の式によれば、 Ｄls＝12×10-6 ・(25 ×104)・(150 - 25) ＝375 μm となり、ずれをピンピッチ1300μm に対して１/ ３以下
に抑えることができる。このように、接合に使用するは
んだ合金の固相線温度を約１５０℃以下に下げることに
より、はんだ合金が完全に凝固してから室温に温度雰囲
気が低下するまでの温度幅を狭めることができる。その
結果、各基板の熱収縮量の差により接合部の凝固したは
んだ合金に加わる応力歪みを小さくすることができる。
また、本発明では、ヤング率が高くて硬いＳｎ，Ｂｉを
主成分とするはんだ合金を用いることにより、接合部に
生じる応力歪みによるはんだ合金の変形を抑えることが
できる。以上の効果により接合部の信頼性を向上させる
ことができる。[0013] According to the present invention, the solder alloy contains about 42% by weight of Sn, about 59% by weight of Bi, and about 1% by weight of Ag. [Operation] The operation of the present invention will be described below. According to the present invention, in the configuration shown in FIGS.
Is connected to the substrate 6 by the pin grid array of the connection pins 4, the solidus temperature of the solder alloy 5 for connecting the connection pins 4 to the conductor pattern on the substrate 6 is typically about 1
Use a composition with a temperature of 50 ° C or less. In this case, the wiring board 6
Thermal expansion coefficient difference 12 × 10 -6 and, when the maximum distance between the I / O pins 4 is 50 mm, the a 1.3mm pin pitch, of which the operation was performed solidus temperature 0.99 ° C. of the solder alloy, solder alloy solidification According to the above equation, the subsequent displacement D ls is D ls = 12 × 10 −6 (25 × 10 4 ) · (150 −25) = 375 μm, and the displacement is 1/100 with respect to the pin pitch of 1300 μm. 3 or less. As described above, by lowering the solidus temperature of the solder alloy used for joining to about 150 ° C. or lower, the temperature range from the time when the solder alloy completely solidifies to the time when the temperature atmosphere decreases to room temperature can be narrowed. . As a result, the stress strain applied to the solidified solder alloy at the joint due to the difference in the amount of thermal shrinkage of each substrate can be reduced.
Further, in the present invention, by using a solder alloy having Sn and Bi as its main components, which has a high Young's modulus and is hard, it is possible to suppress the deformation of the solder alloy due to stress strain generated at the joint. With the above effects, the reliability of the joint can be improved.
【００１４】[0014]
【発明の実施の形態】図２（Ａ），（Ｂ）は本発明の実
施例を示す構成図である。図中第一の基板１1 （モジュ
ール基板）は、窒化アルミニウムを材質とするＭＣＭ基
板であり、この形状として５０ｍｍ四方、熱膨張率が５
×１０-6、Ｉ／Ｏピン１４の最大間隔が５０ｍｍ、ピン
ピッチが１．３ｍｍのものである。これに従来方法であ
るＡｕ−Ｓｎはんだ合金１３を用いて接合された接続ピ
ンであるＩ／Ｏピン１４が、ガラスポリイミドを材質と
するマザーボード（第二の基板（配線基板））１６とを
接合する上で本発明に係るはんだ合金２３であるＳｎ５
７Ｂｉ−１Ａｇ（数値は重量比を表す）が用いられてい
る例である。Ｉ／Ｏピン１４は、信号の入出力のための
もの以外にも、例えば接地ピンや電源ピン、あるいはク
ロックピン等をも含む。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 2A and 2B are block diagrams showing an embodiment of the present invention. In the figure, a first substrate 11 (module substrate) is an MCM substrate made of aluminum nitride and has a shape of 50 mm square and a coefficient of thermal expansion of 5 mm.
× 10 -6 , the maximum interval between the I / O pins 14 is 50 mm, and the pin pitch is 1.3 mm. An I / O pin 14 as a connection pin joined by using a conventional Au-Sn solder alloy 13 is joined to a motherboard (second board (wiring board)) 16 made of glass polyimide. In this case, the solder alloy 23 according to the present invention, Sn5
This is an example in which 7Bi-1Ag (a numerical value represents a weight ratio) is used. The I / O pins 14 include, for example, a ground pin, a power supply pin, a clock pin, and the like, in addition to those for inputting and outputting signals.
【００１５】本実施形態を図２（Ａ），（Ｂ）に基いて
順次説明すると、次のようになる。図２（Ａ）は、ＭＣ
Ｍ基板（第一の基板）１１とマザーボード（第二の基
板）１６とを接合する前の状態を示すものであり、図２
（Ｂ）はこれらを接合後の状態を示すものである。図２
（Ａ）において、上部は、第１の基板であるＭＣＭ基板
１１が、その上面にプリントされた配線１９と、ビアホ
ール２０と、下面にプリントされた配線２１、および配
線２１とＡｕ−Ｓｎはんだ合金１３を介して接続された
Ｉ／Ｏピン１４からなり、電極配線２１、Ａｕ−Ｓｎは
んだ１３、Ｉ／Ｏピン１４は電気的に接続されている。
そしてこのＭＣＭ基板１１の上面の配線１９に対向し
て、その上部に、半導体チップ１７がその電極バンプ１
８を含む表面を下部（ＭＣＭ基板）側に向けて（フェー
スダウン状態）配接され、電極バンプ１８とＩ／Ｏピン
１４とが電気的に接続されている。The present embodiment will be described below with reference to FIGS. 2A and 2B. FIG. 2 (A) shows the MC
FIG. 2 shows a state before the M substrate (first substrate) 11 and the motherboard (second substrate) 16 are joined.
(B) shows the state after joining them. FIG.
In (A), the upper part is a first substrate MCM substrate 11, a wiring 19 printed on its upper surface, a via hole 20, a wiring 21 printed on its lower surface, and a wiring 21 and an Au-Sn solder alloy. The I / O pins 14 are connected through the I / O pins 13, and the electrode wiring 21, the Au—Sn solder 13, and the I / O pins 14 are electrically connected.
A semiconductor chip 17 is provided on the upper surface of the MCM substrate 11 so as to face the wiring 19 and the electrode bump 1.
The electrode bumps 18 and the I / O pins 14 are electrically connected to each other with the surface including the surface 8 facing downward (the MCM substrate) (face down state).
【００１６】図２（Ａ）下部は基板１６面上に、対応す
る前記Ｉ／Ｏピン１４が接合される位置に電極配線２２
が載置されている。基板１６はガラスポリイミド等より
なり、例えばコンピュータのマザーボードとして使われ
る。基板１６上の配線２２上にははんだ合金のペースト
が塗布されている。前記ＭＣＭ基板１１は、Ｉ／Ｏピン
１４が基板１６上の対応する配線パターン２２にコンタ
クトするように、前記基板１６上に載置される。The lower part of FIG. 2A shows the electrode wiring 22 on the surface of the substrate 16 at the position where the corresponding I / O pin 14 is joined.
Is placed. The substrate 16 is made of glass polyimide or the like, and is used, for example, as a computer motherboard. A paste of a solder alloy is applied on the wiring 22 on the substrate 16. The MCM substrate 11 is placed on the substrate 16 such that the I / O pins 14 contact the corresponding wiring patterns 22 on the substrate 16.
【００１７】はんだ合金としては、例えばリフロー温度
が約１３６℃の、組成がＳｎ−５７Ｂｉ−１Ａｇと表さ
れるＳｎ−Ｂｉ系のはんだ合金を使う。このはんだ合金
は、約４２重量％のＳｎと約５７重量％のＢｉと、約１
重量％のＡｇとを含む。次に、前記ＭＣＭ基板１１を載
置した基板１６は、温度１３６℃に設定されたリフロー
炉中を通され、その結果はんだ合金はリフローし、図２
（Ｂ）のように、Ｉ／Ｏピン１４が、対応する配線パタ
ーン１２に接続される。As the solder alloy, for example, a Sn-Bi-based solder alloy having a reflow temperature of about 136 ° C. and a composition represented by Sn-57Bi-1Ag is used. This solder alloy contains about 42% by weight of Sn, about 57% by weight of Bi, and about 1% by weight.
% Ag by weight. Next, the substrate 16 on which the MCM substrate 11 is mounted is passed through a reflow furnace set at a temperature of 136 ° C., and as a result, the solder alloy is reflowed.
As shown in (B), I / O pins 14 are connected to corresponding wiring patterns 12.
【００１８】さらに、基板１６は前記リフロー炉から出
て室温に冷却されるが、この場合の温度差は高々１１６
℃程度にすぎず、仮にＩ／Ｏピン１４が１．３ｍｍピッ
チあるいはそれ以下のピッチで、しかもＭＣＭ基板１１
上の５０ｍｍ×５０ｍｍの領域に形成されていたとして
も、生じる熱歪みは290 μｍ程度で、前記１．３ｍｍピ
ッチの場合の１/ ３以下となる。 続いて図２（Ｂ）
は、図２（Ａ）上部のＩ／Ｏピン１４と、同図下部の電
極配線２２とが、本発明に係るはんだ合金２３であるＳ
ｎ−５７Ｂｉ−１Ａｇを用いることによって接合された
状態を示すものである。Further, the substrate 16 exits the reflow furnace and is cooled to room temperature. In this case, the temperature difference is at most 116.
° C, and if the I / O pins 14 are arranged at a pitch of 1.3 mm or less and the MCM substrate 11
Even if it is formed in the upper 50 mm × 50 mm area, the generated thermal strain is about 290 μm, which is not more than one third of the 1.3 mm pitch. Subsequently, FIG. 2 (B)
In FIG. 2A, the I / O pins 14 in the upper part and the electrode wirings 22 in the lower part of FIG.
It shows a state of being joined by using n-57Bi-1Ag.
【００１９】次に、本発明の効果を知るために、接合部
の熱疲労特性試験を行い、従来技術におけるＳｎ−３７
Ｐｂとの違いを比較した。その結果を表１に示す。Next, in order to know the effect of the present invention, a thermal fatigue characteristic test of the joint was conducted, and Sn-37 in the prior art was tested.
The difference from Pb was compared. Table 1 shows the results.
【００２０】[0020]
【表１】 [Table 1]
【００２１】図中サイクル数とは、Ｓｎ−３７Ｐｂにつ
いては室温からその固相線温度である１８３℃の間の温
度の昇降回数を、Ｓｎ−５７Ｂｉ−１Ａｇについては室
温から同様に１３６℃までの間の温度の昇降回数を示
す。Ｓｎ−３７Ｐｂはんだ合金を用いたサンプルでは、
１０００サイクル後に顕著なクラック、はんだ合金表面
のしわが発生し、ピンセットによるピッキングで破壊す
る接合部が現れたのに対し、Ｓｎ−５７Ｂｉ−１Ａｇは
んだ合金を用いたサンプルでは、２０００サイクル後ま
で、わずかなクラックの発生に留まり、ピンセットによ
るピッキングで破壊する接合部も現われなかった。In the figure, the number of cycles means the number of times the temperature rises and falls between room temperature and its solidus temperature of 183 ° C. for Sn-37Pb, and from room temperature to 136 ° C. for Sn-57Bi-1Ag. Shows the number of times the temperature rises and falls during that time. In the sample using the Sn-37Pb solder alloy,
After 1000 cycles, remarkable cracks and wrinkles on the surface of the solder alloy were generated, and joints broken by picking with tweezers appeared. On the other hand, in the sample using the Sn-57Bi-1Ag solder alloy, only a little after 2000 cycles. Only cracks were generated, and no joints that could be broken by picking with tweezers appeared.
【００２２】以上の説明では、はんだ合金２３としてＳ
ｎ−５７Ｂｉ−１Ａｇを用いたが、本発明では固相線温
度が約１５０℃以下となるはんだ合金であれば、どのよ
うなものを用いてもよい。例えば、Ｓｎを４２〜５９重
量％、Ｂｉを４１〜５８重量％含むＳｎ−Ｂｉ系のはん
だ合金を用いてもよい。また、１１７℃の固相線温度を
有するＳｎ−Ｉｎ系のはんだ合金（Ｉｎを４８重量％、
Ｓｎを５２重量％含む）を用いてもよい。In the above description, the solder alloy 23 is S
Although n-57Bi-1Ag was used, any solder alloy having a solidus temperature of about 150 ° C. or less may be used in the present invention. For example, a Sn-Bi-based solder alloy containing 42 to 59% by weight of Sn and 41 to 58% by weight of Bi may be used. Further, a Sn-In based solder alloy having a solidus temperature of 117 ° C. (48% by weight of In,
Sn (containing 52% by weight).
【００２３】以上、本発明を好ましい実施例について説
明したが、本発明は上記の実施例に限定されるものでは
なく、特許請求の範囲に記載した範囲内において、様々
な変形や変更が可能である。Although the present invention has been described with reference to preferred embodiments, the present invention is not limited to the above-described embodiments, and various modifications and changes are possible within the scope of the appended claims. is there.
【００２４】[0024]
【発明の効果】本発明によって次のような効果が得られ
る。請求項１から請求項１５までの記載の発明によれ
ば、固相線温度が１５０℃程度以下のＳｎ，Ｂｉを主成
分とするはんだ合金を用いることによって接合すること
により、基板間の熱膨張率の差により生じる、接合部は
んだ合金への応力歪みを低減し、かつ、接合部のはんだ
合金の変形を抑えることができ、接合信頼性を確保でき
る。また、低誘電率ガラスであるポリイミド材を使用し
たマザーボード基板では、耐熱性が低下する問題がある
が、本発明はこの要求に対しても、固相線温度の低いＳ
ｎＢｉ共晶系はんだ合金を用いることで対応できる。さ
らに低融点はんだ合金の使用は、リムーブ、リプレス時
の熱ストレス緩和という利点も併せ持つものである。According to the present invention, the following effects can be obtained. According to the first to fifteenth aspects of the present invention, the thermal expansion between the substrates is achieved by joining by using a solder alloy mainly composed of Sn and Bi having a solidus temperature of about 150 ° C. or less. It is possible to reduce the stress distortion to the solder alloy at the joint portion caused by the difference in the rates, suppress the deformation of the solder alloy at the joint portion, and secure the joint reliability. In addition, a mother board substrate using a polyimide material, which is a low dielectric constant glass, has a problem that heat resistance is reduced.
This can be achieved by using an nBi eutectic solder alloy. Further, the use of a low melting point solder alloy has an advantage of reducing thermal stress during removal and repressing.
【図１】ＭＣＭ基板を従来方法であるはんだ合金によっ
てマザーボードに実装した構成図である。FIG. 1 is a configuration diagram in which an MCM substrate is mounted on a motherboard using a conventional solder alloy.
【図２】（Ａ）は、本発明に係るはんだ合金を用いて、
モジュール基板と配線基板を接続する前の、それぞれの
状態を示す図であり、（Ｂ）は本発明に係るはんだ合金
を用いて、モジュール基板と配線基板を接続後の状態を
示す図である。FIG. 2 (A) shows the results of using the solder alloy according to the present invention.
It is a figure which shows each state before connecting a module board and a wiring board, and (B) is a figure which shows the state after connecting a module board and a wiring board using the solder alloy which concerns on this invention.
１、１１ モジュール基板（第一の基板） ２、６Ａ、１２、１９、２１、２２ 電極配線 ３ Ａｕ−Ｓｎはんだ合金 ４、１４ 入出力ピン（Ｉ／Ｏピン） ５ Ｓｎ−３７Ｐｂはんだ合金 ６ 配線基板（第二の基板） １３ Ｓｎー５７Ｂｉ−１Ａｇはんだ合金 １６ マザーボード（第二の基板） １７ 半導体チップ １８ 電極バンプ ２０ ビアホール ２３ Ｓｎ−５７Ｂｉ−１Ａｇはんだ合金 1, 11 module substrate (first substrate) 2, 6A, 12, 19, 21, 22 electrode wiring 3 Au-Sn solder alloy 4, 14 input / output pin (I / O pin) 5 Sn-37Pb solder alloy 6 wiring Substrate (second substrate) 13 Sn-57Bi-1Ag solder alloy 16 Motherboard (second substrate) 17 Semiconductor chip 18 Electrode bump 20 Via hole 23 Sn-57Bi-1Ag solder alloy
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０１Ｌ 23/32 Ｈ０１Ｌ 23/14 Ｃ (72)発明者 山岸 康男 神奈川県川崎市中原区上小田中４丁目１番 １号 富士通株式会社内 Ｆターム(参考） 5E319 AA03 AB03 AC02 BB05 CC36 CD26 GG11 GG20 ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) H01L 23/32 H01L 23/14 C (72) Inventor Yasuo Yamagishi 4-1-1 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture No. 1 Fujitsu Limited F term (reference) 5E319 AA03 AB03 AC02 BB05 CC36 CD26 GG11 GG20
Claims (15)
有する第１の基板と、相互に対向する第３および第４の
主面を有し、前記第１の基板の近傍に、前記第３の主面
が前記第１の基板の前記第２主面に対面するように配設
された第２の基板と、 前記第１の主面上に担持されたチップと、 前記第２の主面上に担持された複数の導体ピンと、 前記第３の主面上に形成された導体パターンと、 前記第３の主面上において、前記複数の導体ピンの各々
を、前記導体パターンに電気的および機械的に接合する
はんだ合金とよりなる電子装置において、 前記はんだ合金は、約１５０℃以下の固相線温度を有す
ることを特徴とする電子装置。A first substrate having first and second main surfaces opposed to each other; and a third and fourth main surface opposed to each other. A second substrate disposed so that the third main surface faces the second main surface of the first substrate; a chip carried on the first main surface; A plurality of conductor pins carried on the main surface of the conductive pattern; a conductive pattern formed on the third main surface; and a conductive pattern formed on the third main surface. An electronic device comprising an electrically and mechanically joined solder alloy, wherein the solder alloy has a solidus temperature of about 150 ° C. or less.
重量％、Ｂｉを約４１〜５８重量％含むはんだ合金より
なることを特徴とする請求項１記載の電子装置。2. The solder alloy according to claim 1, wherein Sn is approximately 42 to 59.
2. The electronic device according to claim 1, comprising a solder alloy containing about 41 to 58% by weight of Bi.
相線温度を有することを特徴とする請求項１記載の電子
装置。3. The electronic device according to claim 1, wherein the solder alloy has a solidus temperature of about 136 ° C. or less.
金の固相線温度との間の温度差に対応して前記導体ピン
に生じる熱歪みが、前記導体ピンのピッチの約１/ ３以
下になるように、組成を設定されていることを特徴とす
る請求項１乃至３のうち、いずれか一項記載の電子装
置。4. The solder alloy according to claim 1, wherein a thermal strain generated in the conductor pin corresponding to a temperature difference between room temperature and a solidus temperature of the solder alloy is about / or less of a pitch of the conductor pin. The electronic device according to any one of claims 1 to 3, wherein a composition is set so that
％、Ｂｉを約５９重量％、Ａｇを約１重量％含む請求項
１乃至４のうち、いずれか一項記載の電子装置。5. The electronic device according to claim 1, wherein the solder alloy contains about 42% by weight of Sn, about 59% by weight of Bi, and about 1% by weight of Ag.
約１．３ｍｍ以下のピッチで形成されていることを特徴
とする請求項１乃至５のうち、いずれか一項記載の電子
装置。6. The conductor pin is provided on the second main surface,
The electronic device according to any one of claims 1 to 5, wherein the electronic device is formed at a pitch of about 1.3 mm or less.
特徴とする請求項１乃至６のうち、いずれか一項記載の
電子装置。7. The electronic device according to claim 1, wherein the first substrate is made of AlN.
なることを特徴とする請求項１乃至７のうち、いずれか
一項記載の電子装置。8. The electronic device according to claim 1, wherein the second substrate is made of glass polyimide.
第２の主面上、一辺が約５０ｍｍ以上の領域に形成され
ていることを特徴とする請求項１乃至８のうち、いずれ
か一項記載の電子装置。9. The semiconductor device according to claim 1, wherein the conductor pin is formed on the second main surface of the first substrate in a region having one side of about 50 mm or more. An electronic device according to claim 1.
を有し、前記第１の主面上にチップを担持し、前記第２
の主面上に複数の導体ピンを担持する第１の基板と、 相互に対向する第３および第４の主面を有し、前記第１
の基板の近傍に、前記第３の主面が、前記第１の基板の
前記第２主面に対面するように配設され、前記第３の主
面上には導体パターンが担持され、前記第２の主面上の
導体ピンが前記第３の主面上の導体パターンに電気的お
よび機械的に接続された電子装置の製造方法において、 前記第１および第２の基板を、前記第２の主面上の導体
ピンの各々が、前記第３の主面上の対応する導体パター
ンにコンタクトするように配設する工程と、 前記第３の主面上において、前記複数の導体ピンの各々
を、対応する前記導体パターンに、はんだ合金をリフロ
ーすることにより接続するリフロー工程とを含み、 前記リフロー工程は、前記はんだ合金として、１８３℃
未満の固相線温度を有するはんだ合金を用い、前記はん
だ合金をリフローする際に、実質的に前記固相線温度に
等しい温度まで加熱する工程を含むことを特徴とする電
子装置の製造方法。10. A semiconductor device having a first and a second main surface facing each other, carrying a chip on the first main surface,
A first substrate carrying a plurality of conductor pins on a main surface of the first substrate, and third and fourth main surfaces facing each other;
The third main surface is disposed near the second main surface of the first substrate, and a conductor pattern is carried on the third main surface; In a method of manufacturing an electronic device in which a conductor pin on a second main surface is electrically and mechanically connected to a conductor pattern on the third main surface, the first and second substrates are connected to the second Arranging each of the conductor pins on the third main surface so as to contact a corresponding conductor pattern on the third main surface; and forming each of the plurality of conductor pins on the third main surface. A reflow step of connecting a solder alloy to the corresponding conductor pattern by reflow soldering.
A method of manufacturing an electronic device, comprising: using a solder alloy having a solidus temperature of less than and heating the solder alloy to a temperature substantially equal to the solidus temperature when reflowing the solder alloy.
９重量％、Ｂｉを約４１〜５８重量％含むはんだ合金よ
りなることを特徴とする請求項１０記載の電子装置の製
造方法。11. The solder alloy according to claim 11, wherein Sn has a content of about 42-5.
11. The method of manufacturing an electronic device according to claim 10, comprising a solder alloy containing 9% by weight and about 41 to 58% by weight of Bi.
のはんだ合金を使用する工程を含むことを特徴とする請
求項１０記載の電子装置の製造方法。12. The method according to claim 10, further comprising the step of using a solder alloy having a solidus temperature of about 150 ° C. or less.
線温度を有し、前記リフロー工程は、前記はんだ合金を
約１３６℃まで加熱することを特徴とする請求項１０記
載の電子装置の製造方法。13. The electronic device of claim 10, wherein the solder alloy has a solidus temperature of about 136 ° C., and wherein the reflow step heats the solder alloy to about 136 ° C. Production method.
合金の固相線温度との間の温度差に対応して前記導体ピ
ンに生じる熱歪みが、前記導体ピンのピンのピッチの約
１/ ３以下になるように、組成が設定されていることを
特徴とする請求項１０乃至１３のうち、いずれか一項記
載の電子装置の製造方法。14. The solder alloy according to claim 1, wherein a thermal strain generated in said conductor pin corresponding to a temperature difference between room temperature and a solidus temperature of said solder alloy is about 1/1 / of a pitch of said conductor pin. 14. The method of manufacturing an electronic device according to claim 10, wherein the composition is set so as to be 3 or less.
％、Ｂｉを約５９重量％、Ａｇを約１重量％含むことを
特徴とする請求項１０〜１４のうち、いずれか一項記載
の電子装置の製造方法。15. The solder alloy according to claim 10, wherein the solder alloy contains about 42% by weight of Sn, about 59% by weight of Bi, and about 1% by weight of Ag. A method for manufacturing an electronic device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20561598A JP3715438B2 (en) | 1998-07-21 | 1998-07-21 | Electronic device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20561598A JP3715438B2 (en) | 1998-07-21 | 1998-07-21 | Electronic device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000036657A true JP2000036657A (en) | 2000-02-02 |
| JP3715438B2 JP3715438B2 (en) | 2005-11-09 |
Family
ID=16509820
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20561598A Expired - Fee Related JP3715438B2 (en) | 1998-07-21 | 1998-07-21 | Electronic device and manufacturing method thereof |
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| Country | Link |
|---|---|
| JP (1) | JP3715438B2 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100482940B1 (en) * | 2000-05-03 | 2005-04-15 | 인터내셔널 비지네스 머신즈 코포레이션 | High density column grid array connections and method thereof |
| CN100356530C (en) * | 2002-08-01 | 2007-12-19 | 罗姆股份有限公司 | Mfg. method for semiconductor device |
| US8345438B2 (en) | 2006-08-31 | 2013-01-01 | Fujitsu Limited | Electronic part module and method of making the same |
| JP2008177560A (en) * | 2007-12-25 | 2008-07-31 | Sharp Corp | Solar cell and string |
| JP2013219118A (en) * | 2012-04-05 | 2013-10-24 | Mitsubishi Electric Corp | Solar battery and manufacturing method of the same |
| WO2017094537A1 (en) * | 2015-12-03 | 2017-06-08 | ソニー株式会社 | Semiconductor chip and electronic device |
| US11048028B2 (en) | 2015-12-03 | 2021-06-29 | Sony Semiconductor Solutions Corporation | Semiconductor chip and electronic apparatus for suppressing degradation of semiconductor chip |
| US11619772B2 (en) | 2015-12-03 | 2023-04-04 | Sony Semiconductor Solutions Corporation | Semiconductor chip and electronic apparatus |
| JP2020148479A (en) * | 2019-03-11 | 2020-09-17 | 株式会社日本マイクロニクス | Electrical connection device |
| JP7263060B2 (en) | 2019-03-11 | 2023-04-24 | 株式会社日本マイクロニクス | Electrical connection device |
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