JP5246038B2 - Circuit board - Google Patents

Description

The present invention relates to a circuit board .

  With regard to a circuit board mounting structure for electrically connecting a semiconductor element and a circuit board, mounting of a highly integrated LSI (Large Scale Integration Circuit) is required. For this reason, it is necessary to improve the mounting density of the circuit board and increase the number of input / output pins as the LSI is highly integrated. In order to cope with an increase in the number of input / output pins, a BGA (Ball Grid Array) type mounting structure is realized in which a semiconductor package and a circuit board are joined via solder bumps arranged in a grid pattern.

  When an electronic device mounted with a semiconductor package is operated using such a BGA type mounting structure, if the electronic device shifts from a low load state to a high load state, the operating temperature of the electronic device in the high load state rises. Then, the semiconductor package and the circuit board are thermally expanded. Taking a ceramic package and a glass epoxy substrate as an example, the circuit board has a higher coefficient of thermal expansion than the semiconductor package. Therefore, the amount of thermal expansion of the circuit board increases, and the amount of thermal expansion of the semiconductor package decreases. As a result, stress is generated in the solder bumps interposed between the circuit board and the semiconductor package.

  When the high load state and the low load state of the electronic device are repeated, the circuit board is repeatedly expanded and contracted, so that stress is repeatedly generated in the solder bump. When stress is repeatedly generated in the solder bumps, the solder bumps are subjected to metal fatigue and cracks are generated. The generated crack grows at the interface between the solder bump and the electrode. When cracks occur in the solder bumps, the conductive area between the circuit board and the semiconductor package in the solder bumps decreases, and the electrical resistance in the solder bumps increases. As the crack progresses further, the electrical connection is completely broken and the solder bump is disconnected. Therefore, there arises a problem that the mounting reliability in the semiconductor package and the circuit board is lowered.

  In order to cope with the above problem, there has been proposed a bump structure including a cylindrical container containing a conductive liquid in a solder bump interposed between a semiconductor package and a circuit board (for example, Patent Document 1). The container is disposed so as to be perpendicular to the electrodes on the semiconductor package and the circuit board. The conductive liquid described above has a property of solidifying when exposed to air. When a crack occurs in the solder bump, the container enclosed in the solder bump is destroyed by the crack, and the conductive liquid inside the container exudes into the crack. The conductive liquid is exposed to air and solidifies in the crack. The crack is filled with a conductive material. Therefore, an increase in the electrical resistance of the solder bump due to the occurrence of cracks is suppressed.

However, in manufacturing a circuit board including a bump having such a bump structure, the conductive liquid in the container has a property of solidifying in the air, so that the container manufacturing process needs to be performed in a vacuum. For this reason, there is a problem that the manufacturing cost of the container increases.
Further, the distance between the semiconductor package and the circuit board is limited by the height of the container. When solder bumps are formed between electrodes on a semiconductor package and a circuit board, solder bumps lower than the height of the container may be formed. In such a case, since the self-alignment effect using the surface tension of the solder bumps is lost, there is a problem that the semiconductor package and the circuit board cannot be connected.

JP 2008-91926 A

  An object of this invention is to provide the circuit board which can suppress the increase in the electrical resistance accompanying the crack generation of a solder bump, and the repair method of the crack of a solder bump.

  In order to solve the problems of the present invention, according to a first aspect of the present invention, a first substrate, a first electrode formed on the first substrate, become liquid at a predetermined temperature, and Sn (tin) A first conductive material that forms an alloy with the first conductive material, a first capsule that is provided on the first electrode and includes the first conductive material, a solder bump that covers the first capsule and contains Sn, A circuit board comprising: is provided.

  According to the second aspect of the present invention, inside the solder bump containing Sn, a capsule containing a conductive substance that becomes liquid at a predetermined temperature and forms an alloy with Sn is disposed, and the solder bump is cracked. The method of repairing a crack in a solder bump in which the conductive material fills the crack when the capsule is broken and the conductive material in the capsule comes out of the capsule. And

  According to the present invention, the conductive substance that forms an alloy with Sn becomes a liquid at room temperature to 80.0 ° C., which is a normal operating temperature of electronic equipment. Therefore, when a crack is generated in the solder bump and the capsule breaks the capsule, the conductive material that has become liquid exudes into the crack. The conductive substance reacts with Sn contained in the solder bump to form an alloy containing Sn. Since the crack is filled with an alloy containing Sn, an increase in the electrical resistance of the solder bump accompanying the generation of the crack can be suppressed.

FIG. 1 is a diagram illustrating an electrode structure according to the first embodiment. FIG. 2 is a diagram illustrating a manufacturing process of the electrode structure according to the first embodiment. FIG. 3 is a diagram illustrating a manufacturing process of the electrode structure according to the first embodiment. FIG. 4 is a diagram illustrating a manufacturing process of the electrode structure according to the first embodiment. FIG. 5 is a diagram illustrating the semiconductor device according to the first embodiment. FIG. 6 is a diagram illustrating manufacturing steps of the semiconductor device according to the first embodiment. FIG. 7 is a diagram illustrating an electrode structure of a semiconductor package according to the second embodiment. FIG. 8 is a diagram illustrating a manufacturing process of the electrode structure of the semiconductor package according to the second embodiment. FIG. 9 is a diagram illustrating manufacturing steps of the electrode structure of the semiconductor package according to the second embodiment. FIG. 10 is a diagram illustrating manufacturing steps of the electrode structure of the semiconductor package according to the second embodiment. FIG. 11 is a diagram illustrating the semiconductor device according to the second embodiment. FIG. 12 is a diagram illustrating manufacturing steps of the semiconductor device according to the second embodiment. FIG. 13 is a state diagram of a Ga—In alloy that can be used in Example 1 and Example 2. FIG. 14 is a phase diagram of a Ga—Sn alloy that can be used in Example 1 and Example 2.

  Hereinafter, the circuit board according to the first and second embodiments of the present invention and the method for repairing cracks in the solder bumps will be described. However, the present invention is not limited to each example.

  In the first embodiment of the present invention, FIG. 1 to FIG. 6, FIG. 13 and FIG. 14 describe the semiconductor device 70 and the method of manufacturing the semiconductor device 70 in detail.

  FIG. 1 shows an electrode structure 50 provided in a semiconductor device 70. FIG. 1A is a plan view of the electrode structure 50. 1B is a cross-sectional view taken along line XY in FIG. 1A.

1A and 1B show a circuit board 1 and an electrode structure 50. FIG.
The circuit board 1 is formed from, for example, a glass epoxy board or a build-up board formed by stacking an insulating layer and a wiring layer.
The electrode structure 50 includes an electrode pad 2, a capsule 3, and an adhesive 4. As shown in FIGS. 1A and 1B, the electrode structure 50 is provided on the circuit board 1.
The electrode pad 2 is provided on the circuit board 1. The electrode pad 2 is formed with gold plating on, for example, copper or nickel. The electrode pad 2 has a substantially circular shape, for example. The diameter of the electrode pad 2 is, for example, 600 μm. The electrode pad 2 has a thickness of 30 μm to 60 μm, for example.
A recess 8 is formed in the electrode pad 2. The depression 8 has, for example, a diameter of 40 μm to 45 μm and a depth of 5 μm to 10 μm. The depression 8 is formed to ensure that the capsule 3 is fixed on the electrode pad 2. As shown in FIG. 5B described later, when the crack 13 occurs in the solder bump 12 near the surface of the electrode pad 2, the capsule 3 is surely destroyed by the crack 13.
The capsule 3 includes a conductive material 5 and an outer shell 6.
The capsule 3 is formed on the depression 8 of the electrode pad 2 via the adhesive 4. When the diameter of the electrode pad 2 is, for example, 600 μm, the capsule 3 is desirably disposed at a position of, for example, 0 μm to 200 μm from the center of the electrode pad 2. When the capsule 3 is disposed at a position away from the center of the electrode pad 2 by more than 200 μm, when the capsule 3 is broken by the crack 13 as shown in FIG. 5B described later, the conductive material 5 is soldered from the crack 13. There is a possibility of overflowing out of the bump 12. There is a possibility that the conductive material 5 overflowing out of the solder bumps 12 may cause a short circuit between the adjacent electrode pads 2.
The conductive material 5 preferably has a melting point of, for example, 15.7 ° C. to 80.0 ° C. and contains a material that forms an alloy with Sn (tin). For example, Ga (gallium), Ga—In (indium) based alloy, or Ga—Sn based alloy can be used as the conductive material 5. The conductive material 5 is desirably a liquid in the range of the operating temperature of the electronic device, for example, from room temperature to 80.0 ° C. When Ga is used as the conductive material 5, the melting point of the conductive material 5 is 29.8 ° C.
FIG. 13 shows a phase diagram of the Ga—In alloy. In FIG. 13, the vertical axis represents the temperature (° C.) of the Ga—In alloy. In FIG. 13, the lower horizontal axis indicates the number of atomic percent (at%) of In. In FIG. 13, the horizontal axis at the top indicates In% by weight (wt%). A solid line in FIG. 13 indicates a liquidus line of the Ga—In alloy. The composition ratio indicated by the horizontal axis of the Ga—In alloy indicates that all the Ga—In alloy exists in the liquid phase at a temperature above the liquidus line.
As shown at point A in FIG. 13, the melting point of Ga is 29.8 ° C. As shown at point B in FIG. 13, the melting point of the Ga—In alloy in which the atomic percentage of Ga and the atomic percentage of In are 83.5: 16.5 is 15.7 ° C. As indicated by point C in FIG. 13, the melting point of the Ga—In alloy in which the atomic percentage of Ga and the atomic percentage of In are 65.5: 35.5 is 80 ° C.
When a Ga—In alloy is used as the conductive material 5, the conductive material 5 preferably has a melting point of 15.7 ° C. to 80.0 ° C. In order to obtain such a melting point of the conductive material 5, as shown in the range of point A-point B-point C in the liquidus line of FIG. % To 65 atomic%, and the Ga content ratio is preferably 35 atomic% to 100 atomic%.
FIG. 14 shows a phase diagram of the Ga—Sn alloy. In FIG. 14, the horizontal axis indicates the temperature (° C.) of the Ga—Sn alloy. In FIG. 14, the lower horizontal axis indicates the number of atoms of Sn (at%). In FIG. 14, the upper horizontal axis represents Sn weight% (wt%). A solid line in FIG. 14 indicates a liquidus line of the Ga—Sn alloy. The composition ratio indicated by the horizontal axis of the Ga—Sn alloy indicates that the Ga—Sn alloy exists in the liquid phase at a temperature above the liquidus.
As indicated by point D in FIG. 14, the melting point of Ga is 29.8 ° C. As shown at point E in FIG. 14, the melting point of the Ga—Sn alloy in which the atomic percentage of Ga and the atomic percentage of Sn are 95: 5 is 20 ° C. As shown at point F in FIG. 14, the melting point of the Ga—Sn alloy in which the atomic percentage of Ga and the atomic percentage of Sn are 75:25 is 80 ° C.
When a Ga—Sn based alloy is used as the conductive material 5, the melting point of the conductive material 5 is desirably 20.0 ° C. to 80.0 ° C. In order to obtain such a melting point of the conductive material 5, the Sn content ratio in the Ga—Sn alloy is 0 atomic number as shown in the range of point D-point E-point F in the liquidus line of FIG. % To 25 atomic%, and the Ga content ratio is preferably 75 atomic% to 100 atomic%.
The outer shell 6 is formed so as to enclose the conductive material 5. For example, the outer shell 6 preferably has a substantially cylindrical shape. The diameter of the bottom surface of the outer shell 6 is, for example, 40 μm to 45 μm. The height of the outer shell 6 is, for example, 55 μm to 60 μm. The outer shell 6 is formed by sequentially laminating, for example, Ni (nickel) plating as an adhesion layer and Au (gold) plating as an antioxidant layer on the inner wall of a cylindrical container made of Cu (copper), for example. The copper container is formed with a thickness of 1 μm to 2 μm, for example. The adhesion layer is formed with a thickness of 1 μm to 2 μm, for example. The antioxidant layer is formed with a thickness of 1 μm to 2 μm, for example. In order to suppress the corrosive action of Ga (gallium) contained in the conductive material 5 against the metal forming the outer shell 6 on the Au plating on the inner wall of the outer shell 6, as a coating layer, for example, polyphenylene ether (PPE) or polyimide ( PI) is formed. The coating layer is formed with a thickness of 1 μm to 2 μm, for example.
The adhesive 4 is formed on a recess 8 formed on the electrode pad 2. The adhesive 4 is formed for bonding the capsule 3 on the electrode pad 2. The adhesive 4 is formed with a thickness of 2 μm to 3 μm, for example.

  2 to 4 are diagrams illustrating manufacturing steps of the electrode structure 50 according to the first embodiment. In the manufacturing process, the same components as those described in the electrode structure 50 illustrated in FIGS. 1A and 1B are denoted by the same reference numerals, and the description thereof is omitted.

  FIG. 2A is a diagram showing how the conductive material 5 is prepared. The conductive material 5 is cooled to a temperature equal to or lower than the melting point described above, and is processed into a substantially spherical shape. The radius of the conductive material 5 having a substantially spherical shape is, for example, 20 μm to 25 μm.

  FIG. 2B is a diagram showing how the outer shell 6 is prepared.

  FIG. 2C is a diagram showing a state in which the conductive material 5 is arranged in the outer shell 6. As shown in FIG. 2C, the conductive material 5 is disposed in the outer shell 6. When the conductive material 5 is disposed in the outer shell 6, the temperatures of the conductive material 5 and the outer shell 6 are less than the melting point described above using a cooling device (not shown) in order to maintain the shape of the conductive material 5. It is desirable to be cooled to a temperature of

  FIG. 2D is a diagram illustrating how the outer shell 6 having the conductive material 5 disposed therein is processed. As shown in FIG. 2D, the opening of the outer shell 6 in which the conductive material 5 is disposed is sealed by, for example, caulking. The opening of the outer shell 6 may be sealed by brazing. This sealing process prevents the conductive material 5 from flowing out of the outer shell 6 even when the temperature of the conductive material 5 inside the outer shell 6 reaches the melting point or higher and the conductive material 5 becomes liquid. Can do. By this sealing process, the capsule 3 in which the conductive material 5 is enclosed by the outer shell 6 is formed.

  FIG. 3A is a diagram illustrating the preparation of the circuit board 1 provided with the electrode pads 2.

  FIG. 3B is a diagram showing the formation of the resist layer 7 so as to cover the electrode pads 2 provided on the circuit board 1. As shown in FIG. 3B, the resist layer 7 is formed so as to cover the electrode pads 2 on the circuit board 1 by, for example, a spin coating method using a resist solution. Next, an opening 7a of the resist layer 7 having a diameter of 40 μm to 45 μm is formed on the electrode pad 2 by disposing a metal mask (not shown) on the circuit board 1 and exposing and developing the resist layer 7. The A part of the electrode pad 2 is exposed through the opening 7 a of the resist layer 7. In addition to the spin coating method, the resist layer 7 may be formed by attaching a photosensitive dry film on the circuit board 1 and performing exposure and development.

  FIG. 3C is a diagram illustrating the formation of the depression 8 in the electrode pad 2. As shown in FIG. 3C, the electrode pad 2 exposed through the opening 7a of the resist layer 7 is etched by spraying an unillustrated acid or etching solution onto the circuit board 1 using the resist layer 7 as a mask. By etching the electrode pad 2, a recess 8 is formed in the electrode pad 2. The recess 8 has a diameter of, for example, 40 μm to 45 μm and a depth of 5 μm to 10 μm. After the depression 8 is formed in the electrode pad 2, the resist layer 7 is removed from the circuit board 1.

  FIG. 3D is a diagram showing how the adhesive 4 is formed on the recess 8 formed in the electrode pad 2. As shown in FIG. 3D, the adhesive 4 is formed on the depression 8 by using, for example, a dispenser (not shown). The adhesive 4 is desirably conductive and has a property of being cured at a temperature equal to or higher than the melting point of a solder bump 12 described later. As the adhesive 4, for example, a one-component epoxy adhesive containing silver can be used.

FIG. 4A is a diagram showing how the capsule 3 is arranged on the adhesive 4 formed on the depression 8. 4B is a cross-sectional view taken along line XY in FIG. 4A.
As shown in FIGS. 4A and 4B, the capsule 3 is disposed on the adhesive 4 formed on the recess 8 using, for example, a jig (not shown). After the capsule 3 is formed on the adhesive 4, the adhesive 4 interposed between the capsule 3 and the electrode pad 2 is cured, and the capsule 3 is bonded onto the electrode pad 2. Thus, the electrode structure 50 is formed by obtaining the steps shown in FIGS. 2A to 4B described above.

FIG. 5A is a diagram illustrating the semiconductor device 70 according to the first embodiment. The semiconductor device 70 includes an electrode structure 60 of a semiconductor package in addition to the electrode structure 50 illustrated in FIG. 1B. Note that the same components as those described in FIGS. 1A and 1B are denoted by the same reference numerals, and description thereof is omitted.
As shown in FIG. 5A, the electrode structure 60 of the semiconductor package includes the semiconductor package 10, the electrode pads 11, the solder bumps 12, and the insulating coating layer 15.
The semiconductor package 10 is obtained by mounting a semiconductor element (not shown) in a package. The semiconductor package 10 includes a solder bump 12 to have a BGA (Ball Grid Array) type mounting structure.
The electrode pad 11 is provided on the semiconductor package 10. The electrode pad 11 is formed to apply a voltage to a semiconductor element (not shown) mounted on the semiconductor package 10. The electrode pad 11 is formed with gold plating on, for example, copper or nickel.
The solder bumps 12 are adhesive members that electrically connect the electrode pads 2 on the circuit board 1 and the electrode pads 11 on the semiconductor package 10. The solder bumps 12 are formed with a diameter of 600 μm, for example. The solder bumps 12 are, for example, Sn—Pb (lead) based alloy, Sn—Bi (bismuth) based alloy, Sn—In based alloy, Sn—Zn (zinc) based alloy, Sn—Ag (silver) based alloy, Sn It is desirable to include an -Ag-Cu (copper) -based alloy or a Sn-Cu-based alloy. The solder bump 12 is formed so as to enclose the capsule 3 on the electrode pad 2.
The insulating coating layer 15 is formed so as to cover the semiconductor package 10 and the outer periphery of the electrode pad 11. The thickness of the insulating coating layer 15 is, for example, 5 μm to 20 μm. The insulating coating layer 15 is preferably formed of a material having high insulation and mechanical strength, and excellent heat resistance, chemical resistance and flame retardancy. The insulating coating layer 15 is made of polyimide, for example.

FIG. 5B is a diagram showing a semiconductor device 71 in which the electrode structure 50 and the electrode structure 60 of the semiconductor package are electrically connected by the solder bump 12 including the crack 13 inside.
First, as shown in FIG. 5B, a description will be given of how the cracks 13 are generated in the solder bumps 12 related to the semiconductor device 71. When an electronic device (not shown) on which the semiconductor device 71 is mounted operates, when the electronic device shifts from a low load state to a high load state, the operating temperature of the electronic device is changed from a normal operating temperature of the electronic device to a high load state. As a result, the circuit board 1 in the electrode structure 50 and the semiconductor package 10 in the electrode structure 60 of the semiconductor package are thermally expanded. The thermal expansion coefficient of the circuit board 1 is, for example, 16 ppm. The thermal expansion coefficient of the semiconductor package 10 is, for example, 12 ppm. Therefore, the circuit board 1 has a larger thermal expansion coefficient than the semiconductor package 10. Therefore, the thermal expansion amount of the circuit board 1 is increased, and the thermal expansion amount of the semiconductor package 10 is decreased. As a result, stress is generated in the solder bumps 12 interposed between the circuit board 1 and the semiconductor package 10.

  When the high load state and the low load state of the electronic device are repeated, the expansion and contraction of the circuit board 1 is repeated, so that stress is repeatedly generated in the solder bumps 12. When stress is repeatedly generated in the solder bumps 12, the solder bumps 12 are fatigued and cracks 13 are generated. The generated crack 13 grows at the interface between the solder bump 12 and the electrode pad 2. When the crack 13 occurs in the solder bump 12, the conductive area between the circuit board 1 and the semiconductor package 10 in the solder bump 12 decreases, and thus the electrical resistance in the solder bump 12 increases. When the crack 13 further progresses, the electrical connection is completely broken, and the solder bump 12 is disconnected. Therefore, there arises a problem that the mounting reliability in the semiconductor package 10 and the circuit board 1 is lowered.

  As shown in FIG. 5B, when the crack 13 is generated in the solder bump 12, the capsule 3 containing the conductive material 5 is broken by the crack 13. The conductive substance 5 has a property of becoming a liquid in a range from room temperature to 80 ° C., which is the use environment temperature of the electronic device. Therefore, the conductive material 5 that is a liquid oozes into the crack 13. Since the exuded conductive material 5 contains Ga, it reacts with Sn contained in the solder bump 12 to form a Ga—Sn alloy 14. Since the Ga—Sn alloy 14 has conductivity, an increase in the electrical resistance of the solder bump 12 due to the generation of the crack 13 can be suppressed.

Next, the relationship between the volume of the conductive material 5 in the capsule 3 provided on the electrode pad 2 and the volume of the crack 13 formed in the solder bump 12 will be described. Assuming that the diameter of the solder bump 12 is, for example, 600 μm and the width of the crack 13 generated in the solder bump 12 is, for example, 1 μm, the volume of the crack 13 when the solder bump 12 is completely disconnected by the crack 13 is approximately 283000 μm ^3. It becomes.
On the other hand, the volume of the conductive material 5 having a substantially spherical shape with a radius of, for example, 25 μm is approximately 65500 μm ³ . When, for example, four capsules 3 containing the conductive material 5 are arranged on the electrode pad 2, the volume of the conductive material 5 on the electrode pad 2 is approximately 262000 μm ³ . With such a configuration, the volume of the crack 13 and the volume of the conductive material 5 described above are approximately equal. For this reason, the cracks 13 generated in the solder bumps 12 by the conductive material 5 can be substantially filled.
However, when the volume of the conductive material 5 becomes larger than the volume of the crack 13 in the solder bump 12, the conductive material 5 overflows from the crack 13 to the outside of the solder bump 12. The conductive material 5 overflowing outside the solder bumps 12 causes a problem that the adjacent electrode pads 2 are short-circuited. Therefore, it is desirable that the volume of the conductive material 5 is not more than the volume of the crack 13.

  FIG. 6 is a diagram illustrating the method of manufacturing the semiconductor device 70 according to the first embodiment. Note that in the manufacturing method, the same components as those described with reference to the semiconductor device 70 illustrated in FIG. 5A are denoted by the same reference numerals, and description thereof is omitted.

  FIG. 6A is a diagram showing how the electrode structure 50 is prepared.

FIG. 6B is a diagram illustrating the preparation of an electrode structure 60 of a semiconductor package having the semiconductor package 10, the electrode pads 11, the solder bumps 12, and the insulating coating layer 15.
As shown in FIG. 6B, the solder bumps 12 in the electrode structure 60 of the semiconductor package are disposed so as to face the electrode pads 2 on the circuit board 1. At this time, it is desirable to apply a solder paste (not shown) so as to cover the electrode pads on the circuit board 1.

FIG. 6C is a diagram showing heat treatment with the electrode pads 2 on the circuit board 1 and the solder bumps 12 in the electrode structure 60 of the semiconductor package facing each other.
As shown in FIG. 6C, the electrode structure 60 of the semiconductor package is connected to the electrode pad 2 on the circuit board 1 by heating and melting the solder bump 12 on the electrode pad 11 by a reflow process (not shown). Is done. At this time, the capsule 3 formed on the electrode pad 2 is enclosed by the solder bumps 12. Thus, the semiconductor device 70 is completed through the steps shown in FIGS. 6A to 6C described above.

  According to the semiconductor device 70 according to the first embodiment, the conductive material 5 that forms an alloy with Sn becomes a liquid at room temperature to 80.0 ° C., which is a normal operating temperature of electronic equipment. Therefore, a crack 13 is generated in the solder bump 12, and when the crack 13 destroys the capsule 3, the liquid conductive material 5 oozes into the crack 13. The conductive material 5 reacts with Sn contained in the solder bump 12 to form an alloy containing Sn. Since the crack 13 is filled with an alloy containing Sn, an increase in the electrical resistance of the solder bump 12 accompanying the generation of the crack 13 can be suppressed.

  In the second embodiment of the present invention, FIGS. 7 to 14 illustrate the semiconductor device 72 and the method of manufacturing the semiconductor device 72 in detail.

  FIG. 7 shows an electrode structure 61 of a semiconductor package provided in the semiconductor device 72. FIG. 7A is a plan view of the electrode structure 61 of the semiconductor package. FIG. 7B is a cross-sectional view taken along line XY of FIG. 7A. In addition, the same code | symbol is attached | subjected to the structure similar to the structure demonstrated with the electrode structure 50 shown to FIG. 1A and FIG. 1B, and the electrode structure 60 of the semiconductor package shown to FIG. 5A, and description is abbreviate | omitted.

7A and 7B show the semiconductor package 10, the electrode structure 61 of the semiconductor package, and the insulating coating layer 15. FIG.
Similar to the semiconductor package 10 shown in FIG. 5A, the semiconductor package 10 is obtained by mounting a semiconductor element on the package.
The electrode structure 61 of the semiconductor package includes an electrode pad 11, a capsule 3, and an adhesive 4. As shown in FIGS. 7A and 7B, the electrode structure 61 of the semiconductor package is provided on the semiconductor package 10.
The electrode pad 11 is provided on the semiconductor package 10 similarly to the electrode pad 11 shown in FIG. 5A.
The electrode pad 11 is formed with a recess 8 as in the electrode pad 2 shown in FIGS. 1A and 1B. As shown in FIG. 11B described later, the recess 8 is formed in order to ensure that the capsule 3 is fixed on the electrode pad 11. This is for ensuring that the capsule 3 is destroyed by the crack 13 when the crack 13 is generated in the vicinity of the surface of the electrode pad 11 in the solder bump 12 as shown in FIG.
Similar to the electrode structure 50 shown in FIGS. 1A and 1B, the capsule 3 includes a conductive material 5 and an outer shell 6. Similar to the electrode structure 50 shown in FIGS. 1A and 1B, when the diameter of the electrode pad 11 is, for example, 600 μm, the capsule 3 is preferably disposed at a position of, for example, 0 μm to 200 μm from the center of the electrode pad 11. .
The conductive material 5 includes, for example, a material having a melting point of 15.7 ° C. to 80.0 ° C. and forming an alloy with Sn (tin), like the electrode structure 50 shown in FIGS. 1A and 1B. desirable.
Similar to the electrode structure 50 shown in FIGS. 1A and 1B, the outer shell 6 is formed so as to contain the conductive material 5.
The adhesive 4 is formed on the depression 8 formed on the electrode pad 11 in the same manner as the electrode structure 50 shown in FIGS. 1A and 1B. The adhesive 4 is formed to bond the capsule 3 on the electrode pad 11.
The insulating coating layer 15 is formed so as to cover the semiconductor package 10 and the outer periphery of the electrode pad 11 in the same manner as the insulating coating layer 15 shown in FIG. 5A.

  8 to 10 are diagrams illustrating manufacturing steps of the electrode structure 61 of the semiconductor package according to the second embodiment. In the manufacturing method, the same reference numerals are given to the same configurations as those described in the manufacturing process of the electrode structure 50 shown in FIGS. 2 to 4 and the electrode structure 61 of the semiconductor package shown in FIGS. 7A and 7B. The description is omitted.

  FIG. 8A is a diagram showing the preparation of the conductive material 5 as in FIG. 2A.

  FIG. 8B is a diagram illustrating the preparation of the outer shell 6 as in FIG. 2B.

  FIG. 8C is a diagram showing the conductive material 5 arranged in the outer shell 6 as in FIG. 2C.

  FIG. 8D is a diagram illustrating processing of the outer shell 6 in which the conductive material 5 is disposed, similarly to FIG. 2D.

  FIG. 9A is a diagram showing how the semiconductor package 10 including the electrode pads 11 and the insulating coating layer 15 is prepared.

  FIG. 9B is a diagram showing the formation of the resist layer 7 so as to cover the electrode pads 11 provided on the semiconductor package 10. As shown in FIG. 9B, the resist layer 7 is formed so as to cover the electrode pads 11 on the semiconductor package 10 by a method similar to the method shown in FIG. 3B. Next, an opening 7a of the resist layer 7 having a diameter of 40 μm to 45 μm is formed on the electrode pad 11 by a method similar to the method shown in FIG. 3B. A part of the electrode pad 11 is exposed through the opening 7 a of the resist layer 7.

  FIG. 9C is a diagram showing how the recess 8 is formed in the electrode pad 11. As shown in FIG. 9C, the electrode pad 11 exposed through the opening 7a of the resist layer 7 is etched by a method similar to the method shown in FIG. 3C. By etching the electrode pad 11, a recess 8 having a diameter of, for example, 40 μm to 45 μm and a depth of 5 μm to 10 μm is formed in the electrode pad 11. After the depression 8 is formed in the electrode pad 11, the resist layer 7 is removed from the semiconductor package 10.

  FIG. 9D is a diagram showing how the adhesive 4 is formed on the depression 8 formed in the electrode pad 11. As shown in FIG. 9D, the adhesive 4 is formed on the depression 8 by the same construction method as that shown in FIG. 3D.

FIG. 10A is a diagram showing how the capsule 3 is arranged on the adhesive 4 formed on the recess 8. FIG. 10B is a cross-sectional view taken along line XY of FIG. 10A.
As shown in FIGS. 10A and 10B, the capsule 3 is disposed on the adhesive 4 formed on the recess 8 using, for example, a jig (not shown). After the capsule 3 is formed on the adhesive 4, the adhesive 4 interposed between the capsule 3 and the electrode pad 11 is cured, and the capsule 3 is bonded onto the electrode pad 11. Thus, the electrode structure 61 of the semiconductor package is formed by obtaining the steps shown in FIGS. 8A to 10B described above.

FIG. 11A is a diagram illustrating the semiconductor device 72 according to the second embodiment. The semiconductor device 72 includes an electrode structure 50 and solder bumps 12 in addition to the electrode structure 61 of the semiconductor package illustrated in FIG. 10B. Note that the same components as those shown in FIGS. 1A, 1B, 5A, 7A, and 7B are denoted by the same reference numerals, and description thereof is omitted.
The solder bumps 12 are adhesive members that electrically connect the electrode pads 2 on the circuit board 1 and the electrode pads 11 on the semiconductor package 10. The solder bumps 12 are formed with a diameter of 600 μm, for example, like the solder bumps 12 shown in FIG. 5A. The solder bumps 12 are similar to the solder bumps 12 shown in FIG. 5A, for example, Sn—Pb (lead) alloy, Sn—Bi (bismuth) alloy, Sn—In alloy, Sn—Zn (zinc) alloy. It is desirable to contain a Sn-Ag (silver) alloy, a Sn-Ag-Cu (copper) alloy, or a Sn-Cu alloy. The solder bump 12 is formed so as to enclose the capsule 3 on the electrode pad 2 and the capsule 3 on the electrode pad 11.

FIG. 11B is a diagram showing a semiconductor device 73 in which the electrode structure 50 and the electrode structure 61 of the semiconductor package are electrically connected by the solder bump 12 including the crack 13 inside.
First, as shown in FIG. 11B, a description will be given of how the cracks 13 are generated in the solder bumps 12 related to the semiconductor device 73. When an electronic device (not shown) on which the semiconductor device 73 is mounted operates, when the electronic device shifts from a low load state to a high load state, the operating temperature of the electronic device is normally set as in the semiconductor device 71 shown in FIG. 5B. The operating temperature of the electronic device increases to the operating temperature of the electronic device in a high load state, and the circuit board 1 in the electrode structure 50 and the semiconductor package 10 in the electrode structure 61 of the semiconductor package thermally expand. Taking a ceramic package and a glass epoxy substrate as an example, the circuit substrate 1 has a larger thermal expansion coefficient than the semiconductor package 10. Therefore, the thermal expansion amount of the circuit board 1 is increased, and the thermal expansion amount of the semiconductor package 10 is decreased. As a result, stress is generated in the solder bumps 12 interposed between the circuit board 1 and the semiconductor package 10.

  When the high load state and the low load state of the electronic device are repeated, the expansion and contraction of the circuit board 1 is repeated, so that stress is repeatedly generated in the solder bumps 12. When stress is repeatedly generated in the solder bumps 12, the solder bumps 12 are subjected to metal fatigue and cracks 13 are generated. The generated crack 13 grows at the interface between the solder bump 12 and the electrode pad 11. When the crack 13 occurs in the solder bump 12, the conductive area between the circuit board 1 and the semiconductor package 10 in the solder bump 12 decreases, and thus the electrical resistance in the solder bump 12 increases. When the crack 13 further progresses, the electrical connection is completely broken, and the solder bump 12 is disconnected. Therefore, there arises a problem that the mounting reliability in the semiconductor package 10 and the circuit board 1 is lowered.

  As shown in FIG. 11B, when the crack 13 occurs in the solder bump 12, the capsule 3 containing the conductive material 5 is destroyed by the crack 13, as in the semiconductor device 71 shown in FIG. 5B. The conductive substance 5 has a property of becoming a liquid in a range from room temperature to 80 ° C., which is the use environment temperature of the electronic device. Therefore, the conductive material 5 that is a liquid oozes into the crack 13. Since the exuded conductive material 5 contains Ga, it reacts with Sn contained in the solder bump 12 to form a Ga—Sn alloy 14. Since the Ga—Sn alloy 14 has conductivity, an increase in the electrical resistance of the solder bump 12 due to the generation of the crack 13 can be suppressed.

  FIG. 12 illustrates a method for manufacturing the semiconductor device 72 according to the second embodiment. In the manufacturing method, the same components as those described in the semiconductor device 70 shown in FIG. 5A, the manufacturing method of the semiconductor device 70 shown in FIG. 6, and the semiconductor device 72 shown in FIG. Description is omitted.

  FIG. 12A is a diagram illustrating the preparation of the electrode structure 50 as in FIG. 6A.

FIG. 12B is a diagram showing the preparation of the semiconductor package 10, the electrode pad 11, the electrode structure 61 of the semiconductor package having the insulating coating layer 15, and the solder bump 12.
As shown in FIG. 12B, first, solder plating printing (not shown) is performed on the electrode pads 11 of the semiconductor package 10 using a metal mask (not shown). Next, solder bumps 12 are formed on the electrode pads 11 by aggregating the solder plating on the electrode pads 11 due to the surface tension of the melted solder plating, for example, by a heating process using a reflow method. The solder bump 12 is formed so as to enclose the capsule 3 on the electrode pad 11 in the semiconductor package 10. Next, the solder bumps 12 formed on the electrode pads 11 of the semiconductor package 10 are arranged so as to face the electrode pads 2 on the circuit board 1. At this time, it is desirable to apply a flux (not shown) so as to cover the electrode pads 2 on the circuit board 1.

FIG. 12C is a diagram showing heat treatment with the electrode pads 2 on the circuit board 1 and the solder bumps 12 formed on the electrode pads 11 of the semiconductor package 10 facing each other.
As shown in FIG. 12C, the electrode structure 61 of the semiconductor package is connected to the electrode pads 2 on the circuit board 1 by heating and melting the solder bumps 12 on the electrode pads 11 by a reflow process (not shown). Is done. At this time, the capsule 3 formed on the electrode pad 2 is enclosed by the solder bumps 12. Thus, the semiconductor device 72 is completed through the steps shown in FIGS. 12A to 12C described above.

  According to the semiconductor device 72 according to the second embodiment, in addition to the semiconductor device 70 according to the first embodiment, the capsule 3 including the conductive material 5 is formed in the electrode structure 61 of the semiconductor package. Therefore, even when the crack 13 is generated in the solder bump 12 near the electrode pad 11, the crack 13 is filled with an alloy containing Sn, so that an increase in the electrical resistance of the solder bump 12 due to the generation of the crack 13 is suppressed. can do.

DESCRIPTION OF SYMBOLS 1 Circuit board 2 Electrode pad 3 Capsule 4 Adhesive 5 Conductive substance 6 Outer shell 7 Resist layer 7a Opening 8 Depression 10 Semiconductor package 11 Electrode pad 12 Solder bump 13 Crack 14 Ga-Sn alloy 15 Insulating coating layer 50 Electrode structure 60 Electrode structure of semiconductor package 61 Electrode structure of semiconductor package 70 Semiconductor device 71 Semiconductor device 72 Semiconductor device 73 Semiconductor device

Claims (3)

A first substrate constituting an electronic device ;
A first electrode formed on the first substrate;
A first conductive material that becomes liquid at the operating temperature of the electronic device and forms an alloy with Sn (tin);
A first capsule provided on the first electrode and including the first conductive material therein;
A solder bump covering the first capsule and containing Sn;
A circuit board comprising: The circuit board according to claim 1, wherein the first capsule is broken by a crack generated in the solder bump . The circuit board according to claim 1, wherein the first conductive material includes Ga (gallium) and In (indium), or Ga and Sn.