JPH11242506A - Programmable controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce retransmission time by adjustment of data transmission priority in a bus connection system and to shorten data transmission time. SOLUTION: The programmable controller records the priority, the bus occupation time and the tolerable waiting time of its own master and the priority and the data transmission processing remaining time of a master operating as a master at present in the registers of the respective masters. At the time of transmitting data based on them, it is decided whether a processing is to be executed after the termination of the data transmission of the present master is waited for or the processing is to be executed after the data transmission of the present master is stopped.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a programmable controller, and more particularly to control of a bus use right of a plurality of masters in a bus connection system.

[0002]

2. Description of the Related Art In a programmable controller using a bus connection method, control of a bus use right of a plurality of masters is performed, for example, by a master A during data transmission processing and a master B requesting transmission processing. , B according to the "priority" which determines in principle which should be processed first, if the higher priority master A is performing data transmission processing, as shown in FIG. A keeps the right to use the bus and continues the data transmission process, and the newly requested master B waits until the data transmission process is completed to acquire the right to use the bus. Is in the data transmission process, as shown in FIG. 10B, the master A stops the data transmission process and releases the right to use the bus, and the newly requested master B acquires the right to use the bus. Data Performs transmission processing, the master A data transmission processing after the completion of the master B was performed control of the bus use right determines only the priority of each master and so, again performing data transmission processing.

[0003]

Therefore, when one master A requests a bus use right from the master B having a higher priority while the master A is performing data transmission processing by the bus, the master A during the data transmission processing becomes: For example, even immediately before the end of the data transmission process, the data transmission process is stopped, and after the data transmission process of the master B having a higher priority is completed, the data transmission process is restarted from the beginning.
As shown in (b), the processing time wasted L.

[0004] In addition, if a failure occurs in the master during data transmission processing and a signal indicating the end of the data transmission processing cannot be output, it is also difficult to release the right to use the bus.

An object of the present invention is to provide a programmable controller which solves the above-mentioned problems, reduces processing time due to retransmission of data, and increases the reliability of the programmable controller against a master failure.

[0006]

SUMMARY OF THE INVENTION In order to achieve the above-mentioned object, a first aspect of the present invention is a programmable controller in which a bus controller controls a bus use right of a plurality of bus-coupled masters. , Bus occupation time, allowable waiting time, at least two types of information, the priority of the current master currently operating as the master,
Based on the information on the remaining time of the data transmission processing, when the data transmission processing of the next master not currently operating as the master becomes possible, the data transmission processing of the current master is continued, or the data transmission of the current master is performed. It is characterized in that it is determined whether to stop the processing and switch to the data transmission processing of the next master.

According to a second aspect of the present invention, in the first aspect of the invention, the above-mentioned determination is made by comparing the priority of the current master and the remaining time of the data transmission processing with the priority and the allowable waiting time of the next master, respectively. It is characterized by performing.

According to a third aspect of the present invention, in the second aspect, the priority of the next master is higher than the priority of the current master, and the allowable waiting time of the next master is longer than the remaining time of data transmission processing of the current master. When the value is also smaller, the data transmission processing of the current master is stopped and the processing is switched to the data transmission processing of the next master.

According to a fourth aspect of the present invention, in the first aspect of the present invention, when the information on the elapsed time of the remaining data transmission processing of the current master is not sent and the remaining time of the data transmission processing does not decrease, the right to use the bus is stopped. Is transferred to the next master.

According to a fifth aspect of the present invention, in a programmable controller in which a bus controller controls a bus use right of a plurality of bus-coupled masters, a register of each master stores a priority, a bus occupation time, and an allowable waiting time of the master. Of the information, at least two types of information, the priority of the current master currently operating as the master, and information on the remaining time of the data transmission process are recorded. Based on the plurality of pieces of information, the master transmits a bus use right request signal. Is transmitted to the bus controller, and when the master becomes the current master upon receiving a bus use right grant signal from the bus controller, the priority of the current master and the bus occupation time are sent to other masters.

According to a sixth aspect of the present invention, in a programmable controller in which a bus controller controls a bus use right of a plurality of bus-coupled masters, the bus controller receiving a bus use right request signal from the plurality of masters comprises:
The bus use right acquisition order is determined for the plurality of masters that have issued the bus use right request signal in descending order of the allowable waiting time of the plurality of masters that have issued the bus use right request signal.

According to a seventh aspect of the present invention, in the fifth aspect of the invention, the bus use right acquisition order is further determined in the descending order of the priority of a plurality of masters that have issued the bus use right request signal. Features.

According to an eighth aspect of the present invention, in the fifth aspect of the present invention, the bus use right acquisition order is further determined in ascending order of the bus occupation time of the plurality of masters that issued the bus use right request signal. It is characterized by.

The "priority" in the present invention means a priority order in principle between masters when performing transmission processing of masters. The “bus occupation time” is the time during which the master occupies the bus for data transmission processing, and substantially corresponds to the net required time for data transmission processing.

The "permissible wait time" is a time during which the master can suspend data transmission processing and wait. The actual allowable waiting time is the time when the data transmission processing is not finished and the time when the next processing is hindered is reversed by the bus occupation time for the data transmission processing,
This is the difference from the current time. Therefore, the actual allowable waiting time decreases as the time elapses while waiting. Therefore, when recording the “allowable waiting time” in the register, the following 2
Perform one of the following processes. That is, when it becomes possible to perform data transmission processing, the actual permissible waiting time, which is decreasing, is used as the "permissible waiting time" in the register and compared with the remaining data transmission processing time of the current master. Then, when actually moving to the data transmission process,
Either return to the initial value for the next data transmission process, or keep the "Allowable wait time" in the register at the initial value and wait for the allowable wait time copied to the work area , And using this value to compare with the data transfer processing remaining time of the current master.

The "next master" means a master that is to perform data transmission processing next to the current master.

[0017]

Embodiments of the present invention will be described below.
This will be described with reference to the drawings.

FIG. 1 is an explanatory diagram for explaining a bus use right acquisition condition of each master according to an embodiment of the present invention. In FIG. 1, master A is currently performing data transmission processing.
And two masters A and B which are ready to transmit and want to transmit.

In the example of FIG. 1, the priority Pa of the master A is
If the priority is higher than or equal to the priority Pb of the master B, regardless of the magnitude relation between the remaining data transmission processing time Ta of the master A currently performing data transmission processing and the allowable waiting time WTb of the master B to be transmitted from now on, Without changing the bus use right, the master A continues the data transmission
After the data transmission process of the master A is completed, the data transfer process is executed by transferring the right to use the bus. This is the same as the bus use right control in the conventional programmable controller.

When the priority Pa of the master A is lower than the priority Pb of the master B, the relationship between the data transmission processing remaining time Ta of the master A and the allowable waiting time WTb of the master B is
When Ta ≦ WTb, the data transmission processing of the master A having a relatively small remaining time is continued, and only when Ta> WTb, the bus use right is transferred from the master A to the master B, and the data transmission processing of the master A is performed. Is stopped, and the data transmission process of the master B is interrupted.

FIGS. 2 (a) and 2 (b) are timing charts each showing an example of a bus use right control state according to the embodiment of FIG. 1. FIG. 2 (a) shows the priority P of the master A.
a is lower than the priority Pb of the master B and the remaining data transmission processing time Ta of the master A when the master B is ready for transmission is the allowable waiting time WT of the master B at that time.
It shows the state of the bus use right control when it is smaller than b. That is, in this case, since the remaining data transmission time Ta of the master A is relatively small and the master B is in a state of waiting, the remaining data transmission processing of the master A is continued, and when the processing is completed, Immediately, the master B performs data transmission processing. On the other hand, in the conventional bus right control, as shown in FIG. 2C, as soon as the master B having the higher priority can transmit, the data transmission process of the master A is stopped and the master B is stopped. After the data transmission processing of the master B is completed,
The data transmission process of the master A is performed again from the beginning. FIG.
As is clear from comparison between FIG. 2A and FIG. 2C, in the case of FIG. 2A of the present invention, the conventional FIG.
The processing time can be saved by Ts as compared with the case (c).

FIG. 2B is similar to FIG. 2A.
The data when the priority Pa of the master A is lower than the priority Pb of the master B, the data transmission processing remaining time Ta of the master A is longer than the allowable waiting time WTb of the master B at that time, and the master B cannot wait. Indicates the order of transmission processing. In this case, as in the conventional case, the data transmission process of the master A is stopped, the data transmission process of the master B is terminated, and then the data transmission process of the master A is performed again from the beginning. Although there is a waste of data retransmission, the time until cancellation is short, so that relatively little waste time is required.

FIG. 3 is a block diagram showing an embodiment of the present invention.

In FIG. 3, a bus 1 is connected to a plurality of masters A, B,... And a bus controller 2, and a plurality of slaves such as memories and I / Os (not shown). A coupling type programmable controller is formed.

The bus 1 includes a bus use right request signal line Bus re, which connects the bus controller 2 and each of the masters A, B,.
q1, Bus req2, ‥‥, Bus use right grant signal line Bus grant
1, Bus grant 2} and commonly used lines such as an address line Ad and a data line Data commonly connected to each device of the bus controller 2, a plurality of masters A, B,. In addition, it comprises a data transmission processing remaining time write signal line CsSetCount and a priority write signal line CsSetPriority commonly connected to these devices. FIG. 4 shows the contents of the signal lines and the like of the bus 1 described above.

The bus controller 2 responds to the bus use right request signal of the bus use right request signal lines Bus req1, Bus req2, ‥‥ by using the bus use right grant signal lines Bus grant1, Bus grant.
A bus use right grant signal is output to grant2 ‥‥. In this embodiment, the bus use right can be given to only one master, and the bus use right grant signal has not been output yet, but the one that can receive the bus use right request signal and stand by can be provided. is there. The bus controller 2 is provided with a standby table 2T in order to determine the data transmission processing order of these standby masters. FIG.
Illustrates the contents of the standby table 2T.

Each master A, B,... Has a register Ra, Rb,.
Rb and ‥‥ are the priorities Pa, Pb and ‥ of the master, respectively.
Priority, a priority register SetPriorityMine for recording マ ス タ, a bus occupancy time T0a, T0b of the master, an occupancy time register SetCountMine for recording ‥‥, an allowable waiting time W of the master
Allowable waiting time register Se for recording Ta, WTb, ‥‥
A current master priority register SetPriority for recording tWaitCount and the priority Pa (or Pb, ‥‥) of the master currently operating as the master, and remaining data transmission processing times Ta and Tb of the current master currently operating as the master. ,
It consists of the remaining time register SetCount for recording ‥‥.

FIG. 6 shows the registers Ra and R described above.
The contents of b and ‥‥ are shown. That is, the contents of the priority register SetPriorityMine, the occupation time register SetCountMine, and the allowable waiting time register SetWaitCount are different for each master. Current master priority register SetPriorit
As described later, y and the remaining time register SetCount always hold a common value for all masters.

When each of the masters A, B,... Has completed its internal processing and is ready for data transmission, the priority registers SetPriorityMine recorded in the registers Ra, Rb # of the masters A, B,. Time register SetC
When the master determines that it is appropriate to request the bus use right based on the values of ountMine, the allowable wait time register SetWaitCount, the current master priority register SetPriority and the remaining time register SetCount, the master sends the bus use right request signal to the bus. The request is sent to the bus controller 2 via the bus request signal line Bus req, and the bus controller 2 waits for the status of another master, for example, when another master has already issued a bus use right request signal and waited for a bus use right grant signal. If there is no problem, the bus use right grant signal is sent to the bus use permission signal line Bus gran
via t to the master that issued the bus right request signal.

The master that has received the bus use right grant signal immediately notifies the other masters of the priority register SetPriorit.
The priority of its own master recorded in yMine and the data transmission processing time of its own master recorded in the occupation time register SetCountMine are sent to notify the priority of the active master and the data transmission processing time. The priority of the active master is stored in the “Current Master Priority Register Se” of all other masters.
tPriority ", and the data transmission processing time is written into the" remaining time register SetCount "of all other masters, and is used as the data transmission processing remaining time.
Although the priority of the active current master does not change, the remaining time of the data transmission process decreases as the data transmission process progresses. Therefore, as the data transmission process progresses, the operating master notifies the other masters of the remaining time of the data transmission process timely in a timely manner.
tCount ”.

Next, the processing flow when the programmable controller of the bus connection system described in FIG. 3 performs the data transmission processing in accordance with the bus use right control algorithm shown in FIG. 1 will be described with reference to FIGS. 7 and 8. explain. FIG.
Is a flowchart showing the processing flow of the masters A, B, and 、. FIG. 8 is a flowchart showing the processing flow of the bus controller 2, and the masters A, B, and ‥‥ and the bus controller 2 respond to each other's processing results. Processing proceeds.

First, among the masters A, B,..., For example, the master N proceeds with the processing related to the register Rn according to the flow of FIG. In step 701,
After the processing in the master is completed, it is checked whether or not the resulting data can be transmitted using the bus. When data can be transmitted (yes), the process proceeds to step 702, where the priority register SetPri of the register Rn of the master is set.
The own priority Pn recorded in orityMine, the allowable wait time WTn recorded in the allowable wait time register SetWaitCount, and the allowable error count WECn are copied to the work area. The allowable error count WECn is a constant used for transferring the bus use right to the next master when a failure occurs in the active current master and the remaining time of the data transmission processing does not decrease, and differs for each master. You can also set a value.

In the next step 703, the error counter EC is cleared to zero. The error counter EC is a counter that is added when the remaining time of the data transmission processing does not decrease.

At step 704, the data transmission processing remaining time Tm of the work area is copied to the previous remaining time TOm.

Next, in step 705, the data transmission processing remaining time Tm recorded in the remaining time register SetCount is overwritten on the work area and copied. The data transmission processing remaining time Tm of the work area is, as described later,
It decreases every moment as the data transmission process progresses.

In the next step 706, it is checked whether or not the data transmission processing remaining time Tm is zero. If it is 0 (yes), it indicates that the data transmission process is not currently being performed and the bus is in an idle state, so that the master N sends a bus use right request signal Bus req n to the bus controller 2. Proceed directly to 715. Conversely, if it is not 0 (no), since the data transmission process is currently being performed, the data transmission process is suspended, and the current data transmission process is continued or the current data transmission process is stopped. Then, the process proceeds to step 707 and subsequent steps for determining whether to interrupt the data transmission process by itself.

In step 707, the remaining time Tm is compared with the previous remaining time TOm, and if they do not match (no),
Since the data transmission process of the current master is proceeding more normally than the previous time, the process proceeds to step 708, where the error counter EC is cleared to 0, and the process proceeds to step 711.

If it is determined in step 707 that Tm = TOm (yes), the process proceeds to step 709, where the error counter EC is incremented by one. In the next step 710, the value of the error counter EC and the allowable error are set. The number of times WECn is compared.

In step 710, EC> WECn
If (yes), since the number of cycles in which the remaining time Tm does not decrease exceeds the allowable number, the processing of the current master M is terminated, and the master N sends the bus use right request signal Bus req n to the bus controller 2. Proceed to step 715 for sending. In step 710, EC> WEC is still
If n is not reached (no), the process proceeds to step 711. In addition, after step 712 to be described later, a repetition cycle of steps 704 to 707 is entered, and Tm ≠ T
If it becomes Om, it means that the processing of the current master M has been continued, and the error counter E
C is set to 0.

In step 711, the priority Pm currently being transmitted is copied from the current master priority register SetPriority to the work area. In the next step 712, the priority Pm during the current data transmission process is compared with the own priority Pn copied earlier, and if Pm <Pn (yes), the process proceeds to the next step 713. Pm ≧ Pn (n
If o), the process returns to step 704 to copy the previously read remaining time Tm to the last remaining time TOm, and proceeds to the subsequent step. When the condition of step 706 or step 710 is satisfied, the process proceeds to step 715.

In step 713, the data transmission processing remaining time Tm currently being processed for data transmission is copied from the remaining time register SetCount to the work area again. Then, in the next step 714, the remaining time Tm is compared with its own allowable waiting time WTn copied earlier. If Tm> WTn (yes), the process goes to step 715 in order to issue a bus request request signal Bus req, since the data transmission process cannot wait. If Tm ≦ WTn (no), the process returns to step 713 via step 716 because it is ready to wait. In step 716, the allowable waiting time WTn copied to the work area is corrected by the elapsed time. That is, the difference between the time when the previous step 713 is reached and the time when the current step 713 is reached is subtracted from the allowable waiting time WTn, and the value of the allowable waiting time WTn is reduced.

If the current master fails and the elapsed time information of the remaining time Tm is not sent and the remaining time Tm does not decrease, if Pm ≧ Pn, then at step 710, Pm <Pn, then Tm> W
In step 714, the process proceeds to step 715, and the bus use right is transferred from the current master to the next master, regardless of the failure of the current master, and the processing of the programmable controller is advanced.

When the processing reaches step 715, the bus use right request signal Bus req n may be issued as long as it is determined from the register information of the master N. Therefore, the processing after step 715 proceeds according to the control of the bus controller 2.

First, at step 715, a bus use right request signal Bus req n is issued to the bus controller 2. In the bus controller 2, as will be described later in detail with reference to FIG. 8, a bus request request signal Bus req n sent from all masters, a bus request In consideration of data transmission processing, a Bus grant n signal is issued to the master, so that the next step 717 reads this Bus grant n signal. If there is a Bus grant n signal in step 718 (yes), the data transmission process starting from step 719 is started. If no Busgrant n signal is present (n
o), returning to step 717 to repeatedly read the Bus grant n signal and wait for the Bus grant n signal.

Upon starting the transmission process in response to the Bus grant n signal data, in step 719, its own priority Pn is sent to the registers Ra, Rb # of all masters, and is written to the current master priority register SetPriority. Let

Subsequently, at step 720, the own bus occupation time T0n is sent to all the master registers Ra, Rb #, and the remaining time Tn is set as the remaining time Tn.
Make ount write. These priorities Pn and remaining time T
n is used in the above-described process from step 702 to step 715 when each master has completed its internal processing and is ready for data transmission.
As will be understood from the following description, the remaining time Tn is rewritten and decreases with the progress of the data transmission process.

After step 720, the process proceeds to step 721. In this step 721, it is determined whether or not the data transmission processing has ended (the end is the remaining time Tn = 0). If the processing has ended (yes), the flow of FIG. 7 is completed. When the process goes through this step 721 for the first time, the data transmission process is usually not completed (no), so the next step 7
Proceeding to 22, the data transmission process is performed in an appropriate unit amount.

During the data transmission process, another master may require a more urgent data transmission, and the bus controller 2 may attempt to transfer the right to use the bus to the urgent master. Accordingly, in step 722, the process proceeds to step 723 without reading all the data transmission at once, and again reads the Bus grant n signal. In the next step 724, it is determined whether or not the Bus grant n signal for itself is maintained. Find out. If yes (yes), step 720
Then, the remaining time is written to the remaining time register SetCount of the registers R of all masters. If the remaining time is not 0 in step 721, the data transmission process is continued in step 722.

In step 724, if the Bus grant n signal has been cleared (no), the data transmission process is stopped and the right to use the bus is usually handed over to another master. As processing, in step 725, the priority Pn of the master N and the bus occupation time T0
n and the allowable waiting time WTn in the priority register S, respectively.
etPriorityMine, occupancy time register SetCountMine, allowable wait time register SetWaitCount, read out and send to bus controller 2, wait table 2T described later
, And then the flow of FIG. 7 is completed.

Step 7 in the flowchart of FIG.
The subtraction of the allowable waiting time with the passage of time in 16 is performed in the work area, but the allowable waiting time register SetWaitC
The value of “unt” may be directly subtracted and returned to the initial value after step 715.

The algorithm up to step 715 can be modified in other ways, for example, using information on the bus occupation time, the allowable waiting time, the priority of the current master, and the remaining time of the data transmission process. Alternatively, it is possible to use information on the priority, the bus occupation time, the priority of the current master, and the remaining time of the data transmission process.

Next, a processing flow of the bus controller 2 corresponding to the above processing flow of the master will be described with reference to FIG.

The bus controller 2 starts the flow from step 801 in a predetermined cycle. Step 8
In step 01, the bus use right request signal lines of all masters are checked sequentially, and in the next step 802, it is determined whether or not there are bus use right request signals Bus req 1, Busreq 2,. If no (no), this flow is completed, but if there is at least one (yes), the process moves to step 803, and the priority register SetPrior is set from the registers R of all masters that have issued the bus request signal Bus req.
Priority P, occupation time register recorded in ityMine
The bus occupation time T0 recorded in SetCountMine and the allowable wait time WT recorded in the allowable wait time register SetWaitCount are read, and the standby table 2T is set for each master.
Will be added to. Note that the acceptable waiting time decreases with time while waiting,
It is preferable that the allowable waiting time WT of the waiting table 2T is also subtracted as time elapses.

Next, in step 804, the order of data transmission processing is determined on the standby table 2T from the priority P, the bus occupation time T0n, and the allowable wait time WT. For example, the masters in the standby table 2T are sorted in ascending order of waiting time WT, in descending order of priority P, and finally in order of decreasing bus occupation time T0.
The data transmission processing order is from the top of the sorting result. Note that this ranking can be variously modified, and the waiting time WT
The same waiting time WT
If there is any, the request may be processed in the detection order of the bus use right request signal Bus req, and the bus request signal may be processed in the order of higher priority P, or the bus occupation time T
You may rank them in ascending order of 0.

Next, at step 805, the bus use right grant signal lines of all masters are sequentially examined, and at the next step 806, the bus use right grant signals Bus grant1, Bus gr
It is determined whether there is ant2, ‥‥. If there is no bus use right grant signal on any of the bus use right grant signal lines (no), the process proceeds to step 807 and the standby table 2
A bus use right grant signal Bus grant n1 is output to the bus use right grant signal line of the highest priority master n1 in T,
At the same time, the master n1 in the standby table 2T is deleted, and the flow of FIG. 8 is completed.

In step 806, if there is any bus use right grant signal Bus grant m (yes)
s), release the right to use the bus of this master M, and
Since the bus use right has to be granted to the master 1, the process goes to step 808 to clear the bus grant right signal Bus grant m of the master M, and to execute the current master priority register of the registers R of all masters. SetPriorit
Clear y and set the remaining time register SetCount to 0.
After that, it moves to step 807.

The output of the bus use right grant signal Bus grant n1 in step 807 is detected by the master n1 in step 717 in FIG. 7 described above, and the master n1 starts data transmission processing.

The clearing of the current bus use right grant signal Bus grant m in the above step 808 is performed in the manner shown in FIG.
In step 723, the current master M detects
The master M stops the data transmission process.

According to the flow of FIGS. 7 and 8, the right to use the bus of the programmable controller is controlled.
The data transmission process of each master is efficiently advanced in accordance with the priority order with little retransmission. As is clear from the flowcharts of FIGS. 7 and 8, when the control is performed in this manner, the same operation and effect can be obtained not only when the number of masters described with reference to FIG. Demonstrate.

In the above-described embodiment, the bus controller 2 uses the standby table 2T to store the data for which the bus use right is requested. Is the bus request signal Bus re
In step 802, all of these bus use right request signals Bus req are read out, and in step 802, all the bus use right request signals Bus req are read out.
In step 4, the highest-priority master may be selected.

FIG. 9 shows a processing state different from that of FIG. 2, that is, a master B having a higher priority than the master A and a master B having a higher priority than the master B during the data transmission processing. 7 shows an example of a processing state in a case where C and C can sequentially transmit data.

FIG. 9A shows a processing state in the embodiment of the present invention, and FIG. 9B shows a conventional processing state. When master B becomes available for transmission, master A
9A, the remaining time Ta of the data transmission processing of the master A is smaller than the allowable waiting time WTb of the master B, and in FIG. 9A, the data transmission processing of the master A is performed. And master B
Is waiting in the meantime. In contrast, FIG.
Then, the data transmission process of the master A is stopped, and the data transmission process of the master B is performed.

In FIG. 9A, when the data transmission process of the master A is completed, the next master C is ready for data transmission, and the data transmission process of the master C having a higher priority than the master B is performed by the master B. Is performed prior to the data transmission processing. On the other hand, in FIG. 9B, the data transmission process of the master B is stopped and the data transmission process of the master C is performed.

In FIG. 9A, when the data transmission process of the master C is completed, the data transmission process of the master B is finally performed. The required time is the processing time of master A +
The processing time of the master C is equal to the processing time of the master B. In this case, there is no need for retransmission. On the other hand, in FIG. 9B, when the data transmission process of the master C is completed, the retransmission process of the master B having the next highest priority is performed.
Thereafter, retransmission processing of master A is performed.

As is apparent from FIG. 9, in the case of the present invention, the processing time is reduced by Ts as compared with the conventional case.

In the above-described embodiment, the priority of the master Pa, Pb,..., The bus occupation time T0a, T0b,. , WTb, ‥‥, the priority Pa (or Pb, ‥) of the master currently operating as the master.
Ii), the remaining data transmission processing time Ta, Tb, の of the master currently operating as the master is recorded, and the transfer of the bus use right is determined based on this. For example, the master that records these data in the bus controller and can perform the data transmission process immediately issues a bus use right request signal, and transmits the bus use right request signal and the data of the bus controller. Based on this, the right to use the bus may be controlled by a similar algorithm.

[0067]

As will be understood from the above description, according to the present invention, at least two types of information among the priority of each master, the bus occupation time, and the permissible waiting time, and the current operation of the master. Based on the priority of the current master and the information on the remaining time of the data transmission processing, when the data transmission processing of the next master not currently operating as the master becomes possible, whether to continue the data transmission processing of the current master Since the data transmission processing of the current master is stopped and it is determined whether to switch to the data transmission processing of the next master, useless processing stoppage and duplicate retransmission that occur in the case of bus right adjustment only based on the priority are performed. And the processing efficiency of the programmable controller can be improved.

In the register of each master, at least two kinds of information of the priority of the master, the bus occupation time, and the allowable waiting time, the priority of the current master currently operating as the master, and the data transmission processing. Record the remaining time information,
Based on these, the master sends a bus use right request signal to the bus controller, and when the master receives the bus use right grant signal from the bus controller, the other masters give their master priority and data transmission processing time. With this configuration, the master itself determines whether or not the bus use right request is appropriate, so that the burden on the bus controller, which tends to be complicated, is reduced, and the processing efficiency of the programmable controller is further improved.

In the case where some masters fail and stop the processing while securing the right to use the bus, the interruption of the transmission of the current master data transmission processing remaining time elapse information caused by the stop of the processing is described in the above data. If it is determined that the remaining time of the transmission processing will not decrease and the right to use the bus is transferred to the next master, the control of the right to use the bus can be continued, and the reliability of the programmable controller is improved.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram illustrating a bus use right acquisition condition of each master according to an embodiment of the present invention.

2 (a) and 2 (b) are timing charts each showing an example of a bus use right control state according to the embodiment of FIG. 1, and FIG. 2 (c) is a timing chart showing a conventional comparative example.

FIG. 3 is a block diagram showing one embodiment of the present invention.

FIG. 4 is an explanatory diagram for explaining the contents of signals on a bus in FIG. 3;

FIG. 5 is an explanatory diagram illustrating the contents of a standby table in FIG. 3;

FIG. 6 is an explanatory diagram illustrating the contents of a register in FIG. 3;

FIG. 7 is a flowchart showing a processing flow when the master of FIG. 3 performs the processing of the embodiment of FIG. 1;

FIG. 8 is a flowchart showing a processing flow when the bus controller of FIG. 3 performs the processing of the embodiment of FIG. 1;

9A is a timing chart showing an example of a bus use right control state according to the embodiment of FIG. 1, and FIG. 9B is a timing chart showing a conventional comparative example.

FIGS. 10A and 10B are timing charts showing processing states of a plurality of masters by the conventional bus use right control.

[Explanation of symbols]

 1 Bus 2 Bus controller 2T Standby table A, B, $ N Master Pa, Pb, $ Pn Priority Ra, Rb, $ Rn register T0a, T0b, $ T0n Bus occupation time Ta, Tb, $ ‥ Tn data transmission processing remaining time WTa, WTb, ‥‥ WTn allowable waiting time

Claims (8)

[Claims] 1. A programmable controller in which a bus controller controls a bus use right of a plurality of bus-coupled masters, wherein at least two kinds of information of a priority, a bus occupation time, and an allowable waiting time of each master, Based on the priority of the current master operating as the master and the information on the remaining time of the data transmission processing, when the data transmission processing of the next master not currently operating as the master becomes possible, the data transmission of the current master becomes possible. A programmable controller for determining whether to continue the process or to stop the data transfer process of the current master and switch to the data transfer process of the next master. 2. The programmable controller according to claim 1, wherein the determination is made by comparing the priority of the current master and the remaining time of the data transmission processing with the priority and the allowable waiting time of the next master, respectively. . 3. When the priority of the next master is higher than the priority of the current master and the allowable waiting time of the next master is shorter than the remaining time of the data transmission processing of the current master, the data transmission processing of the current master is stopped. 3. The programmable controller according to claim 2, wherein the control is switched to a data transmission process of a next master. 4. The bus mastership is transferred to the next master when the data transmission processing remaining time information of the current master is no longer sent and the data transmission processing remaining time does not decrease. The programmable controller as described. 5. A programmable controller in which a bus controller controls a bus use right of a plurality of bus-coupled masters, wherein at least two of the master's priority, bus occupation time, and allowable waiting time are stored in a register of each master. Type information, priority of the current master currently operating as the master, and information on the remaining time of the data transmission process are recorded. Based on the plurality of information, the master sends a bus use right request signal to the bus controller. A programmable controller, wherein when the master receives the bus use right grant signal from the bus controller and becomes the current master, the priority of the current master and the bus occupation time are sent to other masters. 6. A programmable controller in which a bus controller controls a bus use right of a plurality of bus-coupled masters, wherein the bus controller receiving a bus use right request signal from the plurality of masters issues the bus use right request signal. A programmable controller characterized in that a bus use right acquisition order is determined for a plurality of masters that have issued the bus use right request signal in ascending order of allowable wait time of the plurality of masters. 7. The programmable controller according to claim 5, wherein the bus use right acquisition order is further determined in descending order of priority of a plurality of masters that have issued the bus use right request signal. 8. The programmable controller according to claim 5, wherein said bus use right acquisition order is further determined in ascending order of bus occupation time of a plurality of masters which issued said bus use right request signal.