JPH11237450A - Circuit division atg partial circuit processing system, circuit division atg partial circuit processing method, and storage medium where circuit division atg partial circuit processing method is written - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce time required for test pattern generation processing. SOLUTION: A failure detection difficulty circuit judging means 7 for delaying failure information in a partial circuit and outputting it as a list when the number of failures within the partial circuit is larger than a specific value based on the partial circuit and failure information created by a partial circuit creation means 5 is provided. Further, a test pattern is created based on failure information other than that in the partial circuit that is outputted as a delay list from the failure detection difficulty circuit judging means 7 in an ATG means 10, then a test pattern is created based on the failure information in the partial circuit being outputted as the delay list, and failure detection processing is completed when the failure detection reaches a predetermined target failure detection rate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit division ATG sub-circuit for dividing a circuit into partial circuits and automatically generating a test pattern for detecting a failure based on the failure pattern in the divided partial circuit. About the method.

[0002]

2. Description of the Related Art ATG (Automatic Test Generation:
“Automatic test generation” is a method of defining a fault that may occur in a circuit and automatically generating a test pattern for detecting the defined fault using a program.

[0003] First, a random pattern for detecting a fault defined in a circuit is generated, and a fault simulation is performed for all faults defined in the circuit using the generated random pattern. .

[0004] Next, a random test pattern is generated so that a failure pattern detected by the failure simulation is adopted as a test pattern, and the detected failure is not subject to failure detection thereafter.

After the number of faults detected by random test pattern generation decreases, a test pattern is generated by ATG processing for automatically generating a test pattern while referring to the circuit configuration. Here, the detected fault is not set as a fault detection target thereafter.

Here, in generating the test pattern as described above, a target failure detection rate (to be described later) is set in advance, and the processing is terminated when the failure detection rate reaches the set value. There is a method in which a target failure detection rate is not set.

The above-described method of calculating the failure detection rate includes, for example, the following method.

(1) (Fault detection rate) = (Number of detected faults) / (Total number of faults) (2) (Fault detection rate) = (Number of detected faults) /
｛(Total number of faults) − (number of faults determined to be undetectable)｝ (3) (failure detection rate) = ｛(number of detected faults) +
(Number of failures determined to be undetectable)｝ / (total number of failures) Here, in the above-described ATG processing, it takes an enormous amount of time. Thus, there is a distributed processing as one of the methods for reducing the processing time.

The circuit division / dispersion processing ATG is one of the methods of performing the ATG processing in a distributed manner, and divides a circuit into several partial circuits and performs ATG for each of the divided partial circuits.

The division method of the partial circuits may be any division method as long as it allows each partial circuit to be processed independently (the order of processing can be changed arbitrarily).

For example, there is a method in which all output terminals are divided into several groups, and all elements related to one group of output terminals are formed as one partial circuit. However, in this method, elements that affect a plurality of output terminals may be included in a plurality of partial circuits redundantly. In this case, a fault defined in an input or output of an element that is included in a plurality of partial circuits redundantly will be included in a plurality of partial circuits redundantly.

Similarly, in other circuit division methods, a plurality of partial circuits may include the same fault redundantly. The number of partial circuits is divided so as to be larger than the number of CPUs used. The ATG processing of the partial circuit is assigned to a plurality of CPUs, and the ATG processing of the next partial circuit is assigned to the CPU that has completed the ATG processing.
G processing is assigned.

FIG. 6 is a block diagram showing one configuration example of a conventional circuit division ATG partial circuit processing system.

In this conventional example, as shown in FIG. 6, a random pattern is generated using random numbers, and the generated random pattern and all elements included in a circuit for performing ATG processing and information on connections between these elements are used. A failure simulation for detecting a failure in a circuit is performed based on certain input circuit information 1 and input failure information 2 which is information on a failure that can be defined in a circuit performing ATG processing. Based on the detected fault, a test pattern for detecting a fault in the circuit is generated, the generated test pattern is output as a pattern 12, and information on a fault not detected in the fault simulation is output as an undetected fault. Random test pattern generating means 3 for outputting as information 4 and input circuit information 1 Divides the circuit for performing ATG process,
In addition to generating a partial circuit, based on the generated partial circuit and the undetected fault information 4 output from the random test pattern generation means 3, fault information that can be detected by the partial circuit is generated. Automatically generating and generating a test pattern for detecting a fault in a circuit based on the partial circuit generating means 5 for outputting as the fault information 6 and the partial circuit information and the fault information 6 output from the partial circuit generating means 5 ATG means 10 for outputting the test pattern thus obtained as pattern 12 and outputting failure information not used for generating the test pattern as undetected failure information 4 or output undetected failure information 15; random test pattern generation means 3; A pattern merging unit 13 for merging the test pattern 12 generated by the ATG unit 10 and outputting it as an output pattern 14 Are al configuration. In addition, in the ATG means 10, when the failure detection rate does not reach the specified value, information on a failure not used for generating a test pattern is output as undetected failure information 4, and the failure detection rate is specified. When the value reaches the value, information on a fault not used for generating a test pattern is output as output undetected fault information 15.

The test pattern generation processing in the circuit division ATG partial circuit processing system configured as described above will be described below.

FIG. 7 is a flowchart for explaining a test pattern generation process in the circuit division ATG partial circuit processing system shown in FIG.

First, in the random test pattern generation means 2, a random pattern is generated using random numbers, and the generated random pattern and all faults which have not yet been detected among the faults stored as the input fault information 2 are generated. A failure simulation for detecting a failure using the information is performed, and a failure pattern detected by the failure simulation is adopted as a test pattern (step S101). Note that the detected fault is excluded from targets for subsequent pattern generation.

The processing in step S101 may be performed on the entire circuit before the partial circuit is created, or may be performed on each partial circuit after the partial circuit is created. In this conventional example, the process is performed on the entire circuit before the partial circuit is created. Also, in the random test pattern generation process, faults that are easy to detect tend to be detected, so how many faults can be detected by this method is an index of whether the circuit configuration of the circuit is easy to detect faults. Becomes

The test pattern generated in step S101 is output as a pattern 12, and the faults not detected in the fault simulation in step S101 are output as undetected fault information 4 to be used for generating the test pattern. Is done.

Next, in the partial circuit creating means 5, a circuit for performing ATG processing based on the input circuit information 1
U is divided into more than the number of U, thereby generating a partial circuit. On the basis of the generated partial circuit and the undetected fault information 4, fault information detectable by the partial circuit is generated. And failure information 6 (step S102).

In step S102, the partial circuit creating means 5
Is output to the ATG means 10 of the vacant CPU among the CPUs in the circuit, and the ATG means 10 outputs the partial circuit information and the failure information in the circuit based on the partial circuit information and the failure information 6. A test pattern for detecting a failure is automatically generated (Step S103).

The test pattern generated in step S103 is output as the pattern 12, and the faults not used for test pattern generation in step S103, that is, the faults not detected, are continuously used for test pattern generation. Is output as undetected failure information 4.

Thereafter, it is determined whether or not the fault detected in the above-described series of processes has a value that satisfies a preset target fault detection rate (step S).
104), if it is determined that the value satisfies the target failure detection rate, the pattern merge unit 13 merges the test patterns 12 generated by the random test pattern generation unit 3 and the ATG unit 10 and outputs the output pattern 14
At the same time, and information on a fault not used for generating a test pattern is output from the ATG means 10 as output undetected fault information 15 (step S).
105).

On the other hand, if it is determined in step S104 that the value does not satisfy the target failure detection rate,
It is determined whether the processing for all the partial circuits has been completed (step S106). If it is determined that the processing for all the partial circuits has been completed, step S105 is performed.
If it is determined that the processing has not been completed for all the partial circuits, the process proceeds to step S1.
The process returns to 02.

[0025]

Detecting a fault that is difficult to detect requires a great deal of time. For example,
In circuits with 1M gates, 1
While several hours are spent, several hours may be spent detecting one of the hard-to-detect faults.

Therefore, in the conventional circuit division ATG partial circuit processing method as described above, in the circuit,
When a fault that is difficult to detect exists locally, if a partial circuit having the fault is processed in the early order, if there is a fault that can be easily detected in a partial circuit that is processed later, There is a problem that the time required to detect an easily detectable failure is unnecessarily spent.

Even in the case where the target failure detection rate can be reached without detecting a failure that is difficult to detect, the processing for detecting those failures is performed. There is a problem that it takes more time than necessary to reach it.

The present invention has been made in view of the above-mentioned problems of the prior art, and provides a circuit division ATG partial circuit processing method capable of reducing the time spent for test pattern generation processing. The purpose is to do.

[0029]

In order to achieve the above object, the present invention provides a method for generating a random pattern using random numbers, detecting a fault in a circuit using the generated random pattern, and detecting the detected fault. A random test pattern generating means for generating a test pattern for detecting a fault in the circuit based on the above, and a partial circuit created by dividing the circuit, and fault information detectable by the created partial circuit. Means for automatically generating a test pattern for detecting a fault in a circuit based on the partial circuit and fault information created by the partial circuit creating means; Pattern generating means and pattern merge means for merging the test patterns generated by the ATG means and outputting them as output patterns. In the circuit division ATG partial circuit processing method, when the number of faults in the partial circuit is larger than a predetermined value based on the partial circuit and the fault information created by the partial circuit creating means, the fault information in the partial circuit is determined. Is output as a postponed list, and the ATG means outputs the test pattern based on the fault information other than the fault information in the partial circuit output as the postponed list from the fault detection difficult circuit judging means. After generating the test pattern, the test pattern is generated based on the failure information in the partial circuit output as the postponed list.

Further, the predetermined value is set based on a ratio of the number of faults detected by the random test pattern generation means to the number of faults defined in the entire circuit.

Further, there is provided a postponed list storing means for storing the fault information in the partial circuit outputted as the postponed list from the fault detection difficult circuit judging means.

After the test pattern is generated by the ATG means based on the failure information other than the failure information in the partial circuit output as the delay list from the failure detection difficult circuit determination means, the test pattern is generated as the delay list. It is characterized by having a failure detection difficult circuit processing means for extracting the output failure information of the partial circuit from the postponed list storage means and outputting it to the ATG means.

Further, the failure detection difficult circuit processing means comprises:
The fault information is output to the ATG means in order from the fault information of the partial circuit having a small number of faults among the partial circuits stored in the postponed list storage means.

The ATG means terminates the failure detection processing when the failure detection reaches a predetermined target failure detection rate.

Further, the partial circuit creating means divides the circuit into partial circuits equal to or more than the number of CPUs in the circuit.

A first process for detecting a fault in a circuit using a random pattern generated using random numbers and generating a test pattern for detecting a fault in the circuit based on the detected fault. And a second process of creating a partial circuit by dividing the circuit and generating fault information detectable by the created partial circuit; and a partial process and a fault created by the second process. A third process for automatically generating a test pattern for detecting a fault in a circuit based on the information, and the test patterns generated in the first and third processes are merged and output as an output pattern. In the circuit division ATG partial circuit processing method having the fourth process, the number of faults in the partial circuit is set to a value smaller than a predetermined value based on the partial circuit and the fault information created in the second process. A big place , A fifth process of outputting the failure information in the partial circuit as a deferred list, the third
After the test pattern is generated based on the failure information other than the failure information in the partial circuit output as the postponed list, the test pattern is generated based on the failure information in the partial circuit output as the postponed list. It is characterized by doing.

Further, the predetermined value is set based on a ratio of the number of faults detected by the random test pattern generation means to the number of faults defined in the entire circuit.

Further, the generation of the test pattern based on the failure information of the partial circuit output as the postponed list in the third processing is performed from a small number of failures in the partial circuit. .

Further, when the failure detection in the third processing reaches a predetermined target failure detection rate, the failure detection processing is terminated.

Further, the generation of the test pattern based on the failure information of the partial circuit output as the post-processing list in the third processing is performed by dividing the failure in the partial circuit into a plurality of blocks. And

Further, in the storage medium in which the processing program of the computer is written, the method of processing the circuit-divided ATG partial circuit is written.

(Operation) In the present invention configured as described above, the number of faults in the partial circuit is larger than a predetermined value based on the partial circuit and the fault information created by the partial circuit creating means. In this case, after the failure information in the partial circuit is output as a delay list, the ATG means generates a test pattern based on failure information other than the failure information in the partial circuit output as the delay list,
A test pattern is generated based on the failure information in the partial circuit output as the postponed list.

As described above, a partial circuit having a circuit configuration that is difficult to detect a failure is a postponed list, and the order of processing is postponed. As a result, if a fault that should have been processed by a partial circuit having a circuit configuration that is difficult to detect is also included in a partial circuit that has a circuit configuration that is easy to detect the fault, the fault detection is not performed. Processing is first performed in a partial circuit having an easy circuit configuration, and a failure is detected.

If the fault is detected first in a partial circuit having a circuit configuration that makes it easy to detect the fault, the fault once detected is excluded from the target of test pattern generation thereafter, so that it is postponed. In a difficult circuit having a circuit configuration in which failure detection is difficult, the processing is not performed, and the circuit division distributed ATG
As a whole, the processing time is shortened accordingly.

In the case where the target failure detection rate is smaller than 100%, if the target failure detection rate is achieved before performing the failure detection processing in the partial circuit having the circuit configuration in which the failure detection is difficult, a failure is detected. This eliminates the need to perform any fault detection processing in a partial circuit having a circuit configuration that is difficult to detect, and in that case, eliminates the processing time required for the fault detection processing in a partial circuit that has a circuit configuration that is difficult to detect. Can be. For example, assuming that the target failure detection rate is 95%, the remaining 5% includes a hard-to-detect fault, and the target fault detection is performed before performing a fault detection process in a partial circuit having a circuit configuration that is difficult to detect. If the rate is achieved, there is no need to perform a failure detection process in a partial circuit having a circuit configuration in which failure detection is difficult.

Normally, most faults are detected in random test pattern generation. The fault once detected is thereafter excluded from the target of test pattern generation. Therefore, after the random test pattern generation ends, most of the faults of the entire circuit are excluded from the target of test pattern generation. Further, in the random test pattern generation, a failure that is easy to detect tends to be detected because the generated pattern is a random pattern. Taking advantage of this,
After a certain amount of random test pattern generation, partial circuits that have many undetected faults remain are judged to have a circuit configuration that makes it difficult to detect faults, and are regarded as difficult to detect faulty partial circuits, and are postponed. Target.

[0047]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is a block diagram showing a first embodiment of a circuit division ATG partial circuit processing system according to the present invention.

In this embodiment, as shown in FIG. 1, a random pattern is generated by using a random number, and all the elements included in a circuit for performing the ATG processing with the generated random pattern and information on connections between those elements. Input circuit information 1 and A
A failure simulation for detecting a failure in the circuit is performed based on the input failure information 2 which is information on a failure that can be defined in the circuit performing the TG process, and based on the failure detected by the failure simulation. A test pattern for detecting a fault in the circuit, outputting the generated test pattern as a pattern 12, and outputting information on a fault not detected in the fault simulation as undetected fault information 4. The circuit for performing the ATG process is divided based on the test pattern generation means 3 and the input circuit information 1,
In addition to generating a partial circuit, based on the generated partial circuit and the undetected fault information 4 output from the random test pattern generation means 3, fault information that can be detected by the partial circuit is generated. Based on the partial circuit information output from the partial circuit generating means 5 and the fault information 6 when the number of faults in the partial circuit is larger than a predetermined value or When the value depends on the circuit information and the failure information 6,
The failure information in the partial circuit is output as a postponed list, and when the number of failures in the partial circuit is equal to or less than a predetermined value or when the value does not depend on the partial circuit information and the failure information 6, Failure detection circuit determination means 7 for outputting the failure information as it is, delay list storage means 8 for storing the delay list output from failure detection circuit determination means 7, and partial circuit information output from partial circuit creation means 5 And automatically generates a test pattern for detecting a fault in the circuit based on the fault information 6, outputs the generated test pattern as a pattern 12, and detects no fault information not used for generating the test pattern. ATG means 10 for outputting as failure information 4 or output undetected failure information 15 and later stored in list storage means 8 It is ATG means 10 the postponed list
And a pattern merger 13 that merges the test pattern 12 generated by the random test pattern generator 3 and the ATG 10 and outputs the output as an output pattern 14.
In addition, in the ATG means 10, when the failure detection rate does not reach the specified value, information on a failure not used for generating a test pattern is output as undetected failure information 4, and the failure detection rate is specified. When the value reaches the value, information on a fault not used for generating a test pattern is output as output undetected fault information 15. Also,
After the test pattern is automatically generated by the ATG means 10 based on the partial circuit information and the failure information 6 which are not output as the postponed list by the failure detection circuit determination means 7, the failure detection circuit processing means 9 If the detection rate has not reached the predetermined failure detection rate, the postponed list stored in the postponed list storage means 8 is output to the ATG means 10.

The test pattern generation processing in the circuit division ATG partial circuit processing system configured as described above will be described below.

FIG. 2 is a flowchart for explaining the test pattern generation processing in the circuit division ATG partial circuit processing system shown in FIG.

First, in the random test pattern generation means 2, a random pattern is generated using random numbers, and the generated random pattern and all faults which have not yet been detected among the faults stored as the input fault information 2 are generated. A failure simulation for detecting a failure is performed using the information and the failure pattern detected by the failure simulation is adopted as a test pattern (step S1). Note that the detected fault is excluded from targets for subsequent pattern generation.

The processing in step S1 may be performed on the entire circuit before the partial circuit is created, or may be performed on each partial circuit after the partial circuit is created. In the present embodiment, the process is performed on the entire circuit before the partial circuit is created. Also, in the random test pattern generation process, faults that are easy to detect tend to be detected, so how many faults can be detected by this method is an index of whether the circuit configuration of the circuit is easy to detect faults. Becomes

The test pattern generated in step S1 is output as a pattern 12, and the test pattern is output in step S1.
Are output as undetected fault information 4 because they are subsequently used for generating a test pattern.

Next, in the partial circuit creating means 5, a circuit for performing ATG processing based on the input circuit information 1
U is divided into more than the number of U, thereby generating a partial circuit. On the basis of the generated partial circuit and the undetected fault information 4, fault information detectable by the partial circuit is generated. And output as the failure information 6 (step S2).

Next, based on the partial circuit information and the fault information 6 output from the partial circuit creation means 5, the fault detection difficult circuit determination means 7 determines whether the number of faults in the partial circuit is greater than a predetermined value. Is determined (step S
3).

Here, by determining whether or not the number of faults in the partial circuit is larger than a predetermined value, it is determined whether or not the partial circuit is a circuit for which fault detection is difficult. As a circuit that is difficult to detect a failure, there is a circuit in which input data is branched to a plurality of gates, and the data is collected again in one gate at an output. And a circuit which is more difficult to detect a failure. The value for judging whether or not the circuit is difficult to detect a fault may be determined in advance, but the value of the number of faults detected by the random test pattern generation means 3 is defined in the entire circuit. It is set based on the ratio to the number of failures.

If it is determined in step S3 that the number of faults in the partial circuit is larger than a predetermined value, the failure detection circuit determining means 7 outputs the fault information in the partial circuit as a postponed list, and postpones it. It is stored in the list storage means 8 (step S4).

On the other hand, if it is determined in step S3 that the number of faults in the partial circuit is equal to or less than the predetermined value, the fault information in the partial circuit is stored in the ATG means of the vacant CPU among the CPUs in the circuit. The ATG means 10 automatically generates a test pattern for detecting a failure in the circuit based on the partial circuit information and the failure information 6 (step S5).

The test pattern generated in step S5 is output as pattern 12, and
The faults not used in the test pattern generation, that is, the faults that are not detected, are output as the undetected fault information 4 because they are continuously used for the test pattern generation.

Thereafter, it is determined whether or not the number of faults detected in the above-described series of processes is a value that satisfies a preset target failure detection rate (step S6). If it is determined that the value satisfies the condition, the pattern merge unit 13 merges the test patterns 12 generated by the random test pattern generation unit 3 and the ATG unit 10, and outputs an output pattern 14.
At the same time, and information on a fault not used for generating a test pattern is output from the ATG means 10 as output undetected fault information 15 (step S).
7).

On the other hand, if it is determined in step S6 that the value does not satisfy the target failure detection rate, it is determined whether or not the processing has been completed for all the partial circuits (step S8). If it is determined that the process for has not been completed, the process returns to step S2.

On the other hand, if it is determined in step S8 that the processing for all the partial circuits has been completed, it is detected whether or not the postponed list is stored in the postponed list storage means 8 (step S9). If no is stored, the process proceeds to step S7.

On the other hand, if it is detected in step S9 that the postponed list is stored in the postponed list storage unit 8, the failure detection difficult circuit processing unit 9 stores the postponed list stored in the postponed list storage unit 8. The (partial circuits) are sorted in ascending order of the number of failures (step S10). This is because the number of faults remaining after the generation of the random test pattern is an index of the ease of detecting a fault in the circuit configuration of the partial circuit.By sorting in this way, when there are a plurality of postponed partial circuits In addition, it is possible to perform processing in order from a circuit having a circuit configuration in which failure detection is most easily performed.

Next, the fault detection difficult circuit processing means 9 selects a fault corresponding to the partial circuit from the undetected fault list of the entire circuit in the undetected fault information 4, and determines the number of faults and the fault of the entire circuit. The number of faults that need to be detected in order for the fault coverage to reach the target fault coverage is compared, thereby calculating the target fault coverage of the partial circuit (hereinafter referred to as the partial circuit target fault coverage). (Step S1
1).

Next, in the ATG means 10, on the basis of the partial circuit target fault coverage calculated in step S 11 and the partial circuit information and the fault information 6 output from the partial circuit creation means 5, A test pattern for detecting a failure is automatically generated (Step S12).

The test pattern generated in step S12 is output as pattern 12, and
Faults not used for test pattern generation in 5,
That is, a failure that has not been detected is indicated by the undetected failure information 4
Is output as

Thereafter, it is determined whether or not the failure detection rate of the partial circuit satisfies the partial circuit target failure detection rate (step S13). If it is determined that the partial circuit target failure detection rate is satisfied, the process proceeds to step S7. Move on to the processing in.

On the other hand, if it is determined in step S13 that the partial circuit target failure detection rate is not satisfied, it is determined whether or not any of the postponed lists is stored in the postponed list storage means 8 (step S14). When it is determined that no postponed list is stored, the process proceeds to step S7, and when it is determined that the postponed list is stored, the process returns to step S11.

As described above, the processing of steps S11 to S14 is performed every time the automatic generation of the test pattern is completed by the ATG means 10 of any of the CPUs in the circuit, and the failure detection of any of the partial circuits is performed. The process is performed until the rate reaches the partial circuit target fault detection rate or until the postponed list (subcircuit) stored in the postponed list 9 disappears.

(Second Embodiment) FIG. 3 is a block diagram showing a second embodiment of the circuit division ATG partial circuit processing system of the present invention.

In this embodiment, as shown in FIG. 3, compared with the first embodiment,
After the partial circuit is created, the only difference is that a random test pattern is generated by the random test pattern generation means 3, and the other configuration is the same as that shown in the first embodiment.

As shown in the present embodiment, even when the random test pattern is generated after the partial circuit is created, it is difficult to detect the number of faults not used for random test pattern generation after the random test pattern is generated. The same effect as that of the first embodiment in which the random test pattern is generated before the creation of the partial circuit can be obtained in that it is used as an index.

(Third Embodiment) An embodiment in which the postponement list processing is performed by failure division will be described below.

FIG. 4 is a flowchart for explaining an embodiment in which the processing of the postponed list is performed by the fault division in the circuit division ATG partial circuit processing method of the present invention. Note that the fault division is a method in which faults to be processed by one circuit are not given all at the same time, but the faults are divided into several groups and given one by one. In the case of performing distributed processing by fault division, the same circuit is provided to a plurality of CPUs, and one group of faults divided into several groups is provided to different CPUs.

First, a circuit for performing the ATG process is divided into a number of CPUs or more, thereby generating a partial circuit and generating fault information detectable by the partial circuit (step S201).

Next, a random pattern is generated using random numbers, and a fault is detected using the generated random pattern and information on all faults not yet detected among faults described as input fault information. A failure simulation is performed, and a failure pattern detected by the failure simulation is adopted as a test pattern (step S202). Note that the detected fault is excluded from targets for subsequent pattern generation.

Next, it is determined whether the number of faults in the partial circuit is larger than a predetermined value (step S20).
3).

Here, by determining whether or not the number of faults in the partial circuit is larger than a predetermined value, it is determined whether or not the partial circuit is a circuit in which fault detection is difficult. As a circuit that is difficult to detect a failure, there is a circuit in which input data is branched to a plurality of gates, and the data is collected again in one gate at an output. And a circuit which is more difficult to detect a failure. The value for determining whether the circuit is difficult to detect a failure may be predetermined, but is defined in the entire circuit as the number of failures detected by the random test pattern generation means. It is set based on the ratio to the number of failures.

If it is determined in step S203 that the number of faults in the partial circuit is larger than a predetermined value, fault information in the partial circuit is output as a postponed list and stored in the postponed list storage means (step S203). S
204).

On the other hand, if it is determined in step S203 that the number of faults in the partial circuit is equal to or smaller than the predetermined value, a test pattern for detecting a fault in the circuit is determined based on the circuit configuration of the fault pattern. Is automatically generated (step S205).

Thereafter, it is determined whether or not the number of faults detected in the above-described series of processes is a value that satisfies a preset target failure detection rate (step S206). If it is determined that the value satisfies the condition, step S202 and step S2
The test patterns generated in step 05 are merged (step S207).

On the other hand, if it is determined in step S206 that the value does not satisfy the target failure detection rate,
It is determined whether the processing for all the partial circuits has been completed (step S208), and if it is determined that the processing for all the partial circuits has not been completed, the process proceeds to step S208.
The process returns to 201.

On the other hand, if it is determined in step S208 that the processing for all the partial circuits has been completed,
It is detected whether or not a postponed list is stored in the postponed list storage means (step S209). If no postponed list is stored, step S207 is performed.
Move on to the processing in.

On the other hand, if it is detected in step S209 that the postponed list is stored in the postponed list storage unit, the postponed list (partial circuit) stored in the postponed list storage unit has a small number of faults. (Step S210).

Next, faults in one partial circuit are randomly divided into several groups (step SS21).
1) The divided faults are passed to the vacant CPU in the circuit for each group, and a test pattern is generated in each CPU (step S212).

Thereafter, it is determined whether or not the fault detected in the above-described series of processes has a value that satisfies a preset target fault detection rate (Step S).
213) If it is determined that the value satisfies the target failure detection rate, the process proceeds to step S207.

On the other hand, if it is determined in step S213 that the value does not satisfy the target failure detection rate,
It is detected whether any of the divided faults has not been used for generating a test pattern yet (step S214). If it is detected that there is a fault not used for generating a test pattern, the process proceeds to step S214. It returns to the process in S212.

On the other hand, if it is detected in step S214 that there is no failure not used for generating the test pattern, it is detected whether or not the postponed list is stored in the postponed list storage means (step S21).
5) If no postponed list is stored, the process proceeds to step S207. If a postponed list is stored, the process returns to step S212.

In the case where the processing of the postponed list is performed by the fault division as shown in the present embodiment, the following effects are obtained.

In distributed processing by circuit division, the same fault may be handled by a plurality of CPUs at the same time. However, processing the same fault by two circuits that are difficult to detect at the same time wastes processing time.

In the processing of the postponed list, the overhead required to detect one fault is considered to be longer than the time required to detect one fault in a partial circuit that is not postponed, so that this overhead is very large.

By processing the postponed list by fault division, the same circuit is processed by all CPUs and different CPs are processed.
U does not handle the same fault. That is, different C
The overhead of handling the same fault in the PU is avoided.

Further, in the case where the processing of the postponed list is performed by the fault division, there is an effect that the efficiency is higher than the case where the circuit which is difficult to detect is the last circuit, which is processed by only one CPU.

(Fourth Embodiment) Hereinafter, a method of forming the partial circuit shown in the above-described embodiment will be described in detail with a specific example.

FIG. 5 is a flow chart for explaining an embodiment of a method of forming a partial circuit in the circuit division ATG partial circuit processing method of the present invention.

First, the information of the circuit for performing the ATG process and the failure information of the circuit are read (step S301).

Next, the input side gate is sequentially traced from the PO (Primary Output) side, and the number of cones included in each cone of each PO is counted (step S302). Here, the cone means a set of gates obtained by sequentially tracing the gates on the input side from the PO side to the PO (Primary Input).

Next, based on the number of gates included in each cone of each PO, POs are sequentially sorted in ascending order of the number of gates, and a PO list is created (step S303).

Next, the number of gates included in the cone of PO sorted last is set as a threshold value of the number of gates of a partial circuit to be created later (step S30).
4).

Thereafter, a random test pattern is generated (step S305).

Next, from the PO list, P
O are taken out one by one (step S306), and the P
A list of gates included in the cone of O is created (step S307).

Next, based on the list created in step S307, the P
The number of gates included in the cone of O is added to the total number of gates of the partial circuit (step S308).

Next, it is determined whether or not the total number of gates in step S308 exceeds the threshold value set in step S304 (step S30).
9) If it is determined that the threshold value is exceeded, a fault list in the partial circuit is created.
0) If it is determined that the threshold value has not been exceeded, the process returns to step S306.

Next, the gate list created in step S307 and the failure list created in step S310 are sent to the remote CPU (step S31).
1).

Thereafter, the remote CPU performs ATG processing based on the gate list and the failure list sent in step S311 (step S31).
2).

[0107] The subsequent processing is the same as that described in the above-described embodiment, and a description thereof will be omitted.

When the ATG process is completed in the remote CPU, a signal to that effect is sent to the partial circuit creating means, and the process returns to step S306.

In the above-described circuit-divided ATG partial circuit processing method, the data is written into a storage medium such as a ROM in which a computer processing program is written, and is read from the storage medium at the time of execution.

[0110]

As described above, in the present invention,
If the number of faults in the partial circuit is larger than a predetermined value based on the partial circuit and fault information created by the branch circuit creating means, the fault information in the partial circuit is output as a postponed list, and the ATG means After the test pattern is generated based on the failure information other than the failure information in the partial circuit output as the postponed list, the test pattern is generated based on the failure information in the partial circuit output as the postponed list, If the failure detection reaches a predetermined target failure detection rate, the failure detection process is terminated.If the target failure detection rate is reached before processing a partial circuit having a circuit configuration in which failure detection is difficult, a failure occurs. There is no need to perform processing of a partial circuit having a circuit configuration that is difficult to detect, and the processing time required for ATG by circuit division is greatly reduced. Door can be.

Further, if a fault that should have been processed by a partial circuit having a circuit configuration that is difficult to detect is also included in a partial circuit that has a circuit configuration that is easy to detect the fault, the fault is detected. Processing is performed first in a partial circuit having a circuit configuration that is easy to detect, a fault is detected, and the detected fault is subsequently excluded from the target of test pattern generation. It is no longer processed in a difficult circuit having a difficult circuit configuration, and the circuit division distributed ATG
As a whole, the processing time can be reduced accordingly.

Further, since the number of faults that need to be detected in the partial circuit which is regarded as the postponed list is not necessarily all of the corresponding undetected fault list, the fault detection rate required in this partial circuit is calculated. The number of failures to be processed can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a circuit division ATG partial circuit processing method according to the present invention.

FIG. 2 is a flowchart for explaining test pattern generation processing in the circuit division ATG partial circuit processing method shown in FIG.

FIG. 3 is a block diagram showing a second embodiment of the circuit division ATG partial circuit processing system of the present invention.

FIG. 4 is a flowchart for explaining an embodiment in which a postponed list is processed by failure division in the circuit division ATG partial circuit processing method of the present invention.

FIG. 5 is a flowchart for explaining one embodiment of a method of creating a partial circuit in the circuit division ATG partial circuit processing method of the present invention.

FIG. 6 is a block diagram showing a configuration example of a conventional circuit division ATG partial circuit processing method.

FIG. 7 is a flowchart for explaining a test pattern generation process in the circuit division ATG partial circuit processing method shown in FIG. 6;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Input circuit information 2 Input fault information 3 Random test pattern generation means 4 Undetected fault information 5 Partial circuit creation means 6 Partial circuit information and fault information 7 Fault detection difficult circuit determination means 8 Delay list storage means 9 Fault detection difficult circuit processing means DESCRIPTION OF SYMBOLS 10 ATG means 12 Pattern 13 Pattern merge means 14 Output pattern 15 Output undetected failure information

Claims (13)

[Claims] A test pattern for generating a random pattern using random numbers, detecting a fault in a circuit using the generated random pattern, and detecting a fault in the circuit based on the detected fault. A random test pattern generating means for generating a partial circuit by dividing the circuit, and a partial circuit generating means for generating fault information detectable by the generated partial circuit; and ATG means for automatically generating a test pattern for detecting a fault in a circuit based on the partial circuit and the fault information created by the above, and a test pattern generated by the random test pattern generating means and the ATG means. A circuit division ATG partial circuit processing system having a pattern merging means for merging and outputting as an output pattern; If the number of faults in the partial circuit is greater than a predetermined value based on the partial circuit and the fault information created by the path creating means, a fault detection difficult circuit determination that outputs the fault information in the partial circuit as a postponed list The ATG means generates the test pattern based on the failure information other than the failure information in the partial circuit output as the delay list from the failure detection circuit determination means, and outputs the test pattern as the delay list. And generating the test pattern based on the failure information in the partial circuit. 2. The circuit division ATG partial circuit processing method according to claim 1, wherein the predetermined value is the number of faults detected by the random test pattern generation means, and the number of faults defined in the entire circuit. A circuit-divided ATG partial circuit processing method, which is set based on a ratio to a number. 3. A postponed list storing means for storing fault information in a subcircuit output as a postponed list from said faulty difficult circuit determination means in the circuit divided ATG partial circuit processing method according to claim 1 or 2. Circuit AT characterized by having
G partial circuit processing method. 4. The circuit division ATG partial circuit processing method according to claim 3, wherein a test pattern is generated based on failure information other than the failure information in the partial circuit output from the failure detection difficult circuit determination means as a postponed list. After the ATG is performed by the ATG means, extracts failure information in the partial circuit output as the postponed list from the postponed list storage means, and outputs the failure detection difficult circuit processing means to the ATG means. Circuit division ATG partial circuit processing method. 5. The circuit-divided ATG partial circuit processing method according to claim 4, wherein said failure-detection-resistant circuit processing means is a partial circuit having a small number of failures among the partial circuits stored in said postponed list storage means. A circuit-divided ATG partial circuit processing method characterized by sequentially outputting failure information to the ATG means. 6. The circuit division ATG partial circuit processing method according to claim 1, wherein said ATG means detects a failure when the failure detection reaches a predetermined target failure detection rate. A circuit division ATG partial circuit processing method, which terminates processing. 7. The circuit division ATG partial circuit processing method according to claim 1, wherein said partial circuit creation means divides said circuit into partial circuits equal to or more than the number of CPUs in the circuit. A circuit divided ATG partial circuit processing method. 8. A first process for detecting a fault in a circuit using a random pattern generated using a random number and generating a test pattern for detecting a fault in the circuit based on the detected fault. And a second process of creating a partial circuit by dividing the circuit and generating fault information detectable by the created partial circuit; and a partial process and a fault created by the second process. A third method for automatically generating a test pattern for detecting a fault in a circuit based on information
And a fourth process of merging the test patterns generated in the first and third processes and outputting the merged test patterns as an output pattern. In the case where the number of faults in the partial circuit is larger than a predetermined value based on the partial circuit and the fault information created in the above process, a fifth process for outputting the fault information in the partial circuit as a postponed list is provided. The third process generates the test pattern based on the failure information other than the failure information in the partial circuit output as the delay list, and then generates the test pattern based on the failure information in the partial circuit output as the delay list. A method of processing a circuit-divided ATG partial circuit, wherein the test pattern is generated. 9. The circuit division ATG partial circuit processing method according to claim 8, wherein the predetermined value is the number of faults detected by the random test pattern generation means, and the number of faults defined in the entire circuit. A circuit-divided ATG partial circuit processing method, wherein the setting is made based on a ratio to the number. 10. The circuit division ATG partial circuit processing method according to claim 8, wherein the test pattern is generated based on the failure information of the partial circuit output as the post-processing list in the third processing. Is a method of processing a circuit-divided ATG partial circuit, wherein the method is performed from the one with the smallest number of faults in the partial circuit. 11. The circuit-divided ATG partial circuit processing method according to claim 8, wherein a failure is detected when the failure detection in the third processing reaches a predetermined target failure detection rate. A method of processing a circuit-divided ATG partial circuit, wherein the detection processing is terminated. 12. The circuit division ATG partial circuit processing method according to claim 8, wherein the test based on the failure information of the partial circuit output as the post-processing list in the third processing. A method of processing a circuit-divided ATG partial circuit, wherein a pattern is generated by dividing a failure in the partial circuit into a plurality of blocks. 13. A storage medium in which a computer processing program is written, wherein the circuit division ATG partial circuit processing method according to claim 8 is written.