JPH11233618A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH11233618A JPH11233618A JP10345630A JP34563098A JPH11233618A JP H11233618 A JPH11233618 A JP H11233618A JP 10345630 A JP10345630 A JP 10345630A JP 34563098 A JP34563098 A JP 34563098A JP H11233618 A JPH11233618 A JP H11233618A
- Authority
- JP
- Japan
- Prior art keywords
- film
- opening
- etching
- mask
- trench
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 28
- 238000004519 manufacturing process Methods 0.000 title claims description 18
- 238000005530 etching Methods 0.000 claims abstract description 42
- 238000000034 method Methods 0.000 claims description 84
- 229920003209 poly(hydridosilsesquioxane) Polymers 0.000 claims description 58
- 239000004020 conductor Substances 0.000 claims description 14
- 238000001020 plasma etching Methods 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 13
- 238000011049 filling Methods 0.000 claims description 8
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 7
- 239000003990 capacitor Substances 0.000 claims description 7
- 238000002955 isolation Methods 0.000 claims description 6
- 239000011810 insulating material Substances 0.000 claims description 4
- 230000002411 adverse Effects 0.000 abstract description 2
- 239000012530 fluid Substances 0.000 abstract 2
- 238000009413 insulation Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 254
- 239000006117 anti-reflective coating Substances 0.000 description 38
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 13
- 229910052721 tungsten Inorganic materials 0.000 description 13
- 239000010937 tungsten Substances 0.000 description 13
- 229910052581 Si3N4 Inorganic materials 0.000 description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 10
- 239000002904 solvent Substances 0.000 description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 9
- 230000004888 barrier function Effects 0.000 description 9
- 238000001459 lithography Methods 0.000 description 9
- 239000007789 gas Substances 0.000 description 8
- 230000009977 dual effect Effects 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 239000000945 filler Substances 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 238000010304 firing Methods 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 230000005855 radiation Effects 0.000 description 4
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 3
- 239000002253 acid Substances 0.000 description 3
- 238000004380 ashing Methods 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- NTIZESTWPVYFNL-UHFFFAOYSA-N Methyl isobutyl ketone Chemical compound CC(C)CC(C)=O NTIZESTWPVYFNL-UHFFFAOYSA-N 0.000 description 2
- UIHCLUNTQKBZGK-UHFFFAOYSA-N Methyl isobutyl ketone Natural products CCC(C)C(C)=O UIHCLUNTQKBZGK-UHFFFAOYSA-N 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000002156 mixing Methods 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000002243 precursor Substances 0.000 description 2
- SCPYDCQAZCOKTP-UHFFFAOYSA-N silanol Chemical compound [SiH3]O SCPYDCQAZCOKTP-UHFFFAOYSA-N 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 239000003513 alkali Substances 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- -1 for example Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
- H01L21/0276—Photolithographic processes using an anti-reflective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/66181—Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
- H10B12/0385—Making a connection between the transistor and the capacitor, e.g. buried strap
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Element Separation (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】この発明は、一般に開口部を
形成する工程を含む半導体装置の製造方法に係り、特に
上記開口部内に流動可能な酸化膜を充填した後に新たな
開口部を形成するようにした半導体装置の製造方法に関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to a method of manufacturing a semiconductor device including a step of forming an opening, and more particularly to a method of forming a new opening after filling the opening with a flowable oxide film. And a method for manufacturing a semiconductor device.
【0002】[0002]
【従来の技術】半導体装置における金属配線及びコンタ
クトを形成するために種々のプロセスが開発されてい
る。一例として、金属膜を形成し、その後、選択エッチ
ングして金属配線を形成するプロセスがある。他の例と
して、いわゆるダマシンプロセス(damascene process
)がある。このダマシンプロセスは、トレンチあるい
は開口を絶縁膜中に形成し、次に導電材料を充填し、そ
の後、導電材料を平坦化するプロセスである。2. Description of the Related Art Various processes have been developed for forming metal wirings and contacts in semiconductor devices. As an example, there is a process of forming a metal film and then performing selective etching to form a metal wiring. Another example is the so-called damascene process.
). This damascene process is a process in which a trench or an opening is formed in an insulating film, a conductive material is filled, and then the conductive material is planarized.
【0003】ダマシンプロセスの一種である二重ダマシ
ンプロセス(dual damascene process)は、導電コンタ
クトと導電配線とを同時に製造するプロセスを含んでい
る。特に、二重ダマシンプロセスにおいて、コンタクト
孔はTEOS膜等の絶縁膜中に形成され、その後、コン
タクト孔の上部部分を広げることによって配線のための
トレンチが絶縁膜中に形成される。次に導電性材料が絶
縁膜上に形成され、コンタクト孔及びトレンチが充填さ
れる。形成された導電性材料はその後、絶縁膜をストッ
パとして使用して化学的機械的研磨(CMP)等の平坦
化プロセスによって平坦化される。[0003] A dual damascene process, which is a type of damascene process, includes a process for simultaneously manufacturing conductive contacts and conductive wiring. In particular, in the dual damascene process, a contact hole is formed in an insulating film such as a TEOS film, and then a trench for wiring is formed in the insulating film by expanding an upper portion of the contact hole. Next, a conductive material is formed on the insulating film, and the contact holes and the trenches are filled. The formed conductive material is then planarized by a planarization process such as chemical mechanical polishing (CMP) using the insulating film as a stopper.
【0004】このような二重ダマシンプロセスによっ
て、プロセスの工程の数が減少し、導電コンタクトと導
電配線とが直に接続される。[0004] With such a dual damascene process, the number of process steps is reduced, and conductive contacts and conductive wiring are directly connected.
【0005】図7(a)〜(d)は、従来の二重ダマシ
ンプロセスにおける幾つかの工程を示す断面図である。FIGS. 7A to 7D are cross-sectional views showing several steps in a conventional dual damascene process.
【0006】図7(a)に示すように、TEOS膜等か
らなる絶縁膜50中にコンタクト孔51を形成し、絶縁
膜50の下部に設けられた絶縁層52中に形成された導
電配線53の上部表面の一部分をこのコンタクト孔51
から露出させる。As shown in FIG. 7A, a contact hole 51 is formed in an insulating film 50 made of a TEOS film or the like, and a conductive wiring 53 formed in an insulating layer 52 provided below the insulating film 50. A part of the upper surface of the contact hole 51
To expose.
【0007】次に、図7(b)に示すように、全面に反
射防止被覆(antireflective coating:ARC)膜(以
下、ARC膜と称する)54を堆積し、さらにレジスト
膜55をARC膜54上に形成する。図7(b)からわ
かるように、コンタクト孔51の形成によって生じたA
RC膜54の上部表面の凹凸状態のために、レジスト膜
55の厚さは不均一となる。Next, as shown in FIG. 7B, an antireflective coating (ARC) film (hereinafter referred to as an ARC film) 54 is deposited on the entire surface, and a resist film 55 is further formed on the ARC film 54. Formed. As can be seen from FIG. 7B, A generated by the formation of the contact hole 51
The thickness of the resist film 55 becomes uneven due to the unevenness of the upper surface of the RC film 54.
【0008】次に、図示しないパターンマスクを用いて
レジスト膜55に対し選択的に露光を行い、その後、現
像処理を行って、図7(c)に示すように、上記コンタ
クト孔51を含みこのコンタクト孔51よりも広い部分
に開口56を有するようにレジスト膜55をパターン化
する。Next, the resist film 55 is selectively exposed using a pattern mask (not shown), and thereafter, is subjected to a development process. As shown in FIG. The resist film 55 is patterned so as to have an opening 56 in a portion wider than the contact hole 51.
【0009】その後、パターン化された上記レジスト膜
55をマスクとして使用してARC膜54及び絶縁膜5
0を反応性イオンエッチング(RIE)プロセスにより
エッチングし、図7(d)に示すようにトレンチ57を
形成する。After that, using the patterned resist film 55 as a mask, the ARC film 54 and the insulating film 5 are formed.
0 is etched by a reactive ion etching (RIE) process to form a trench 57 as shown in FIG.
【0010】[0010]
【発明が解決しようとする課題】ここで、ARC膜54
と絶縁膜50とは異なるエッチング速度を有しており、
RIEプロセス中にARC膜54が絶縁膜50よりも速
い速度でエッチングされる場合には、導電配線53が損
傷を受ける。Here, the ARC film 54 is used.
And the insulating film 50 have different etching rates,
If the ARC film 54 is etched at a higher rate than the insulating film 50 during the RIE process, the conductive wiring 53 is damaged.
【0011】反対に、RIEプロセスの間に、ARC膜
54が絶縁膜50よりも遅い速度でエッチングされる場
合、RIEプロセスの後には、図7(d)に示されるよ
うに、残存したARC膜54の界面付近で一部が突出
し、その他の部分ではARC膜54よりも高さが低い形
状に絶縁膜50が残る。そのため、残存したレジスト膜
55及びARC膜54を除去した後は、先のコンタクト
孔51とトレンチ57との境界に隣接した絶縁膜50に
スパイク部分58が残る。Conversely, if the ARC film 54 is etched at a lower rate than the insulating film 50 during the RIE process, after the RIE process, as shown in FIG. In the vicinity of the interface 54, a part protrudes, and in other parts, the insulating film 50 remains lower than the ARC film 54. Therefore, after removing the remaining resist film 55 and ARC film 54, a spike portion 58 remains in the insulating film 50 adjacent to the boundary between the contact hole 51 and the trench 57.
【0012】この後は、例えば窒化チタン等の接着/バ
リア膜を、絶縁膜50の表面上とコンタクト孔51並び
にトレンチ57の側壁上及び底部壁上に形成する。Thereafter, an adhesion / barrier film of, for example, titanium nitride or the like is formed on the surface of the insulating film 50, on the contact holes 51 and on the side walls and the bottom wall of the trench 57.
【0013】しかし、絶縁膜50のスパイク部分58で
は接着/バリア膜が不均一に形成され、ある領域では全
く形成されなくなる。接着/バリア膜の形成後にタング
ステン等の導電材料をコンタクト孔51及びトレンチ5
7内に形成するが、この導電材料の形成工程において、
接着/バリア層が存在していない領域ではタングステン
中に空隙が生じる可能性がある。これによってタングス
テンが不連続になり、タングステンによって構成される
コンタクト及び配線の抵抗が増加する。However, the bonding / barrier film is formed unevenly at the spike portion 58 of the insulating film 50, and is not formed at all in a certain region. After the formation of the adhesion / barrier film, a conductive material such as tungsten is applied to the contact hole 51 and the trench 5.
7, but in the step of forming the conductive material,
Voids can form in the tungsten in areas where no adhesion / barrier layer is present. As a result, the tungsten becomes discontinuous, and the resistance of the contact and the wiring made of tungsten increases.
【0014】さらに、図7(b)の工程の際に、レジス
ト膜55の厚さが不均一となるために、リソグラフィプ
ロセスが悪影響を受け、高度に正確な寸法を有するトレ
ンチを形成することが困難になる。これは、ARC膜5
4の形成を省略し、レジスト膜55を絶縁膜50の上部
に形成してコンタクト孔51を充填する場合にも同様の
問題が生じる。Further, in the step of FIG. 7B, the thickness of the resist film 55 becomes non-uniform, so that the lithography process is adversely affected and a trench having a highly accurate dimension may be formed. It becomes difficult. This is the ARC film 5
A similar problem occurs when the formation of the resist film 55 is omitted and the contact hole 51 is filled by forming the resist film 55 on the insulating film 50.
【0015】この発明は上記のような事情を考慮してな
されたものであり、その目的は、トレンチを形成する際
に如何なる層に対しても損傷を与えず、コンタクト孔及
びトレンチ内に形成される導電材料からなる層の不連続
性を防止して、導電材料によって構成されるコンタクト
及び配線の抵抗の増加を抑制することができる半導体装
置の製造方法を提供することにある。The present invention has been made in view of the above circumstances, and has as its object to prevent damage to any layer when forming a trench, and to form a contact hole and a trench formed in a trench. It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of preventing discontinuity of a layer made of a conductive material and suppressing an increase in resistance of a contact and a wiring formed of the conductive material.
【0016】この発明の他の目的は、ほぼ均一で比較的
薄い厚さを有するマスク層を用いてリソグラフィプロセ
スを行うことができ、これによりリソグラフィプロセス
を高精度に行うことができる半導体装置の製造方法を提
供することにある。Another object of the present invention is to manufacture a semiconductor device capable of performing a lithography process using a mask layer having a substantially uniform thickness and a relatively small thickness, thereby performing the lithography process with high accuracy. It is to provide a method.
【0017】[0017]
【課題を解決するための手段】本発明によれば、絶縁膜
からなる第1の膜に第1の開口部を形成し、上記第1の
膜の上部に第2の膜を形成して上記第1の開口部を充填
し、上記第2の膜上にマスク層を形成し、上記マスク層
をマスクとして使用して上記第1及び第2の膜がほぼ同
じ速度でエッチングされる条件の第1のエッチングプロ
セスによって上記第1の膜及び第2の膜をエッチングし
て上記第1の膜に第2の開口部を形成し、上記第1の開
口部において上記第2の膜が上記第1の膜よりも速い速
度でエッチングされる条件の第2のエッチングプロセス
によって上第2の膜の残りの部分をエッチング除去する
半導体装置の製造方法が提供されている。According to the present invention, a first opening is formed in a first film made of an insulating film, and a second film is formed on the first film. A first opening is filled, a mask layer is formed on the second film, and the first and second films are etched at substantially the same rate using the mask layer as a mask. Etching the first film and the second film by an etching process to form a second opening in the first film, wherein the second film is formed in the first opening by the first film; A method of manufacturing a semiconductor device in which the remaining portion of the upper second film is etched away by a second etching process under conditions in which etching is performed at a higher speed than that of the first film.
【0018】本発明によれば、絶縁膜からなる第1の膜
に第1の開口部を形成し、上記第1の膜の上部に第2の
膜を形成して上記第1の開口部を充填し、上記第2の膜
上にマスク層を形成し、上記マスク層をマスクとして使
用して上記第1及び第2の膜がほぼ同じ速度でエッチン
グされる条件の第1のエッチングプロセスによって上記
第1の膜及び第2の膜をエッチングして第2の開口部を
形成し、上記第2の膜が上記第1の膜のエッチング速度
よりも速い速度でエッチングされる条件の第2のエッチ
ングプロセスによって上記第1の開口部における上記第
2の膜の残りの部分をエッチングし、上記第1及び第2
の開口部を導電材料で充填する半導体装置の製造方法が
提供されている。According to the present invention, a first opening is formed in a first film made of an insulating film, and a second film is formed on the first film to form the first opening. Filling, forming a mask layer on the second film, and using the mask layer as a mask, performing a first etching process under the condition that the first and second films are etched at substantially the same rate. Etching the first film and the second film to form a second opening, and performing the second etching under the condition that the second film is etched at a higher speed than the etching speed of the first film. The process etches the remaining portion of the second film in the first opening, and removes the first and second films.
A method for manufacturing a semiconductor device in which an opening is filled with a conductive material is provided.
【0019】本発明によれば、隣接した深いトレンチキ
ャパシタを互いに分離するために半導体基板に浅いトレ
ンチ分離構造を形成する半導体層装置の製造方法におい
て、1以上のパッド膜の上部に流動可能な酸化膜を形成
して、上記1以上のパッド膜中に形成されて上記深いト
レンチキャパシタの上部表面の少なくとも1部分を露出
する開口を充填し、上記流動可能な酸化膜上にパターン
化されたレジスト膜を形成し、上記レジスト膜をマスク
として使用して上記流動可能な酸化膜をエッチングし、
上記レジスト膜をマスクとして使用して上記1以上のパ
ッド膜、上記半導体基板及び上記深いトレンチキャパシ
タをエッチングして浅いトレンチを形成し、その際に、
エッチングされた流動可能な酸化膜の残っている部分を
マスクとして使用し、上記浅いトレンチを絶縁材料で充
填する半導体装置の製造方法が提供されている。According to the present invention, in a method of manufacturing a semiconductor layer device for forming a shallow trench isolation structure in a semiconductor substrate in order to isolate adjacent deep trench capacitors from each other, an oxide capable of flowing over one or more pad films is formed. Forming a film to fill an opening formed in the at least one pad film and exposing at least a portion of an upper surface of the deep trench capacitor, and patterned on the flowable oxide film; Forming, etching the flowable oxide film using the resist film as a mask,
The one or more pad films, the semiconductor substrate and the deep trench capacitor are etched using the resist film as a mask to form a shallow trench,
There is provided a method of manufacturing a semiconductor device in which the above-described shallow trench is filled with an insulating material using a remaining portion of the etched flowable oxide film as a mask.
【0020】この発明の半導体装置の製造方法によれ
ば、流動可能な酸化膜によってほぼ均一な厚さを有する
レジストを使用することができる。さらに、流動可能な
酸化膜はエッチングマスクとして機能するため、比較的
薄いレジストを使用でき、それによってリソグラフィプ
ロセスを高精度に行うことができる。According to the method of manufacturing a semiconductor device of the present invention, it is possible to use a resist having a substantially uniform thickness by a flowable oxide film. Further, since the flowable oxide film functions as an etching mask, a relatively thin resist can be used, and thus the lithography process can be performed with high precision.
【0021】[0021]
【発明の実施の形態】以下、図面を参照して本発明の半
導体装置の製造方法を実施の形態により説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a semiconductor device according to the present invention will be described below with reference to the drawings.
【0022】図1(a)〜(d)、図2(a)、(b)
及び図3(a)、(b)はこの発明を二重ダマシンプロ
セスに実施した場合の工程を示す断面図である。FIGS. 1 (a) to 1 (d), FIGS. 2 (a) and 2 (b)
FIGS. 3A and 3B are cross-sectional views showing steps in a case where the present invention is applied to a dual damascene process.
【0023】図1(a)に示すように、絶縁材料、導電
材料あるいは半導電材料で構成された基板10上に、二
酸化シリコン(SiO2 )、ボロフォスフォシリケート
ガラス(BPSG)、フォスフォシリケートガラス(P
SG)、窒化シリコン(Si3 N4 )、あるいはその他
の絶縁材料からなる第1の絶縁膜11を形成し、さら
に、ダマシンプロセスによって第1の絶縁膜11中に導
電配線12を形成する。この導電配線12は、例えばタ
ングステン(W)によって構成されており、約200n
mの厚さと約300nmの幅とを有している。As shown in FIG. 1A, silicon dioxide (SiO 2 ), borophosphosilicate glass (BPSG), and phosphosilicate are formed on a substrate 10 made of an insulating material, a conductive material or a semiconductive material. Glass (P
A first insulating film 11 made of SG), silicon nitride (Si 3 N 4 ), or another insulating material is formed, and a conductive wiring 12 is formed in the first insulating film 11 by a damascene process. The conductive wiring 12 is made of, for example, tungsten (W) and has a thickness of about 200 n.
m and a width of about 300 nm.
【0024】上記導電配線12はダマシンプロセスに従
って次のように形成される。すなわち、通常のリソグラ
フィプロセスを使用して第1の絶縁膜11に開口部を形
成し、それに続いて反応性イオンエッチングを行う。次
にタングステンをスパッタリングあるいは化学的気相成
長(CVD)によって堆積し、CMPプロセスによって
平坦化する。この平坦化の際に、第1の絶縁膜11はC
MPプロセスに対するストッパとして使用される。ま
た、必要ならば、例えば窒化チタン等の接着/バリア膜
をタングステンの堆積の前に形成してもよい。The conductive wiring 12 is formed as follows according to a damascene process. That is, an opening is formed in the first insulating film 11 using a normal lithography process, and subsequently, reactive ion etching is performed. Next, tungsten is deposited by sputtering or chemical vapor deposition (CVD) and planarized by a CMP process. At the time of this flattening, the first insulating film 11 has C
Used as a stopper for the MP process. If necessary, an adhesive / barrier film such as titanium nitride may be formed before the tungsten is deposited.
【0025】次に、図1(b)に示すように、第2の絶
縁膜13を第1の絶縁膜11上に形成する。この第2の
絶縁膜13は、約1100nmの厚さを有しており、例
えば低圧化学的気相成長(LPCVD)あるいはプラズ
マ増強化学的気相成長(PECVD)によって形成され
たTEOS膜である。続いて、「Shipley 社」から入手
可能であり、約45nmの厚さを有している「BAR
L」等の反射防止被覆膜(ARC膜)14を、第2の絶
縁膜13上に形成する。このARC膜14は、次の工程
においてARC膜14上に形成される放射線感知膜を露
光するために使用する放射線の反射を減少する目的で設
けられる。Next, as shown in FIG. 1B, a second insulating film 13 is formed on the first insulating film 11. The second insulating film 13 has a thickness of about 1100 nm and is, for example, a TEOS film formed by low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD). Subsequently, a "BAR" available from Shipley and having a thickness of about 45 nm
An anti-reflection coating film (ARC film) 14 such as “L” is formed on the second insulating film 13. The ARC film 14 is provided for the purpose of reducing the reflection of radiation used for exposing the radiation-sensitive film formed on the ARC film 14 in the next step.
【0026】次に、放射線感知膜、例えばフォトレジス
ト等のレジスト膜15をARC膜14上に形成する。こ
のレジスト膜15は約850nmの厚さを有し、例えば
「Shipley 社」から入手可能な「APEX−E」あるい
は「UV2HS」等が使用可能である。さらに、上記レ
ジスト膜15としては、例えば化学的増幅レジスト、非
化学的増幅レジスト、ポジ型レジスト、あるいはネガ型
レジスト等を含む種々のタイプのレジスト膜が使用可能
である。Next, a radiation sensing film, for example, a resist film 15 such as a photoresist is formed on the ARC film 14. The resist film 15 has a thickness of about 850 nm. For example, "APEX-E" or "UV2HS" available from "Shipley" can be used. Further, as the resist film 15, various types of resist films including, for example, a chemically amplified resist, a non-chemically amplified resist, a positive resist, a negative resist and the like can be used.
【0027】次に、レジスト膜15に対し、図示しない
マスクを使用して露光を行い、その後、レジスト膜15
中にパターンを定めるように現像する。現像後、レジス
ト膜15のパターンは開口部16を含む。この露光プロ
セスの際に、例えば「SVGL社」から入手可能な「Mi
crascan II」、あるいは「ニコン社」から入手可能な
「NSR−S201A」などが露光装置として使用され
る。また、最近のより進歩したリソグラフ技術で使用さ
れる、193nmの単一帯域を有するArFエキシマレ
ーザを使用してもよい。Next, the resist film 15 is exposed using a mask (not shown).
Develop to define the pattern inside. After the development, the pattern of the resist film 15 includes the openings 16. At the time of this exposure process, for example, “Mi
crascan II "or" NSR-S201A "available from Nikon Corporation is used as the exposure apparatus. Also, an ArF excimer laser with a single band of 193 nm used in recent more advanced lithographic techniques may be used.
【0028】次に、図1(c)に示すように、パターン
化されたレジスト膜15をマスクとして使用したRIE
プロセスによってARC膜14及び第2の絶縁膜13を
エッチングし、導電配線12の少なくとも一部分が露出
するようにコンタクト孔17を絶縁膜13に形成する。
このRIEプロセスの際に、ARC膜14は、例えばO
2 ガスあるいはO2 とCF4 の混合ガスを使用してエッ
チングする。また、TEOS膜からなる絶縁膜13は、
例えば、CF4 ガスあるいはCHF3 あるいはC4 F8
等のいくつかの別のCF4 タイプのガスを使用してエッ
チングする。コンタクト孔17の形成後に、レジスト膜
15及び残りのARC膜14を除去する。Next, as shown in FIG. 1C, RIE using the patterned resist film 15 as a mask
The ARC film 14 and the second insulating film 13 are etched by a process, and a contact hole 17 is formed in the insulating film 13 so that at least a part of the conductive wiring 12 is exposed.
During this RIE process, the ARC film 14 is
Etching is performed using two gases or a mixed gas of O 2 and CF 4 . The insulating film 13 made of a TEOS film is
For example, CF 4 gas or CHF 3 or C 4 F 8
Etch using some other CF 4 type gas, such as. After the formation of the contact holes 17, the resist film 15 and the remaining ARC film 14 are removed.
【0029】次に、図1(d)に示すように、「Dow Co
rning 社」より入手可能な「FOX」等の流動可能な酸
化膜18を絶縁膜13上部に形成し、コンタクト孔17
を充填する。ここで、絶縁膜13の上部表面上の酸化膜
18の厚さは約0.1μmである。例えば、米国特許第
5,530,293 号及び第5,085,893 号明細書に記載されてい
るように、流動可能な酸化物は、炭素を含まないSiO
2 の前駆物質である水素シルセスキオキサン(hydrogen
silsequioxanes )から得られる。これらの流動可能な
酸化物は次の式によって表すことができる。Next, as shown in FIG.
A flowable oxide film 18 such as “FOX” available from “Rning Co.” is formed on the insulating film 13 and the contact hole 17 is formed.
Fill. Here, the thickness of oxide film 18 on the upper surface of insulating film 13 is about 0.1 μm. For example, U.S. Patent No.
As described in US Pat. Nos. 5,530,293 and 5,085,893, the flowable oxide is a carbon-free SiO2.
A second precursor hydrogen silsesquioxane (Hydrogen
obtained from silsequioxanes). These flowable oxides can be represented by the following formula:
【0030】(HSi(OH)x O3-x/2 )n ここで、nは約8よりも大きい整数であり、xは0と2
の間の数である。(HSi (OH) x O 3-x / 2 ) n where n is an integer greater than about 8, and x is 0 and 2
Is a number between
【0031】この発明の方法での使用に好適な流動可能
な酸化膜は、溶媒がメチルイソブチルケトン(MIB
K)であり、シラノールの含有量が膜の所望の厚さに応
じて約0.1乃至20重量パーセントであるようなもの
である。例えば、シラノール含有量は、0.1μmの厚
さを有する膜に対して約5重量%である。A flowable oxide film suitable for use in the method of the present invention comprises a solvent wherein methyl isobutyl ketone (MIB) is used.
K) such that the silanol content is about 0.1 to 20 weight percent, depending on the desired thickness of the film. For example, the silanol content is about 5% by weight for a film having a thickness of 0.1 μm.
【0032】上記流動可能な酸化膜18は室温でスピン
コートによって形成し、その後焼成する。焼成は溶媒を
蒸発させるために150℃で1分間行い、その後、流動
可能な酸化膜18をリフローするために200℃で1分
間、次に350℃で1分間焼成する。このときの焼成は
空気中あるいは窒素中で行われる。以下に説明する理由
のために、流動可能な酸化膜18の表面部分の溶媒を完
全に蒸発させることを確実にするために、焼成プロセス
に加えてプラズマO2 灰化プロセス等の表面硬化処理を
約200℃の温度で行ってもよい。The flowable oxide film 18 is formed by spin coating at room temperature, and then fired. The firing is performed at 150 ° C. for 1 minute to evaporate the solvent, and then at 200 ° C. for 1 minute and then at 350 ° C. for 1 minute to reflow the flowable oxide film 18. The firing at this time is performed in air or nitrogen. For reasons explained below, a surface hardening treatment, such as a plasma O 2 ashing process, in addition to a firing process, is performed to ensure that the solvent on the surface portion of the flowable oxide film 18 is completely evaporated. It may be performed at a temperature of about 200 ° C.
【0033】次に、図2(a)に示すように、先に述べ
たBARLのような反射防止被覆膜(ARC膜)19を
流動可能な酸化膜18上に形成する。このとき、ARC
膜19の溶媒と、流動可能な酸化膜18の溶媒との混合
を避けることが望ましい。上述した流動可能な酸化膜1
8の焼成及び灰化処理は、任意の溶媒の混合を防ぐため
に少なくとも流動可能な酸化膜18の表面において流動
可能な酸化膜18の溶媒を蒸発するために役立つ。流動
可能な酸化膜18の焼成及び灰化処理の代りに、流動可
能な酸化膜18の溶媒と混合しない溶媒を使用するAR
C膜19を用いてもよい。Next, as shown in FIG. 2A, an antireflection coating film (ARC film) 19 such as the above-mentioned BARL is formed on the flowable oxide film 18. At this time, ARC
It is desirable to avoid mixing the solvent of the film 19 with the solvent of the flowable oxide film 18. Flowable oxide film 1 described above
The baking and ashing treatment of 8 serves to evaporate the solvent of the flowable oxide film 18 at least on the surface of the flowable oxide film 18 to prevent mixing of any solvent. AR that uses a solvent that does not mix with the solvent of the flowable oxide film 18 instead of baking and ashing the flowable oxide film 18
The C film 19 may be used.
【0034】続いて、上述の「APEX−E」あるいは
「UV2HS」レジストのような放射線感知膜、例えば
フォトレジスト等のレジスト膜20をRC膜19上に約
850nmの厚さに形成する。上記レジスト膜20とし
ては、例えば化学的増幅レジスト、非化学的増幅レジス
ト、ポジ型レジスト、あるいはネガ型レジスト等を含む
種々のタイプのレジスト膜が使用可能である。Subsequently, a radiation sensing film such as the above-mentioned "APEX-E" or "UV2HS" resist, for example, a resist film 20 such as a photoresist is formed on the RC film 19 to a thickness of about 850 nm. As the resist film 20, various types of resist films including, for example, a chemically amplified resist, a non-chemically amplified resist, a positive resist, and a negative resist can be used.
【0035】ここで、流動可能な酸化膜18を形成し、
リフローを行うことによって、レジスト膜20はほぼ均
一な厚さで形成され、これによってリソグラフィプロセ
スの性能を改善することができる。上記レジスト膜20
に対して、図示しないマスクを使用して露光を行い、レ
ジスト膜20中にパターンを定めるように現像する。現
像後、レジスト膜20のパターンは開口部21を含む。Here, a flowable oxide film 18 is formed,
By performing the reflow, the resist film 20 is formed with a substantially uniform thickness, thereby improving the performance of the lithography process. The above resist film 20
Is exposed using a mask (not shown) and developed so as to define a pattern in the resist film 20. After the development, the pattern of the resist film 20 includes the opening 21.
【0036】次に、上記レジスト膜20をマスクに用い
た反応性イオンエッチングプロセス(RIE)等のエッ
チングプロセスより、ARC膜19、流動可能な酸化膜
18及び第2の絶縁膜13をエッチングして、図2
(b)に示すようにトレンチ22を形成する。ここで、
ARC膜19は、例えばO2 ガスあるいはO2 −CF4
混合ガスを使用してエッチングし、流動可能な酸化膜1
8及び第2の絶縁膜13は、例えばCF4 ガス、または
CHF3 あるいはC4 F8 等の別のCF4 タイプのガス
を使用してエッチングする。このエッチングプロセス中
に、流動可能な酸化膜18及び第2の絶縁膜13はほぼ
同じ速度でエッチングされる。従って、従来のような第
2の絶縁膜13のスパイク部分が形成されることがな
く、導電配線12も損傷されない。Next, the ARC film 19, the flowable oxide film 18 and the second insulating film 13 are etched by an etching process such as a reactive ion etching process (RIE) using the resist film 20 as a mask. , FIG. 2
A trench 22 is formed as shown in FIG. here,
The ARC film 19 is made of, for example, O 2 gas or O 2 —CF 4
Flowable oxide film 1 etched using mixed gas
The 8 and the second insulating film 13 are etched using, for example, CF 4 gas or another CF 4 type gas such as CHF 3 or C 4 F 8 . During this etching process, the flowable oxide film 18 and the second insulating film 13 are etched at approximately the same rate. Therefore, a spike portion of the second insulating film 13 unlike the related art is not formed, and the conductive wiring 12 is not damaged.
【0037】次に、図3(a)に示すように、レジスト
膜20及びARC膜19の残りの部分を除去する。この
時、流動可能な酸化膜18は第2の絶縁膜13の上部表
面上及びコンタクト孔17中に残る。その後、この残り
の流動可能な酸化膜18を、例えばレジスト現像液、ま
たはNH3 OHあるいはテトラメチルアンモニウム水酸
化物(TMAH)等のアンモニアベースの液体等のアル
カリを使用して除去する。この場合、HFベースの酸あ
るいは稀釈されたHFベースの酸等の弱酸を使用しても
よい。これに限らず、残存している流動可能な酸化膜1
8を除去するために使用されるプロセスはどのようなも
のであっても、そのプロセスは流動可能な酸化膜を除去
するために非常に高い選択性(例えば100程度の選択
性)を有する必要がある。この方法において、流動可能
な酸化膜18は、TEOS膜からなる第2の絶縁膜13
に損傷を与えずに容易に取除くことができる。Next, as shown in FIG. 3A, the remaining portions of the resist film 20 and the ARC film 19 are removed. At this time, the flowable oxide film 18 remains on the upper surface of the second insulating film 13 and in the contact hole 17. Thereafter, the remaining flowable oxide film 18 is removed using, for example, a resist developer or an alkali such as an ammonia-based liquid such as NH 3 OH or tetramethylammonium hydroxide (TMAH). In this case, a weak acid such as an HF-based acid or a diluted HF-based acid may be used. The remaining flowable oxide film 1 is not limited to this.
Whatever process is used to remove 8, the process must have very high selectivity (eg, selectivity on the order of 100) to remove the flowable oxide film. is there. In this method, the flowable oxide film 18 becomes the second insulating film 13 made of a TEOS film.
It can be easily removed without damaging it.
【0038】次に、第2の絶縁膜13の上部表面、トレ
ンチ22の側壁及び底部壁上、並びにコンタクト孔17
上に、例えばスパッタリングによって窒化チタン等の接
着/バリア層23を形成する。次に、例えばスパッタリ
ングあるいはブランケットCVDプロセスにより、第2
の絶縁膜13の上部表面上に導電材料例えばタングステ
ンを堆積し、コンタクト孔17及びトレンチ22を充填
することによってタングステン層24を形成する。Next, the upper surface of the second insulating film 13, the side wall and the bottom wall of the trench 22, and the contact hole 17 are formed.
An adhesion / barrier layer 23 of titanium nitride or the like is formed thereon by, for example, sputtering. Next, a second process is performed, for example, by sputtering or a blanket CVD process.
A conductive material, for example, tungsten is deposited on the upper surface of the insulating film 13 and a tungsten layer 24 is formed by filling the contact hole 17 and the trench 22.
【0039】次に、図3(b)に示すように、第2の絶
縁膜13をストッパとして使用して、上記接着/バリア
層23及びタングステン層を化学的機械的研磨(CM
P)等の平坦化プロセスによって研磨し、平坦化する。
これによってコンタクト及び金属配線が同時に形成され
る。Next, as shown in FIG. 3B, the bonding / barrier layer 23 and the tungsten layer are chemically and mechanically polished (CM) using the second insulating film 13 as a stopper.
Polishing and flattening by a flattening process such as P).
As a result, the contact and the metal wiring are simultaneously formed.
【0040】このように上記実施の形態による方法で
は、第2の絶縁膜13にコンタクト孔17を形成した後
に流動可能な酸化膜18を形成し、コンタクト孔17を
充填するようにしたので、この流動可能な酸化膜18及
びその上に形成されるARC膜19の膜厚を一様にする
ことができる。また、エッチングの際に、流動可能な酸
化膜18とARC膜19はほぼ同じ速度でエッチングさ
れるので、従来のように第2の絶縁膜13にスパイク部
分が形成されることがなく、導電配線12も損傷される
ことがない。As described above, in the method according to the above embodiment, the flowable oxide film 18 is formed after the contact hole 17 is formed in the second insulating film 13 and the contact hole 17 is filled. The thickness of the flowable oxide film 18 and the ARC film 19 formed thereon can be made uniform. Further, at the time of etching, the flowable oxide film 18 and the ARC film 19 are etched at substantially the same rate, so that a spike portion is not formed in the second insulating film 13 unlike the conventional case, 12 is not damaged.
【0041】また、上記のようにスパイク部分が形成さ
れないので、接着/バリア層23を一様の厚さに形成す
ることができる。従って、この後に、タングステンを堆
積してコンタクト孔17及びトレンチ22を形成する際
に、空隙を生じないでタングステン層24を形成するこ
とができ、この結果、コンタクト及び配線の抵抗の増加
を抑制することができる。Since the spike portion is not formed as described above, the adhesive / barrier layer 23 can be formed with a uniform thickness. Therefore, when tungsten is subsequently deposited to form the contact hole 17 and the trench 22, the tungsten layer 24 can be formed without forming a void, and as a result, an increase in contact and wiring resistance is suppressed. be able to.
【0042】上記実施の形態による方法では、以下のよ
うな種々の変形が可能である。例えば、上記実施の形態
ではコンタクト孔17を形成した後にトレンチ22を形
成する場合を説明したが、これはコンタクト孔17を形
成する前にトレンチ22を形成してもよい。このように
した場合、コンタクト孔17の開口が狭いと、結果的に
コンタクト孔の開口上に形成される流動可能な酸化膜1
8の膜厚の不均一性も小さくなるから、コンタクト孔を
最初に形成することによって平坦度が改良される。In the method according to the above-described embodiment, the following various modifications are possible. For example, in the above embodiment, the case where the trench 22 is formed after the formation of the contact hole 17 has been described. However, the trench 22 may be formed before the formation of the contact hole 17. In this case, if the opening of the contact hole 17 is narrow, the flowable oxide film 1 formed on the opening of the contact hole is consequently formed.
Since the non-uniformity of the film thickness of No. 8 is also reduced, the flatness is improved by forming the contact holes first.
【0043】さらに、上記実施の形態ではARC膜19
を形成する場合について説明したが、このARC膜19
の形成を省略してもよい。Further, in the above embodiment, the ARC film 19 is used.
Has been described, but this ARC film 19 is formed.
May be omitted.
【0044】さらに、上記実施の形態では流動可能な酸
化膜として、炭素を含まないSiO2 の前駆物質である
水素シルセスキオキサン(hydrogen silsequioxanes )
から得られる「FOX」を用いる場合を説明したが、こ
れはそれに限定されるものではなく、トレンチ22を形
成するためのエッチングプロセス中には周囲の材料とほ
ぼ同じエッチング速度を有し、また、残りの部分を取除
くためのエッチングプロセス中には周囲の材料よりも速
いエッチング速度を有する別の膜を使用してもよい。Further, in the above embodiment, the flowable oxide film is formed of hydrogen silsequioxanes which are precursors of carbon-free SiO 2.
Has been described, but is not limited thereto, has an etching rate that is substantially the same as that of the surrounding material during the etching process for forming the trench 22, and During the etching process to remove the remainder, another film with a higher etch rate than the surrounding material may be used.
【0045】次に、ブロセス中に流動可能な酸化膜を使
用する、この発明の他の実施の形態について説明する。
この実施の形態は、この発明の方法を256Mビットの
ダイナミック・ランダム・アクセス・メモリ(DRA
M)におけるメモリセルの製造に実施したものである。
このようなメモリセルの構造は、例えば、「Nesbit」等
による文献「A 0.6 μm2 256Mb Trench DRAM Cell Wi
th Self-AlignedBuriEd STrap(BEST)、(IEDM 1993,pp.6
27-630)」に記載されている。これに記載されたメモリ
セルは深いトレンチキャパシタ及び伝送ゲートを有し、
浅いトレンチ分離構造によって他のメモリセルから分離
されている活性領域中に形成される。Next, another embodiment of the present invention using an oxide film which can flow in a process will be described.
In this embodiment, the method of the present invention is applied to a 256 Mbit dynamic random access memory (DRA).
M).
The structure of such a memory cell is described, for example, in “A 0.6 μm 2 256 Mb Trench DRAM Cell Wi
th Self-AlignedBuriEd STrap (BEST), (IEDM 1993, pp.6
27-630) ". The memory cell described therein has a deep trench capacitor and a transmission gate,
It is formed in an active region separated from other memory cells by a shallow trench isolation structure.
【0046】次に、このようなメモリセルを有するメモ
リの製造方法を図4(a)、(b)、図5(a)、
(b)及び図6の断面図を参照して説明する。Next, a method of manufacturing a memory having such a memory cell will be described with reference to FIGS.
This will be described with reference to FIG. 6B and the cross-sectional view of FIG.
【0047】複数のメモリセルを互いに分離するために
浅いトレンチをエッチングするRIEプロセスの前に、
まず、図4(a)に示すような構造を形成する。すなわ
ち、半導体基板、例えばシリコン半導体基板30中に深
いトレンチ31を形成する。このトレンチ31内には導
電性のトレンチ充填剤32が充填される。このトレンチ
充填剤32は図では単一のトレンチ充填材として示され
ているが、先の「Nesbit」等による文献に記載されてい
るようにポリシリコンを含む種々のトレンチ充填材で構
成してもよい。Prior to the RIE process of etching a shallow trench to separate a plurality of memory cells from each other,
First, a structure as shown in FIG. 4A is formed. That is, a deep trench 31 is formed in a semiconductor substrate, for example, a silicon semiconductor substrate 30. The trench 31 is filled with a conductive trench filler 32. Although this trench filler 32 is shown as a single trench filler in the figure, it may be comprised of various trench fillers, including polysilicon, as described in the literature by Nesbit, supra. Good.
【0048】また、上記トレンチ充填剤32は、記憶ノ
ード(ストレージノード)絶縁膜33及びカラー酸化
(カラーオキサイド)膜34によって半導体基板30か
ら絶縁されている。The trench filler 32 is insulated from the semiconductor substrate 30 by a storage node (storage node) insulating film 33 and a collar oxide (color oxide) film 34.
【0049】さらに、半導体基板30の表面上にはパッ
ドシリコン酸化膜(SiO2 膜)35及びパッドシリコ
ン窒化膜(Si3 N4 膜)36が形成され、このパッド
酸化膜35及びパッドシリコン窒化膜36に対して開口
部37が形成される。そして、この開口部37からトレ
ンチ充填材32の上部表面が露出している。Further, a pad silicon oxide film (SiO 2 film) 35 and a pad silicon nitride film (Si 3 N 4 film) 36 are formed on the surface of the semiconductor substrate 30, and the pad oxide film 35 and the pad silicon nitride film are formed. An opening 37 is formed for 36. Then, the upper surface of the trench filling material 32 is exposed from the opening 37.
【0050】次に、図4(b)に示すように、パッドシ
リコン窒化膜36の上部表面上に流動可能な酸化膜38
を形成して、開口部37内を充填する。この場合、先の
実施の形態の場合と同様に、室温でスピンコートによっ
て形成し、その後焼成する。この焼成は溶媒を蒸発させ
るために150℃で1分間行い、その後、流動可能な酸
化膜18をリフローするために200℃で1分間、次に
350℃で1分間焼成する。このときの焼成は空気中あ
るいは窒素中で行われる。続いて、上記流動可能な酸化
膜38上にARC膜39を形成し、さらにARC膜39
上にレジスト膜40を形成する。Next, as shown in FIG. 4B, a flowable oxide film 38 is formed on the upper surface of the pad silicon nitride film 36.
Is formed to fill the inside of the opening 37. In this case, as in the case of the above embodiment, the film is formed by spin coating at room temperature, and then fired. This baking is performed at 150 ° C. for one minute to evaporate the solvent, and then baking at 200 ° C. for one minute and then at 350 ° C. for one minute to reflow the flowable oxide film 18. The firing at this time is performed in air or nitrogen. Subsequently, an ARC film 39 is formed on the flowable oxide film 38, and the ARC film 39 is further formed.
A resist film 40 is formed thereon.
【0051】ここで、流動可能な酸化膜38を形成する
ことによって、レジスト膜40はほぼ均一な厚さとな
る。Here, by forming the flowable oxide film 38, the resist film 40 has a substantially uniform thickness.
【0052】次に、上記レジスト膜40に対して、浅い
トレンチ分離構造を形成するためにマスクを使用して選
択的に露光を行い、その後、図5(a)に示すように、
パターン化されたレジストを残すように現像する。Next, the resist film 40 is selectively exposed using a mask in order to form a shallow trench isolation structure, and thereafter, as shown in FIG.
Develop to leave patterned resist.
【0053】次に、ARC膜39及び流動可能な酸化膜
38をパターン化されたレジスト膜40をマスクとして
使用してエッチングすることにより、図5(b)に示す
ような構造が残る。エッチングはARC膜39及び流動
可能な酸化膜38に対しては選択的に行われる。このと
き、パターン化されたレジスト膜40及びその下部のA
RC膜39の一部もしくは全部が除去される場合もあ
る。Next, by etching the ARC film 39 and the flowable oxide film 38 using the patterned resist film 40 as a mask, the structure as shown in FIG. 5B remains. The etching is selectively performed on the ARC film 39 and the flowable oxide film 38. At this time, the patterned resist film 40 and A
Some or all of the RC film 39 may be removed.
【0054】次に、図6に示すように、レジスト膜40
が残っている場合にはこのレジスト膜40及びARC膜
39をマスクとして使用して、RIEプロセスにより、
パッドシリコン窒化膜36、パッドシリコン酸化膜3
5、基板30、トレンチ充填材32及びカラー酸化膜3
4をエッチングして浅いトレンチ41を形成する。Next, as shown in FIG.
When the resist remains, the resist film 40 and the ARC film 39 are used as a mask to perform an RIE process.
Pad silicon nitride film 36, pad silicon oxide film 3
5, substrate 30, trench filling material 32 and collar oxide film 3
4 is etched to form a shallow trench 41.
【0055】このエッチングの際に、レジスト膜40及
びARC膜39が完全に除去された後、流動可能な酸化
膜38が残る。特に、このエッチング中に、残っている
レジスト膜40及びARC膜39が除去されることが好
ましい。しかしながら、レジスト膜が取除かれた後でさ
え、流動可能な酸化膜38はエッチングマスクとして機
能する。その理由は、流動可能な酸化膜38のエッチン
グ速度が、窒化シリコン(すなわち、パッドシリコン窒
化膜36)、シリコン(すなわち、半導体基板30)及
びポリシリコン(すなわち、トレンチ充填材32)のエ
ッチング速度よりも遅いからである。At the time of this etching, the flowable oxide film 38 remains after the resist film 40 and the ARC film 39 are completely removed. In particular, it is preferable that the remaining resist film 40 and ARC film 39 are removed during this etching. However, even after the resist film has been removed, the flowable oxide film 38 functions as an etching mask. This is because the etch rate of the flowable oxide film 38 is greater than the etch rate of silicon nitride (ie, pad silicon nitride film 36), silicon (ie, semiconductor substrate 30), and polysilicon (ie, trench fill 32). Is also slow.
【0056】パッドシリコン酸化膜35及びカラー酸化
膜34のエッチング速度と、流動可能な酸化膜38のエ
ッチング速度は類似しているが、パッドシリコン酸化膜
35及びカラー酸化膜34は非常に薄い膜であるため、
図5(b)中に示される流動可能な酸化膜38をマスク
として使用する能力に著しく影響を与えることはない。
流動可能な酸化膜38は、レジスト膜40が取除かれた
後でさえマスクとして機能するので、リソグラフ処理に
は比較的薄いレジストを使用することができ、これによ
りリソグラフィ性能が増強される。Although the etching rates of the pad silicon oxide film 35 and the collar oxide film 34 are similar to the etching rate of the flowable oxide film 38, the pad silicon oxide film 35 and the collar oxide film 34 are very thin films. Because
This does not significantly affect the ability to use the flowable oxide film 38 shown in FIG. 5B as a mask.
Since the flowable oxide film 38 acts as a mask even after the resist film 40 has been removed, a relatively thin resist can be used for lithographic processing, thereby enhancing lithographic performance.
【0057】図6に示した流動可能な酸化膜38の残存
部分を除去した後は、浅いトレンチ41をTEOS等の
絶縁体で充填し、これによって浅いトレンチ分離構造が
形成される。After the remaining portion of the flowable oxide film 38 shown in FIG. 6 is removed, the shallow trench 41 is filled with an insulator such as TEOS, thereby forming a shallow trench isolation structure.
【0058】この実施の形態では、パッド酸化膜35及
びパッドシリコン窒化膜36に対して開口部37を形成
した後、パッドシリコン窒化膜36の上部表面上に流動
可能な酸化膜38を形成して、開口部37内を充填する
ようにしたので、この流動可能な酸化膜38の上面はほ
ぼ平坦面となり、その上に形成されるレジスト膜40の
膜厚は一様になる。さらに、流動可能な酸化膜38はエ
ッチングマスクとして機能するため、比較的薄いレジス
ト膜40を使用することができ、この結果、リソグラフ
ィプロセスを高精度で行うことができる。In this embodiment, after an opening 37 is formed in the pad oxide film 35 and the pad silicon nitride film 36, a flowable oxide film 38 is formed on the upper surface of the pad silicon nitride film 36. Since the opening 37 is filled, the upper surface of the flowable oxide film 38 becomes substantially flat, and the thickness of the resist film 40 formed thereon becomes uniform. Further, since the flowable oxide film 38 functions as an etching mask, a relatively thin resist film 40 can be used, and as a result, the lithography process can be performed with high accuracy.
【0059】[0059]
【発明の効果】以上説明したようにこの発明によれば、
トレンチを形成する際に如何なる層に対しても損傷を与
えず、コンタクト孔及びトレンチ内に形成される導電材
料からなる層の不連続性を防止して、導電材料によって
構成されるコンタクト及び配線の抵抗の増加を抑制する
ことができる。As described above, according to the present invention,
When the trench is formed, no damage is caused to any layer, the discontinuity of the contact hole and the layer made of the conductive material formed in the trench is prevented, and the contact and the wiring constituted by the conductive material are formed. An increase in resistance can be suppressed.
【0060】また、この発明にあっては、ほぼ均一で比
較的薄い厚さを有するマスク層を用いてリソグラフィプ
ロセスを行うことができ、これによりリソグラフィプロ
セスを高精度に行うことができる。Further, according to the present invention, the lithography process can be performed using a mask layer having a substantially uniform thickness and a relatively small thickness, whereby the lithography process can be performed with high precision.
【図1】この発明の第1の実施の形態による二重ダマシ
ンプロセスを示す断面図。FIG. 1 is a sectional view showing a dual damascene process according to a first embodiment of the present invention.
【図2】図1に続くプロセスを示す断面図。FIG. 2 is a sectional view showing a process following FIG. 1;
【図3】図2に続くプロセスを示す断面図。FIG. 3 is a sectional view showing a process following FIG. 2;
【図4】本発明の第2の実施の形態による浅いトレンチ
分離プロセスを示す断面図。FIG. 4 is a cross-sectional view showing a shallow trench isolation process according to a second embodiment of the present invention.
【図5】図4に続くプロセスを示す断面図。FIG. 5 is a sectional view showing a process following FIG. 4;
【図6】図5に続くプロセスを示す断面図。FIG. 6 is a sectional view showing a process following FIG. 5;
【図7】従来の二重ダマシンプロセスの幾つかの工程を
示す断面図。FIG. 7 is a cross-sectional view showing some steps of a conventional dual damascene process.
10…基板、 11…第1の絶縁膜、 12…導電配線、 13…第2の絶縁膜、 14…反射防止被覆膜(ARC膜)、 15…レジスト膜、 16…開口部、 17…コンタクト孔、 18…流動可能な酸化膜、 19…反射防止被覆膜(ARC膜)、 20…レジスト膜、 21…開口部、 22…トレンチ、 23…接着/バリア層、 24…タングステン層、 30…シリコン半導体基板、 31…深いトレンチ、 32…トレンチ充填剤、 33…記憶ノード絶縁膜、 34…カラー酸化膜、 35…パッドシリコン酸化膜(SiO2 膜)、 36…パッドシリコン窒化膜(Si3 N4 膜)、 37…開口部、 38…流動可能な酸化膜、 39…ARC膜、 40…レジスト膜、 41…浅いトレンチ。DESCRIPTION OF SYMBOLS 10 ... board | substrate, 11 ... 1st insulating film, 12 ... conductive wiring, 13 ... 2nd insulating film, 14 ... anti-reflection coating film (ARC film), 15 ... resist film, 16 ... opening part, 17 ... contact Holes: 18: Flowable oxide film, 19: Anti-reflective coating film (ARC film), 20: Resist film, 21: Opening, 22: Trench, 23: Adhesion / barrier layer, 24: Tungsten layer, 30: Silicon semiconductor substrate, 31 deep trench, 32 trench filling material, 33 storage node insulating film, 34 color oxide film, 35 pad silicon oxide film (SiO 2 film), 36 pad silicon nitride film (Si 3 N) 4 film), 37: opening, 38: flowable oxide film, 39: ARC film, 40: resist film, 41: shallow trench.
Claims (7)
を形成し、 上記第1の膜の上部に第2の膜を形成して上記第1の開
口部を充填し、 上記第2の膜上にマスク層を形成し、 上記マスク層をマスクとして使用して上記第1及び第2
の膜がほぼ同じ速度でエッチングされる条件の第1のエ
ッチングプロセスによって上記第1の膜及び第2の膜を
エッチングして上記第1の膜に第2の開口部を形成し、 上記第1の開口部において上記第2の膜が上記第1の膜
よりも速い速度でエッチングされる条件の第2のエッチ
ングプロセスによって上記第2の膜の残りの部分をエッ
チング除去することを特徴とする半導体装置の製造方
法。A first opening formed in a first film made of an insulating film; a second film formed on an upper portion of the first film to fill the first opening; Forming a mask layer on the second film, using the mask layer as a mask,
The first film and the second film are etched by a first etching process under the condition that the film is etched at substantially the same rate to form a second opening in the first film; A second etching process under which the second film is etched at a higher speed than the first film at the opening of the second film, and the remaining portion of the second film is etched away. Device manufacturing method.
特徴とする請求項1記載の半導体装置の製造方法。2. The method according to claim 1, wherein the first film is a TEOS film.
able oxide)であることを特徴とする請求項1記載の半
導体装置の製造方法。3. The method according to claim 1, wherein the second film is a flowable oxide film.
2. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is capable oxide.
イオンエッチング(RIE)プロセスであることを特徴
とする請求項1記載の半導体装置の製造方法。4. The method according to claim 1, wherein the first etching process is a reactive ion etching (RIE) process.
方がコンタクト孔であり、他方がトレンチであり、上記
トレンチの幅が上記コンタクト孔の幅よりも広く形成さ
れることを特徴とする請求項1記載の半導体装置の製造
方法。5. One of the first opening and the second opening is a contact hole, and the other is a trench, wherein the width of the trench is formed larger than the width of the contact hole. 2. The method of manufacturing a semiconductor device according to claim 1, wherein
を形成し、 上記第1の膜の上部に第2の膜を形成して上記第1の開
口部を充填し、 上記第2の膜上にマスク層を形成し、 上記マスク層をマスクとして使用して上記第1及び第2
の膜がほぼ同じ速度でエッチングされる条件の第1のエ
ッチングプロセスによって上記第1の膜及び第2の膜を
エッチングして第2の開口部を形成し、 上記第2の膜が上記第1の膜のエッチング速度よりも速
い速度でエッチングされる条件の第2のエッチングプロ
セスによって上記第1の開口部における上記第2の膜の
残りの部分をエッチングし、 上記第1及び第2の開口部を導電材料で充填することを
特徴とする半導体装置の製造方法。6. A first opening formed in a first film made of an insulating film, a second film is formed above the first film, and the first opening is filled. Forming a mask layer on the second film, using the mask layer as a mask,
The first film and the second film are etched by a first etching process under the condition that the film is etched at substantially the same rate to form a second opening, and the second film is formed of the first film. Etching the remaining portion of the second film in the first opening by a second etching process under a condition that the etching is performed at a higher speed than the etching speed of the film of the first and second openings; Filling a semiconductor device with a conductive material.
に分離するために半導体基板に浅いトレンチ分離構造を
形成する半導体層装置の製造方法において、 1以上のパッド膜の上部に流動可能な酸化膜を形成し
て、上記1以上のパッド膜中に形成されて上記深いトレ
ンチキャパシタの上部表面の少なくとも1部分を露出す
る開口を充填し、 上記流動可能な酸化膜上にパターン化されたレジスト膜
を形成し、 上記レジスト膜をマスクとして使用して上記流動可能な
酸化膜をエッチングし、 上記レジスト膜をマスクとして使用して上記1以上のパ
ッド膜、上記半導体基板及び上記深いトレンチキャパシ
タをエッチングして浅いトレンチを形成し、その際に、
エッチングされた流動可能な酸化膜の残っている部分を
マスクとして使用し、 上記浅いトレンチを絶縁材料で充填することを特徴とす
る半導体装置の製造方法。7. A method of manufacturing a semiconductor layer device for forming a shallow trench isolation structure in a semiconductor substrate to isolate adjacent deep trench capacitors from each other, comprising: forming a flowable oxide film on one or more pad films. Filling an opening formed in the one or more pad films and exposing at least a portion of an upper surface of the deep trench capacitor; forming a patterned resist film on the flowable oxide film; Etching the flowable oxide film using the resist film as a mask; etching the one or more pad films, the semiconductor substrate and the deep trench capacitor using the resist film as a mask to form a shallow trench; To form,
A method for manufacturing a semiconductor device, characterized in that the shallow trench is filled with an insulating material by using a remaining portion of the etched flowable oxide film as a mask.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US989859 | 1997-12-12 | ||
US08/989,859 US5883006A (en) | 1997-12-12 | 1997-12-12 | Method for making a semiconductor device using a flowable oxide film |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH11233618A true JPH11233618A (en) | 1999-08-27 |
Family
ID=25535539
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10345630A Pending JPH11233618A (en) | 1997-12-12 | 1998-12-04 | Manufacture of semiconductor device |
Country Status (2)
Country | Link |
---|---|
US (1) | US5883006A (en) |
JP (1) | JPH11233618A (en) |
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