JPH06177236A - Manufacture of element isolation film of trench structure - Google Patents

Abstract

PURPOSE: To simultaneously form a flattened element separation film on the trenches of different widths without performing an additional masking process by forming a CVD(chemical vapor deposition) oxidized film at the upper part of the trench formed on a semiconductor substrate and then forming an etching barrier layer in the peripheral area of low topology of the CVD oxidized film. CONSTITUTION: The trenches 5a, 5b and 5c of the different widths are formed on the semiconductor substrate 1. The CVD oxidized film 7 is formed thick and the upper part and width of a silicon nitride film pattern 4' are respectively flattened with the upper part of the wide trench 5a. Thereafter, the etching barrier layer 8 is piled up at the upper part. Thereafter, a photosensitive film 9 is formed flat and the photosensitive film 9 is etched back so as to expose the etching barrier layer 8 of the area of high topology. The etching barrier layer 8 remaining at the part of the low topology is masked and the CVD oxidized film 7 is etched. Element separation masks 2' and 3' are etched for the etching barrier layer 8 and the remaining CVD oxidized film 7 is etched.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a device isolation film having a trench structure.

[0002]

2. Description of the Related Art Generally, in a manufacturing process of a highly integrated semiconductor device, a device isolation film for electrically insulating devices from each other is formed by LOCOS (Local Oxidatio).
n of Silicon) technology has been widely used, but LO
The COS series of technologies are based on the bird's beak phenomenon in which an oxide film penetrates into the active region and the severe topology (Topol).
ogy) and step coverage (Ste
p Coverage) deteriorates, which causes lithography (Lit
The difficulty of the hography process increases, or the stress generated during the oxidization process causes a defect, which deteriorates the characteristics of the gate oxide.
Therefore, the higher the degree of integration, the more restricted the use of the LOCOS technology will be.

For this reason, many techniques for forming an element isolation film having a trench structure, which has no bird's beak, is excellent in flatness, and has no possibility of causing stress due to oxidation, have been studied. There is also a problem with the manufacturing technology of.

That is, a method for forming a device isolation film having a trench structure is IEDM 84,580 pages / IEDM 87,732 pages / IEDM.
Although it was announced on pages 89, 62, etc., when the device isolation film was formed at the same time in a narrow trench and a wide trench at the same time, this announced technique was performed after forming a separate mask on the upper part of the wide trench. , An etching process for flattening is performed.

However, since the number of steps is increased by performing the additional mask step, the overall number of steps is increased and the productivity is lowered, and the mask type is limited to a specific semiconductor element. When applied to a semiconductor device having a design rule, a separate mask must be manufactured and used.

The present invention provides a method for manufacturing a planarized device isolation layer without performing an additional masking process when forming a device isolation layer having a narrow trench and a wide trench at the same time. With the goal.

[0007]

A method of manufacturing an element isolation film having a trench structure according to the present invention is a method of manufacturing a semiconductor element, including the steps of: (a) forming an element isolation mask on a substrate; and (b) exposing. Etching the formed substrate to form a number of trenches having different widths, and (c) CVD (Chemical Vapor Deposit) on the substrate and on the element isolation mask.
ion) method to deposit a thick CVD oxide film, and (d)
A step of forming an etching barrier layer on the CVD oxide film; (e) a step of applying a photosensitive film on the etching barrier layer to form a flat surface; and (f) a topology.
a step of etching back the photosensitive film so that the etching barrier layer in a region having a high (topology) is exposed; and (g) a step of etching the exposed etching barrier layer to remove the remaining photosensitive film, h) a step of etching the CVD oxide film exposed until the element isolation mask is exposed by using the etching barrier layer remaining in the lower topography as a mask, and (i) the etching barrier layer and the element isolation mask. Each etching step, (j) CVD
Etching the oxide film to the surface of the substrate and leaving only the trench
A step of forming an element isolation film where the CVD oxide film remains,
Equipped with.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the accompanying drawings.

FIGS. 1A to 3I are sectional views showing a process of forming an element isolation film having a trench structure according to the present invention.

First, a silicon oxide film (2) having a thickness of 100 to 300 Å is formed on a semiconductor substrate (1).
Is formed, and a silicon nitride film (3) having a thickness of 1000 to 3000 angstrom is formed thereon by CVD (Chemical Vapor).
Deposition) method is applied, a photoresist (4) is applied thereon, and then a photoresist pattern (4 ′) is formed by exposure and phenomenon process using a mask (FIG. 1).
(See (a)).

Next, using the photoresist pattern (4 ') as an element isolation mask, the silicon nitride film (3), the silicon oxide film (2) and the semiconductor substrate (1) are formed to a certain depth by a dry etching method. Then, dry etching is sequentially performed to form a silicon nitride film pattern (3 ') and a first silicon oxide film pattern (2'), and then a plurality of trenches (5a, 5b, 5c) having different widths are formed (FIG. 1). (See (b)). After the silicon nitride film pattern (3 ') and the silicon oxide film pattern (2') are formed in the above process and the first photoresist pattern (4 ') is removed, the silicon nitride film pattern (3') and the silicon oxide film pattern (3 ') are removed. It is apparent that the exposed semiconductor substrate (1) may be etched using the film pattern (2 ') as an element isolation mask to form a plurality of trenches (5a, 5b, 5c) having different widths.

The above trenches (5a, 5b, 5c) can be formed by an anisotropic etching method, as shown in FIG.
It is preferable that the boundary between the lower surface and the wall surface of the trench is rounded as shown in FIG.

The depth of the above-mentioned trenches (5a, 5b, 5c) is 0.4 to 0.5 μm, but they can be formed deeper according to the requirements of the device. The wide trench (5a) is mainly formed in the peripheral area (A), and the narrow trench (5b, 5c) is mainly formed in the memory cell area (B).

Next, the photoresist pattern (4 ') is removed, and a thermal oxide film (6) is formed on the surface of the trenches (5a, 5b, 5c) by 100 to 300 angstroms in order to remove the damage on the trench surface. To be formed (see FIG. 1C).

After the step shown in FIG. 1 (c), a CVD oxide film (7) such as BPSG (borophosphosilicate glass), P is formed.
SG (phospho silicate glass) or TEOS (tetra ethyle
A thick ortho silicate film is formed to be flat on the upper portion of the silicon nitride film pattern 4'and the upper portion of the wide trench 5a, and an etching barrier layer (Etch-barrier layer) is formed on the upper portion. (8), for example, a polysilicon layer (8) is deposited (see FIG. 2D).

The CVD oxide film (7) is formed to have a thickness higher than that of the silicon nitride film pattern (3 ').
It is about 7,000 to 9,000 angstroms. Generally, the CVD oxide film is formed thicker than the sum of the depth of the trench and the thickness of the element isolation mask (about 2000 angstroms or less).

After the step shown in FIG. 2D, a photoresist layer 9 is applied to form a flat surface (FIG. 2E).
reference).

The photoresist layer (9) has a thickness of about 12,000 to 20,000 angstroms, and multicoating (3 to 5 times is applied in order to enhance the flattening effect). A multi-coating method can also be used.

Subsequently, the photoresist layer (9) described above is used.
RIE (Reactive Ion Etching) method to etch back (Etc
h-back) and high-topology polysilicon layer (8)
Are fully exposed, leaving 1,000 to 2,000 angstroms of photoresist layer (9) over the low-topology polysilicon layer (8) (see FIG. 2 (f)).

After the step of FIG. 2 (f), the photoresist layer (9) remaining after the polysilicon layer (8) in the exposed cell region (B) is removed by dry or wet etching.
Are removed to expose the polysilicon layer (8) in the peripheral area (A) having a low step (see FIG. 3G).

After the step of FIG. 3 (g), the CVD oxide film (7) in the cell area (B) is etched back by using the polysilicon layer (8) remaining in the area having a low step as a mask to etch the silicon. The upper surface of the nitride film pattern (3 ′) is exposed (see FIG. 3 (h)).

At this time, since the polysilicon layer (8) acts as a mask in the peripheral area (A), the CVD oxide film (7) does not lose its thickness.

After the step of FIG. 3H, the polysilicon layer (8) in the peripheral area (A) is removed by dry etching.
After etching the silicon nitride film pattern (3 ') and the silicon oxide film pattern (2'), the remaining CVD oxide film (7) is etched to be flat with the upper surface of the semiconductor substrate (1) to form a trench. A large number of device isolation films (1) filled with a CVD oxide film (7) inside (5a, 5b, 5c)
0a, 10b, 10c) are formed (see FIG. 3 (i)).

[0024]

As described above, according to the present invention, a uniform thickness is formed in a narrow trench region (cell region) and a wide trench region (peripheral region) in the process of manufacturing an element isolation film having a trench structure. In forming the element isolation film provided,
The mask process need not be added.

Further, by using the etching barrier layer, all chips of the wafer can be made uniform, and the uniformity between the wafers is improved.

[Brief description of drawings]

FIG. 1 is a process drawing of forming an element isolation film having a trench structure according to the present invention.

FIG. 2 is a process drawing of forming an isolation film having a trench structure according to the present invention.

FIG. 3 is a process drawing of forming an isolation film having a trench structure according to the present invention.

[Explanation of symbols]

1 ... Semiconductor substrate, 2 ... Silicon oxide film, 2 '... Silicon oxide film pattern, 3 ... Silicon nitride film, 3' ... Silicon nitride film pattern, 4 ... Photoresist layer, 4 '... Photoresist pattern, 5a, 5b, 5c ... trench, 6 ...
Thermal oxide film, 7 ... CVD oxide film.

Claims (6)

[Claims] 1. A method of manufacturing a semiconductor device, the method comprising: forming an element isolation mask on a substrate; and etching the exposed substrate to form a plurality of trenches having different widths. The CVD (Chemical V
apor Deposition) method to deposit a thick CVD oxide film, a step of forming an etching barrier layer on the CVD oxide film, and a photoresist film on the etching barrier layer to form a flat surface. And a step of etching back the photosensitive film so that the etching barrier layer in a region having a high topology is exposed, and the photosensitive film remaining after etching the exposed etching barrier layer. A step of removing, and a step of etching the CVD oxide film exposed until the element isolation mask is exposed by using the etching barrier layer remaining in a low topology as a mask, the etching barrier layer and the Etching the device isolation mask, etching the CVD oxide film to the surface of the substrate, Method for manufacturing a device isolation film of a trench structure and a step of forming an isolation layer that remains of film. 2. The method for manufacturing an element isolation film having a trench structure according to claim 1, wherein the element isolation mask has a laminated structure of a silicon oxide film pattern and a silicon nitride film pattern. 3. The CVD oxide film is TEOS (tetra ortho
2. The method for manufacturing an isolation film having a trench structure according to claim 1, which is formed on an ethyl silicate) layer, a PSG (phospho silicate glass) layer or a BPSG (boro phospho silicate glass) layer. 4. The method of claim 1, wherein the CVD oxide film is deposited thicker than the sum of the depth of the trench and the thickness of the device isolation mask. 5. The method according to claim 1, wherein the etching barrier layer is formed of a polysilicon layer. 6. The device according to claim 1, wherein when forming a plurality of trenches having different widths in the cell region and the peripheral region of the substrate, the trench formed in the peripheral region has a large area. Method for manufacturing separation membrane.