KR100318255B1 - Device Separation Method in Semiconductor Devices - Google Patents
Device Separation Method in Semiconductor Devices Download PDFInfo
- Publication number
- KR100318255B1 KR100318255B1 KR1019980025780A KR19980025780A KR100318255B1 KR 100318255 B1 KR100318255 B1 KR 100318255B1 KR 1019980025780 A KR1019980025780 A KR 1019980025780A KR 19980025780 A KR19980025780 A KR 19980025780A KR 100318255 B1 KR100318255 B1 KR 100318255B1
- Authority
- KR
- South Korea
- Prior art keywords
- film
- trench
- forming
- oxide film
- etch stop
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 238000000926 separation method Methods 0.000 title description 2
- 238000002955 isolation Methods 0.000 claims abstract description 34
- 238000005530 etching Methods 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 238000000151 deposition Methods 0.000 claims abstract description 6
- 150000004767 nitrides Chemical class 0.000 claims description 31
- 238000000034 method Methods 0.000 claims description 16
- 238000000137 annealing Methods 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 2
- 230000001590 oxidative effect Effects 0.000 claims 1
- 238000000059 patterning Methods 0.000 claims 1
- 238000009413 insulation Methods 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- 241000293849 Cordylanthus Species 0.000 description 1
- 230000003064 anti-oxidating effect Effects 0.000 description 1
- 230000002180 anti-stress Effects 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000008595 infiltration Effects 0.000 description 1
- 238000001764 infiltration Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Element Separation (AREA)
Abstract
본 발명은 반도체 소자의 소자 분리 방법에 관한 것으로, 개시된 본 발명은, 반도체 기판에 트랜치 형성용 패턴을 형성하는 단계, 상기 트랜치 형성용 패턴을 마스크로 하여 사이즈가 상이한 트랜치를 형성하는 단계, 상기 트랜치가 형성된 반도체 기판 상에 매립용 산화막을 증착하는 단계, 상기 매립용 산화막 상부에 에칭 정지용 막을 증착하는 단계, 상기 에칭 정지용막 상부에 평탄화막을 형성하는 단계, 상기 평탄화막을 상기 에칭 정지용막의 최상부가 노출될때까지 에치백하는 단계, 상기 노출된 에칭 정지용 막을 제거하는 단계, 상기 에칭 정지용막으로 노출된 매립용 산화막과 평탄화 막을, 상기 평탄화막이 완전히 제거될때까지 에치백하는 단계, 상기 에칭 정지용 막을 제거하는 단계, 상기 매립용 산화막을 상기 트랜치 형성용 패턴이 노출되도록 에치백하는 단계, 및 상기 트랜치 형성용 패턴을 제거하는 단계를 포함하는 구성된다.The present invention relates to a device isolation method of a semiconductor device, the present invention is to form a trench forming pattern on the semiconductor substrate, forming a trench having a different size using the trench forming pattern as a mask, the trench Depositing a buried oxide film on the semiconductor substrate on which the buried oxide film is formed, depositing an etch stop film on the buried oxide film, forming a planarization film on the etch stop film, and exposing the top of the etch stop film. Etching back, removing the exposed etch stop film, etching the buried oxide film and the planarization film exposed to the etch stop film until the planarization film is completely removed, removing the etch stop film, The trench forming pattern is exposed to the buried oxide film. Is the step of etching back the lock, and the configuration including the step of removing the forming the trench pattern.
Description
본 발명은 반도체 장치의 소자 분리 방법에 관한 것으로, 보다 구체적으로는 사이즈가 상이한 트랜치 구조의 소자 분리 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device isolation method of a semiconductor device, and more particularly to a device isolation method having a trench structure having a different size.
반도체 기술의 진보와 더불어 더 나아가서는 반도체 소자의 고속화, 고집적화가 진행되고 있고, 이에 수반해서 패턴에 대한 미세화의 필요성이 점점 높아지고 있으며, 패턴의 칫수도 고정밀화가 요구되고 있다. 이는 반도체 소자에 있어서, 넓은 영역을 차지하는 소자 분리 영역에도 적용된다.In addition to the advances in semiconductor technology, high speed and high integration of semiconductor devices is progressing, and along with this, the necessity of miniaturization of patterns is increasing, and the size of patterns is also required to be highly accurate. This also applies to device isolation regions that occupy a wide area in semiconductor devices.
현재의 반도체 장치의 소자 분리로는 로코스(LOCOS) 소자 분리막이 대부분 이용된다. 이 로코스 방식의 소자 분리막은 기판을 선택적으로 국부 산화하여, 얻어진다.LOCOS device isolation films are mostly used for device isolation of current semiconductor devices. This LOCOS device isolation film is obtained by selectively localizing a substrate.
그러나, 상기 로코스 방식의 소자 분리막은 그 가장자리 부분에 새부리 형상의 버즈빅이 발생하여, 소자 분리막의 면적을 증대시키면서 누설 전류를 발생시키는 단점을 갖는다.However, the LOCOS isolation layer has a drawback in which a bird-shaped bird's beak is generated at an edge thereof, thereby generating a leakage current while increasing the area of the isolation layer.
따라서, 종래에는 적은 폭을 가지며, 우수한 소자 분리 특성을 갖는 STI(shallow trench isolation) 방식의 소자 분리막이 제안되었다.Accordingly, a device isolation film having a shallow trench isolation (STI) method having a small width and excellent device isolation characteristics has been proposed.
종래의 STI 소자 분라막은 도 1에 도시된 바와 같이, 반도체 기판(1)상에 소자 분리 예정 영역이 노출되도록, 산화방지용 패턴(도시되지 않음)을 형성한다.As shown in FIG. 1, the conventional STI device separator forms an anti-oxidation pattern (not shown) on the semiconductor substrate 1 so that the device isolation region is exposed.
여기서, 소자 분리 예정 영역은 소자와 소자 사이일수도 있고, 웰 사이의 영역일 수도 있다. 이때, 웰 사이의 소자 분리 예정 영역은 소자와 소자의 사이의 소자 분리 영역보다 큰 면적을 차지한다.In this case, the device isolation region may be between the device and the device, or may be a region between the wells. At this time, the device isolation region between the wells occupies a larger area than the device isolation region between the device and the device.
그다음, 노출된 반도체 기판(1)을 소정 깊이만큼 에칭하여, 트랜치를 형성한다. 이어서, 트랜치 내부가 충분히 매립되도록 산화막을 증착한다음, 기판 표면이 노출되도록 에치백 또는 CMP(chemical mechanical polishing)공정을 진행한다. 이에따라, 트랜치내에 절연막을 충진시키어, 소자 분리막(2)을 형성한다.Then, the exposed semiconductor substrate 1 is etched to a predetermined depth to form a trench. Subsequently, an oxide film is deposited to sufficiently fill the inside of the trench, and then an etch back or chemical mechanical polishing (CMP) process is performed to expose the substrate surface. As a result, an insulating film is filled in the trench to form the device isolation film 2.
그러나, 상기와 같은 종래의 트랜치 소자 분리막을 형성하는데 있어서 다음과 같은 문제점이 있다.However, there are the following problems in forming the conventional trench device isolation layer as described above.
종래기술에 있어서는, 상기한 소자 분리막은 소자와 소자 사이를 아이솔레이션시키는 트랜치 소자 분리막(이하, 인트라 웰 트랜치)과 웰과 웰사이를 아이솔레이션하는 트랜치 소자 분리막(이하, 인터 웰 트랜치)은 그 사이즈가 다른데도 불구하고 공정을 단순화하기 위하여 동시에 형성된다.In the prior art, the device isolation layer may have a trench device isolation layer (hereinafter, referred to as an intra well trench) for isolating between devices, and a trench device isolation layer (hereinafter referred to as an inter well trench) for isolating between wells and wells. Nevertheless, they are formed simultaneously to simplify the process.
따라서, 절연막을 에치백하여 트랜치내에 매립시키는 공정시, 인트라 웰 부분의 절연막 에치백(또는 CMP) 속도와, 인터 웰 트랜치 부분의 절연막 에치백(또는 CMP) 속도가 상이하여, 인트라 웰 트랜치와 인터 웰 트랜치내에 절연막이 매립되는 정도가 서로 다르게 된다.Therefore, during the process of etching back the insulating film and filling it into the trench, the insulating film etchback (or CMP) speed of the intra well portion and the insulating film etchback (or CMP) speed of the interwell trench portion are different from each other. The degree of embedding of the insulating film in the well trench is different.
이때, 트랜치내에 절연막이 매립되는 정도는 소자 분리막의 절연특성을 결정하므로써, 완전하게 매립되지 않으면, 소자 분리막 절연 특성이 저하된다.At this time, the degree to which the insulating film is embedded in the trench determines the insulating property of the device isolation film, and if not completely filled, the device isolation film insulation property is reduced.
따라서, 본 발명은 상기 종래기술의 제반 문제점을 해결하기 위하여 안출한 것으로서, 버즈빅이 없으며, 우수한 절연 특성을 갖는 반도체 장치의 소자 분리 방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a device separation method of a semiconductor device, which has been devised in order to solve the above-mentioned problems of the prior art, which is free of Buzzvik and has excellent insulation characteristics.
도 1은 종래의 반도체 장치의 소자 분리막을 보인 단면도.1 is a cross-sectional view showing a device isolation film of a conventional semiconductor device.
도 2a 내지 도 2h는 본 발명에 따른 반도체 장치의 소자 분리막을 형성하기 위한 각 제조 공정별 단면도.2A to 2H are cross-sectional views of respective manufacturing processes for forming an isolation layer of a semiconductor device according to the present invention.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
11 - 반도체 기판 12 - 패드 산화막11-semiconductor substrate 12-pad oxide film
13 - 제 1 질화막 14 - HDP 산화막13-1st nitride film 14-HDP oxide film
15 - 제 2 질화막 16 - SOG막15-second nitride film 16-SOG film
상기 목적을 달성하기 위한 본 발명은, 반도체 기판에 트랜치 형성용 패턴을 형성하는 단계; 상기 트랜치 형성용 패턴을 마스크로 하여 크기가 서로 다른 트랜치를 형성하는 단계; 상기 트랜치가 형성된 반도체 기판 상에 고밀도플라즈마산화막을 증착하는 단계; 상기 고밀도플라즈마산화막상부에 에칭 정지용 질화막을 증착하는 단계; 상기 에칭 정지용 질화막 상부에 평탄화용 SOG막을 형성하는 단계; 상기 평탄화용 SOG막을 상기 에칭정지용 질화막의 최상부가 노출될때까지 에치백하는단계; 상기 노출된 에칭 정지용 질화막을 제거하는 단계; 상기 에칭 정지용 질화막으로 노출된 고밀도 플라즈마산화막과 평탄화용 SOG막을, 상기 평탄화용 SOG막이 완전히 제거될때까지 에치백하는 단계; 상기 에칭 정지용 질화막을 제거하는 단계; 상기 매립용 고밀도플라즈마산화막을 상기 트랜치 형성용 패턴이 노출되도록 에치백하는 단계; 및 상기 트랜치 형성용 패턴을 제거하는 단계를 포함하는 것을 특징으로 한다.The present invention for achieving the above object, forming a trench forming pattern on a semiconductor substrate; Forming trenches having different sizes using the trench formation pattern as a mask; Depositing a high density plasma oxide film on the trench on which the trench is formed; Depositing an etch stop nitride film on the high density plasma oxide film; Forming a planarization SOG film on the etch stop nitride film; Etching the planarization SOG film until the top of the etch stop nitride film is exposed; Removing the exposed etch stop nitride film; Etching back the high density plasma oxide film and the planarization SOG film exposed to the etch stop nitride film until the planarization SOG film is completely removed; Removing the etch stop nitride film; Etching the buried high density plasma oxide layer to expose the trench formation pattern; And removing the trench forming pattern.
본 발명에 의하면, 사이즈가 상이한 트랜치내에 HDP 산화막을 용이하게 매립할 수 있어, 절연 특성을 확보할 수 있다.According to the present invention, the HDP oxide film can be easily embedded in trenches of different sizes, and the insulating properties can be secured.
아울러, 트랜치 구조를 이용하므로, 버즈 빅이 발생되지 않는다.In addition, since the trench structure is used, buzz big does not occur.
(실시예)(Example)
이하 본 발명에 따른 반도체장치의 소자분리방법의 바람직한 실시예를 첨부한 도면에 의거하여 자세히 설명하도록 한다.Exemplary embodiments of a device isolation method of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2h는 본 발명에 따른 반도체 장치의 소자 분리막을 형성하기 위한 각 제조 공정별 단면도이다.2A to 2H are cross-sectional views of respective manufacturing processes for forming the device isolation film of the semiconductor device according to the present invention.
본 발명에 따른 반도체장치의 소자분리방법은, 먼저, 도 2a에 도시된 바와같이, 반도체 기판(11) 상부에 스트레스 방지용 패드 산화막(12)을 50 내지 100Å 정도 형성한다음, 패드 산화막(12) 상에 산화 방지용 제1 질화막(13)을 1000 내지 2000Å 정도로 형성한다. 이때, 패드 산화막(12)은 열산화 방식 또는 화학 기상 증착 방식으로 형성할 수 있으며, 상기 제 1 질화막(13)의 높이는 이후 소자 분리막이 기판(1) 상부로 돌출되는 높이를 결정한다.In the device isolation method of the semiconductor device according to the present invention, first, as shown in FIG. 2A, the anti-stress pad oxide film 12 is formed on the semiconductor substrate 11 at about 50 to 100 kPa, and then the pad oxide film 12 is formed. The first nitride film 13 for prevention of oxidation is formed on about 1000-2000 micrometers. In this case, the pad oxide layer 12 may be formed by a thermal oxidation method or a chemical vapor deposition method, and the height of the first nitride layer 13 determines a height at which the device isolation layer protrudes above the substrate 1.
그다음, 제 1 질화막(13)과 패드 산화막(12)을 소자 분리 예정 영역이 노출되도록 패터닝한다음 패터닝된 제 1 질화막(13)과 패드 산화막(12)을 마스크로하여, 노출된 반도체 기판(1)을 소정 깊이 예를들어 2000 내지 3000Å 정도로 에칭하여 트랜치(미도시)를 형성한다.Next, the first nitride film 13 and the pad oxide film 12 are patterned to expose the device isolation region, and then the exposed semiconductor substrate 1 is formed using the patterned first nitride film 13 and the pad oxide film 12 as a mask. ) Is etched to a predetermined depth, for example 2000 to 3000 microns, to form a trench (not shown).
이어서, 트랜치 내벽 모서리 부분에 전계 집중을 방지하고, 트랜치 내벽의 데미지를 방지하기 위하여, 결과물 표면에 1050 내지 1100℃의 고온 산화방식에 의하여, 150Å정도의 희생 산화막(미도시)을 증착한다음, 이를 제거한다. 이때, 트랜치 내벽의 모서리 부분이 완만해진다.Subsequently, in order to prevent electric field concentration at the edge portion of the trench inner wall and to prevent damage to the trench inner wall, a sacrificial oxide film (not shown) of about 150 Hz is deposited on the resultant surface by a high temperature oxidation method of 1050 to 1100 ° C. Remove it. At this time, the edge portion of the trench inner wall becomes smooth.
그다음, 결과물 전면에 공간 매립 특성이 우수한 매립용 산화막, 예를들어, HDP(high density plasma) 산화막(14)을 상기 트랜치가 충분히 매립되도록 증착한다. 더욱 바람직하게는 트랜치를 매립하면서, 제 1 질화막(13) 상부에도 어느 정도의 두께가 존재할 수 있을만큼의 충분한 두께로 형성한다.Then, a buried oxide film, for example, a high density plasma (HDP) oxide film 14 having excellent space filling characteristics is deposited on the entire surface of the resultant so that the trench is sufficiently buried. More preferably, the trench is filled with a sufficient thickness so that a certain thickness may exist on the first nitride film 13.
이어서, 도 2b에 도시된 바와 같이, HDP 산화막(14) 상부에 에칭 정지용 제 2 질화막(15)을 형성한다. 이때, 제 2 질화막(15)은 화학 기상 증착 방식으로 형성될 수 있다.Subsequently, as shown in FIG. 2B, a second nitride film 15 for stopping etching is formed on the HDP oxide film 14. In this case, the second nitride film 15 may be formed by chemical vapor deposition.
그다음, HDP 산화막(14) 상부에 평탄화막인 SOG(spin on glass)막(16)을 형성한다.Next, a spin on glass (SOG) film 16 that is a planarization film is formed on the HDP oxide film 14.
이어서, 도 2c에 도시된 바와 같이, SOG막(16)과 HDP 산화막(14)간의 에칭 속도차를 줄이기 위하여, 질소(N2) 분위기 하에서 어닐링 공정을 실시한다.Subsequently, as shown in FIG. 2C, an annealing process is performed under a nitrogen (N 2) atmosphere in order to reduce the etching rate difference between the SOG film 16 and the HDP oxide film 14.
그다음, SOG막(16)을 상기 제 2 질화막(15)의 최상부 즉, 가장 높은 단차부에 존재하는 제 2 질화막(15)이 노출될때까지 에치백하여, 결과물을 평탄하게 만든다.Then, the SOG film 16 is etched back until the second nitride film 15 existing at the top of the second nitride film 15, i.e., the highest stepped portion, is exposed, thereby making the resultant flat.
이어서, 도 2d에서와 같이, 노출된 제 2 질화막(15)만을 선택적으로 제거한다.Subsequently, as shown in FIG. 2D, only the exposed second nitride film 15 is selectively removed.
그다음, 도 2e에 도시된 바와 같이, 에치백된 SOG막(16a)과 노출된 HDP 산화막(14)을 상기 에치백된 SOG막(16a)이 모두 제거될때까지 2차적으로 에치백한다. 이때, 상기에서와 같은 고온 열처리 공정에 의하여, SOG막(16a)은 HDP 산화막(14)과 거의 유사한 에칭 속도를 가지므로, 서로 동일 두께만큼 에치백된다.Then, as shown in FIG. 2E, the etched back SOG film 16a and the exposed HDP oxide film 14 are second etched back until both of the etched back SOG film 16a are removed. At this time, by the high temperature heat treatment process as described above, since the SOG film 16a has an etching rate almost similar to that of the HDP oxide film 14, it is etched back by the same thickness.
이어서, 도 2f에 도시된 바와 같이, 제 2 질화막(15)을 뜨거운 H3PO4용액에 담그어 제거한다.Subsequently, as shown in FIG. 2F, the second nitride film 15 is immersed in a hot H 3 PO 4 solution and removed.
그다음, SOG막(16a)에 의한 수분 침투를 방지하고, 이후 클리닝 공정시 산화막이 일부 유실되는 것을 방지하기 위하여, 고온의 질소 분위기에서 어닐링 공정을 진행하여, 상기 HDP 산화막(14)을 고밀도화한다.Then, in order to prevent moisture infiltration by the SOG film 16a and to prevent partial loss of the oxide film during the cleaning process, the annealing process is performed in a high temperature nitrogen atmosphere to increase the density of the HDP oxide film 14.
이어서, 도 2g에 도시된 바와 같이, 제 1 질화막(13)이 노출되도록 HDP 산화막(14)을 드라이 에칭한다. 바람직하게는 HDP 산화막(14)은 제 1 질화막(13)의 높이에 대하여 소정 깊이만큼 오버 에칭되면서, 기판(11) 표면보다는 높도록 형성된다.Next, as shown in FIG. 2G, the HDP oxide film 14 is dry etched to expose the first nitride film 13. Preferably, the HDP oxide film 14 is formed to be higher than the surface of the substrate 11 while being overetched by a predetermined depth with respect to the height of the first nitride film 13.
그다음, 도 2h에 도시된 바와 같이, 패드 산화막(12), 제 1 질화막(13)을 공지의 방식으로 제거하여, 소자 분리막(17)을 완성한다.Then, as shown in FIG. 2H, the pad oxide film 12 and the first nitride film 13 are removed in a known manner to complete the device isolation film 17.
이상에서 자세히 설명된 바와 같이, 본 발명에 의하면, 크기가 각각 다른 트랜치내에 HDP 산화막을 용이하게 매립할 수 있어, 절연 특성을 확보할 수 있다.As described in detail above, according to the present invention, it is possible to easily embed the HDP oxide film in trenches having different sizes, thereby ensuring insulation characteristics.
또한, 본 발명은 트랜치 구조를 이용하므로써, 버즈 빅이 발생되지 않는다.In addition, the present invention does not generate buzz big by using a trench structure.
기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980025780A KR100318255B1 (en) | 1998-06-30 | 1998-06-30 | Device Separation Method in Semiconductor Devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980025780A KR100318255B1 (en) | 1998-06-30 | 1998-06-30 | Device Separation Method in Semiconductor Devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20000004348A KR20000004348A (en) | 2000-01-25 |
| KR100318255B1 true KR100318255B1 (en) | 2002-04-22 |
Family
ID=19542168
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019980025780A KR100318255B1 (en) | 1998-06-30 | 1998-06-30 | Device Separation Method in Semiconductor Devices |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100318255B1 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR940004779A (en) * | 1992-08-31 | 1994-03-16 | 김주용 | Device isolation region formation method of semiconductor device using trench technology |
-
1998
- 1998-06-30 KR KR1019980025780A patent/KR100318255B1/en not_active IP Right Cessation
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR940004779A (en) * | 1992-08-31 | 1994-03-16 | 김주용 | Device isolation region formation method of semiconductor device using trench technology |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20000004348A (en) | 2000-01-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100428805B1 (en) | Structure of Trench Isolation and Method of Forming The Same | |
| US6277709B1 (en) | Method of forming shallow trench isolation structure | |
| KR100239453B1 (en) | Method of forming a device isolation film of semiconductor device | |
| KR100224700B1 (en) | Isolation method of semiconductor device | |
| US5981402A (en) | Method of fabricating shallow trench isolation | |
| KR20020071063A (en) | Dent free trench isolation structure and method for fabricating the same | |
| KR100251280B1 (en) | Sti method | |
| US6265283B1 (en) | Self-aligning silicon oxynitride stack for improved isolation structure | |
| KR100564550B1 (en) | a semiconductor device comprising a trench type isolation film and method for manufacturing the same | |
| KR100318255B1 (en) | Device Separation Method in Semiconductor Devices | |
| US6153479A (en) | Method of fabricating shallow trench isolation structures | |
| KR100272274B1 (en) | Method for isolating element in semiconductor device | |
| KR100979230B1 (en) | The method for forming shall trench isolation in semiconductor device | |
| KR19980048836A (en) | Device Separating Method of Semiconductor Device | |
| KR100895824B1 (en) | Method for forming isolation layer of semiconductor device | |
| KR19990021366A (en) | Device Separation Method of Semiconductor Device | |
| KR20000019032A (en) | Isolation method of semiconductor device | |
| KR100733693B1 (en) | Method of forming a isolation layer in semiconductor device | |
| KR19990055791A (en) | Device Separation Method of Semiconductor Device | |
| KR100517351B1 (en) | Method for manufacturing device isolation barrier of semiconductor device | |
| KR100571484B1 (en) | Semiconductor device manufacturing method | |
| KR20030052663A (en) | method for isolating semiconductor device | |
| KR19990048786A (en) | Method of forming device isolation film of semiconductor device | |
| KR100242387B1 (en) | Method of forming an element isolation film in a semiconductor device | |
| KR100228345B1 (en) | Method for isolating semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20091126 Year of fee payment: 9 |
|
| LAPS | Lapse due to unpaid annual fee |