JPH11232166A - Data transfer device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data transfer device which transfers data from an expanded storage device to a main storage device even when array data that are transfer objects are scattered in the expanded storage device. SOLUTION: An address buffer 7 stores the address of an expanded storage device 3 that is a data transfer source according to an address transfer instruction issued from a processor 1 before the issue of a data transfer instruction from the processor 1. An address controlling part 6 reads an address stored in the buffer 7 according to the data transfer instruction from the processor 1, issues a read request to read data from the corresponding address of the device 3 of the transfer source, also makes a write request to store the data read from the device 3 to a main storage device 2 that is a transfer destination and performs data transfer, updating a read address of the buffer 7.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to data transfer means between a main storage device and an extended storage device of a computer device, and more particularly to data for transferring data between storage devices in response to a data transfer command from an arithmetic processing unit. It relates to a transfer device.

[0002]

2. Description of the Related Art It is difficult for a supercomputer performing large-scale scientific and technical calculations to store all target data in a main memory. Thus, in this type of supercomputer, a high-capacity extended storage device capable of high-speed data transfer with the main storage is provided, and data that cannot be stored in the main storage is stored in the extended storage device. ing. The prior art relating to the data transfer means between the extended storage device and the main storage device is disclosed in, for example, JP-A-2-228743.

FIG. 6 is a block diagram showing a configuration example of an information processing apparatus according to the prior art. This information processing device
At least one arithmetic processing unit 2, a high-speed large-capacity main storage device 2, a large-capacity extended storage device 3 capable of high-speed data transfer between the main storage device 2, a main storage device 2, and an extended storage device Data transfer device 4 connected to device 3 and input / output control device 5
And

The information processing apparatus is provided with a data buffer 8 for temporarily storing transfer data between the main storage device 2 and the extended storage device 3. Starting address of the main storage device 2,
An extended storage data transfer processing unit 9 that controls data transfer between the main storage device 2 and the data buffer 8 based on the block length and the distance between elements is provided.

FIG. 7 is a time chart showing an operation example of the information processing apparatus, and FIG. 8 is a view showing a data storage state in the information processing apparatus at the time of this operation. In the operation examples shown in these figures, L data having an n-byte length each existing at an interval of m bytes from the address a in the main storage device 2 are transferred to the address b of the extended storage device 3. Hereinafter, the operation of the information processing apparatus will be described with reference to FIGS.

The arithmetic processing unit 1 includes an operation code for instructing a data transfer request from the main storage device 2 to the extended storage device 3, a head address a on the main storage device 2 as a transfer source,
Data transfer including a data length n per block, an inter-element distance m indicating an interval at which block data to be transferred exists, the number of transfer blocks L, and a start address b on the extended storage device 3 as a transfer destination. The request 100 is issued to the extended storage data transfer unit 9.

[0007] When the extended storage data transfer processing unit 9 that has received the data transfer instruction 100 recognizes that the data transfer from the main storage device 2 to the extended storage device 3 has been instructed from the operation code, the extended storage data transfer processing unit 9 executes the operation of the main storage device 2. The usage status is checked, and when the status becomes accessible, a + m, a + 2m,.
A read request (read request) is issued continuously to the address (L-1) × m, and the transfer data read from the main storage device 2 is stored in the data buffer 8.

When reading of all L data having an n-byte block length transferred from the main storage device 2 is completed and storage in the data buffer 8 is completed, the expanded storage data processing section 9 expands the read data. In order to transfer the data to the storage device 3, a write request (write request) to the extended storage device 3 is sent.

When writing to the extended storage device 3 becomes possible, the transfer data stored in the data buffer 8 is transferred continuously. When the data transfer of all the transfer data to the extended storage device 3 is completed, the extended storage data transfer processing unit 9 sends an end report 101 to the arithmetic processing device 1. Also, if an error is detected in the data transfer device 4 or the extended storage device 3 during the data transfer, the end status is reported with error information when the end is reported, and the data transfer to the arithmetic processing unit 1 ends abnormally. Report. In the above, the data transfer from the main storage device 2 to the extended storage device 3 has been described. In the data transfer from the extended storage device 3 to the main storage device 2, the data transfer device 4 also transmits the data transfer request from the arithmetic processing device 1. Thus, it is possible to read desired data from the extended storage device 3 and write the data at the instructed inter-element distance on the main storage device 2.

[0010]

However, the above-mentioned prior art has the following problems. (1) A data transfer device according to the prior art receives, from a central processing unit, a head address of each of a transfer destination and a transfer source, a block length and an inter-block distance of data as a transfer unit, and the number of blocks of data to be transferred. Although data transfer is performed based on such information, it does not have a function of transferring data of array data scattered on the extended storage device. Therefore, when data is transferred at a fixed address interval for array data expanded on the extended storage device, high-speed data transfer can be performed between the main storage device and the extended storage device. If the array data required by the device is scattered, high-speed data transfer cannot be performed. (2) A data transfer device according to the prior art transfers data from a storage address of a transfer source storage device designated by an arithmetic processing device to a storage address of a transfer destination storage device. Must be specified by physical (direct) address. However, in general, an arithmetic processing device performs an arithmetic process using data in a main storage device using a virtual (logical) address. Therefore, in the arithmetic processing device, when instructing the data transfer device to perform data transfer, it is necessary to convert each virtual address of the transfer source and the transfer destination into a physical address, which may cause a reduction in the arithmetic processing performance. is there.

The present invention has been made in view of the circumstances described above, and a first object of the present invention is to provide a memory device which can be used even when array data expanded on an extended storage device is scattered (even at random addresses). Another object of the present invention is to provide a data transfer device capable of controlling data transfer between an extended storage device and a main storage device. A second object of the present invention is to provide a data transfer device capable of performing high-speed data transfer without lowering the processing performance of an arithmetic processing device.

[0012]

The invention according to claim 1 is
In a data transfer device that performs data transfer between a plurality of storage devices according to a data transfer instruction from an arithmetic processing device, an address transfer command issued from the arithmetic processing device before the data transfer instruction is issued from the arithmetic processing device. An address buffer that stores the address of the storage device that is the data transfer source; an address that is stored in the address buffer according to a data transfer instruction from the arithmetic processing device; and data is read from the address of the storage device that is the transfer source Issue a read request for
Making a write request to store data read from the transfer source storage device to the transfer destination storage device,
A data transfer device, comprising: a control unit that performs data transfer while updating a read address of the address buffer.

According to a second aspect of the present invention, in a data transfer device for transferring data between a plurality of storage devices in response to a data transfer instruction from an arithmetic processing device, an address buffer for storing an address of a transfer source storage device in the data transfer. Reading the address of the transfer source storage device in the data transfer from the predetermined storage device according to the data transfer instruction, storing the read address of the transfer source storage device in the address buffer, and storing the read address in the address buffer. Issues a read request to read data from the address of the storage device of the transfer source, issues a write request to store the data read from the transfer source to the storage device of the transfer destination, A control unit for performing data transfer while updating the read address of the buffer. And gist data transfer apparatus according to symptoms.

According to a third aspect of the present invention, there is provided a data transfer apparatus receiving a supply of a virtual address as an address of a data transfer source and a transfer destination storage device from the arithmetic processing unit, wherein the virtual address is a physical address of the storage device. The data transfer device according to claim 1 or 2, further comprising an address conversion table for converting the data into a data.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. A. First Embodiment FIG. 1 is a block diagram showing a configuration of an information processing apparatus using a data transfer device 4A according to a first embodiment of the present invention. The information processing apparatus includes one or more arithmetic processing units 1
A high-speed large-capacity main storage device 2, a large-capacity extended storage device 3 capable of high-speed data transfer between the main storage device 2,
It comprises an arithmetic processing unit 1, a main storage unit 2, an extended storage unit 3, and a data transfer unit 4A connected to the input / output control unit 5.

The data transfer device 4A includes an address buffer 7 for storing addresses of array data to be transferred scattered on the transfer source extended storage device 3, and a main storage device 2
A data buffer 8 for temporarily storing transfer data between the storage device 3 and the extended storage device 3 is provided. Further, an address control unit 6 is provided in the data transfer device 4A. When transferring data from the extended storage device 3 to the main storage device 2, the address control unit 6 reads the address of the array data to be transferred on the extended storage device 3 from the address buffer 7, and sends the data together with this address. Transfer device 4A
A read request (read request) for transferring the array data to the data buffer is transmitted to the extended storage device 3, while a write request for transferring the array data of the data buffer 78 is sent to the main storage device 2. Issued.

FIG. 2 is a diagram showing the contents stored in each unit when data is transferred from the extended storage device 3 to the main storage device 2 in this information processing apparatus. In the operation example shown in FIG. 2, n pieces of data from the address a0 to the address an-1 of the extended storage device 3 are transferred to the main storage device 2 and subsequent addresses. Hereinafter, the operation of the present embodiment will be described with reference to FIG.

The arithmetic processing unit 1 is configured to pre-store addresses ao, a1,...
An-1 is transferred to the address buffer 7 of the data transfer device 4 via the address transfer signal 102. Then, the arithmetic processing unit 1 executes a data transfer instruction including an operation code for instructing a data transfer request from the extended storage device 3 to the main storage device 2 and a physical address b of the main storage device 2 to which the array data is to be written. The signal 100 is transferred to the data transfer device 4
A is issued to the address control unit 6 of A.

When receiving the data transfer command signal 100, the address control unit 6 recognizes that the data transfer from the extended storage device 3 to the main storage device 2 has been instructed by the operation code contained therein, and The address a0 in the device 3 where the first array data to be read is stored is read from the address buffer 7.

Next, the address control unit 6 issues a read request to the extended storage device 3 for reading the array data stored at the address a0. When receiving the read data from the extended storage device 3, the read data is stored in the data buffer 8.

Generally, writing / writing to the extended storage device 3
Since the read operation is performed by block transfer (a predetermined data unit), it is necessary to once store data in block units including array data required by the arithmetic processing device 1 in the data buffer 8.

Finally, the address control unit 6 sets the arithmetic processing unit 1 of the read data stored in the data buffer 8
The array data required by the main storage device 2 is read in units of transfer, and an address b to be written on the main storage device 2 is added together with the read data, and a write request is issued to the main storage device 2.

When the data transfer to the main memory 2 is completed, the address control unit 6 sets the read address of the address buffer 7 indicating the read address of the extended memory 3 to 1
The word is updated, and the array data stored at the address a1 of the extended storage device 3 is transferred to the main storage device 2 in the same procedure as described above.

Hereinafter, similarly, the transfer processing of all array data from addresses a2 to an-1 is performed.

When transfer of all array data is completed,
The data transfer device 4 sends an end report 101 to the arithmetic processing device 1. If an error is detected in the data transfer device 4 and the extended storage device 3 during the data transfer, an end report, in particular, error information is added to the end status, and a report is made. Report that.

B. Second Embodiment FIG. 3 is a block diagram showing a configuration of an information processing device using a data transfer device 4B according to a second embodiment of the present invention. In the first embodiment, the address where the array data in the extended storage device 3 is stored is directly transferred to the address buffer 7 in the data transfer device 4A via the address transfer signal 102. On the other hand, in the present embodiment, the arithmetic processing device 1 stores the address of the array data to be transferred in the extended storage device 3 in the address transfer signal 103.
Is transferred in advance to a predetermined address on the main storage device 2 via the data transfer device 4, and the data transfer device 4 stores the address in response to a data transfer command signal 102 from the arithmetic processing device 1 in an address buffer in the data transfer device 4. 7.

Next, the operation of this embodiment will be described with reference to FIG. In this operation example, as in the first embodiment, n pieces of data from the address a0 to the address an-1 on the extended storage device 3 are transferred to the address b on the main storage device 2 and thereafter.

The arithmetic processing unit 1 is arranged in advance with addresses a0, a1,...
an-1 is a predetermined address c in the main memory 2.
Is transferred via the address transfer signal 103 to the address.

Next, the arithmetic processing unit 1 includes a data transfer unit 4
On the other hand, the array buffer required by the arithmetic processing unit 1 is stored from the address c on the main storage device 2 to the address buffer 7 in the data transfer device 4 via the data transfer command signal 100. An instruction to transfer the address of the storage device 3 is sent.

When receiving the data transfer command signal 100, the address control unit 6 reads the data from the extended storage device 3 accompanying the data transfer from the main storage device 2 to the address buffer 7 from the main storage device based on the operation code included in the signal. Recognizing that the data transfer to the address 2 has been instructed, first, a read request from the address c is transmitted to the main storage device 2. When receiving the read data a0, a1,..., An-1 from the main storage device 2, the address control unit 6 stores the read data a0, a1,.

Next, as in the first embodiment, the address a0 at which the first array data to be read in the extended storage device 3 is stored is read from the address buffer 7. The processes after the issuance of the write request to the extended storage device 3 are the same as those in the first embodiment, and thus the description is omitted.

C. Third Embodiment FIG. 4 is a block diagram showing a configuration of an information processing device using a data transfer device 4C according to a third embodiment of the present invention. The basic configuration is the same as that of the first embodiment, but this embodiment is different from the first embodiment in the following points. That is, in the first embodiment, the (physical) address is directly transferred from the arithmetic processing unit 1 to the address buffer 7 in the data transfer device 4 via the address transfer signal 102, but in the present embodiment, According to the address transfer signal 102, a virtual (logical) address is transferred as an address on the main storage device 2 and the extended storage device 3. For this reason, in the present embodiment, the data transfer device 4
An address translation unit 10 for directly translating the virtual address into an address is added to the address control unit 6 in C. As shown in FIG. 5, the address translation mechanism 10 stores a virtual address and a direct address in association with each other.
It is configured to output a corresponding direct address.

Next, the operation of the present embodiment will be described with reference to the data transfer diagram of FIG. 2, focusing on the parts performing operations different from those of the first embodiment.

In this operation example, as in the first embodiment, n data from the address a0 to the address an-1 on the extended storage device 3 are transferred to the address b and subsequent addresses on the main storage device 2. .

First, the arithmetic processing unit 1 sets a direct address a0 of array data on the extended storage device 3 necessary for calculation in advance.
virtual addresses d0, d corresponding to a1, ..., an-1
1, to dn-1 are transmitted via the address transfer signal 102,
The data is transferred to the address buffer 7 of the data transfer device 4 in advance.

Next, the arithmetic processing unit 1 includes an operation code for instructing a data transfer request from the extended storage unit 3 to the main storage unit 2 and a virtual address e of the main storage unit 2 to which array data is to be written. The data transfer command signal 100 is issued to the address control unit 6 of the data transfer device 4.

When receiving the data transfer command signal 100, the address control unit 6 recognizes from the operation code included in the signal that the data transfer from the extended storage device 3 to the main storage device 2 has been instructed, The virtual address d0 of the first array data to be read on the extended storage device 3 is read from the address buffer 7.

Next, the address control unit 6 controls the virtual address d0 of the array data on the extended storage device 3 read from the address buffer 7 by the address conversion mechanism 10.
Is directly converted to the address a0, and a read request for reading the array data stored at the address a0 is issued to the extended storage device 3.

The address control unit 6 converts the virtual address e for storing the array data read from the extended storage device 3 into the direct address c of the main storage device 2 by the address conversion mechanism 10. I do.

The processing after receiving the read data from the extended storage device 3 is the same as that of the first embodiment, so that the description is omitted. If the direct address a0 corresponding to the virtual address d0 in the extended storage device 3 does not exist in the address translation mechanism 10, the address control unit 6 does not have the direct address a0 corresponding to the virtual address d0. Then, an end report 101 is issued to the arithmetic processing unit 1.

D. Fourth Embodiment Next, a fourth embodiment of the present invention will be described with reference to the drawings. This embodiment has a configuration basically similar to that of the second embodiment.
However, the configuration is such that an address translation mechanism 10 is added to the second embodiment. Therefore, according to the present embodiment, the arithmetic processing device 1
Specifies the virtual address at the transfer source of the array data and the virtual address at the transfer destination, so that the same data transfer as in the second embodiment can be performed. Since the detailed operation in that case is a composite type of the second embodiment and the third embodiment, the description is omitted.

[0042]

According to the present invention, the following effects can be obtained. (1) Even when array data required by the central processing unit is scattered, high-speed data transfer can be performed. As a result, it is possible to improve the operation performance of the entire system in transferring array data between the main storage device and the extended storage device. This is because the data transfer device has a multi-word address buffer for storing the addresses of the main storage device and the extended storage device and an address control unit for controlling the address buffer. This is because the data transfer between the main storage device and the extended storage device can be performed using only the data transfer device. (2) There is no need to convert a virtual address to a physical address on the side of an arithmetic processing unit that performs arithmetic processing with a virtual address. Thus, even if the storage addresses of the main storage device and the extended storage device received from the arithmetic processing device are virtual (logical) addresses, the data can be directly converted to (physical) addresses and data can be transferred. Because the data transfer device has an address translation mechanism for directly translating the virtual address of the main storage device and the extended storage device into the address, the virtual address is directly translated into the address in the data transfer device. Is possible,
This is because it is possible to suppress a decrease in arithmetic performance due to an address conversion operation in the arithmetic processing device.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an information processing device using a data transfer device 4A according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a data array in each device at the time of data transfer in the embodiment.

FIG. 3 is a block diagram showing a configuration of an information processing device using a data transfer device 4B according to a second embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of an information processing device using a data transfer device 4C according to a third embodiment of the present invention.

FIG. 5 is a diagram illustrating a configuration of an address conversion mechanism of an address control unit according to the first embodiment.

FIG. 6 is a block diagram illustrating a configuration of an information processing device using a conventional data transfer device.

FIG. 7 is a time chart illustrating an operation example of data transfer performed in the information processing apparatus.

FIG. 8 is a diagram showing a data array of each unit in the information processing apparatus in the operation example.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 arithmetic processing unit 2 main storage device 3 extended storage device 4 data transfer device 6 address control unit 7 address buffer 8 data buffer 9 extended storage data transfer processing unit 10 address conversion mechanism 100 data transfer request signal 101 end report 102 first address Transfer signal 103 Second address transfer signal

Claims (3)

[Claims] 1. A data transfer device for performing data transfer between a plurality of storage devices in accordance with a data transfer instruction from an arithmetic processing device, wherein the data transfer instruction is issued from the arithmetic processing device before the data transfer instruction is issued from the arithmetic processing device. An address buffer that stores the address of the storage device that is the data transfer source according to the address transfer instruction, and reads the address stored in the address buffer according to the data transfer instruction from the arithmetic processing unit. A read request for reading data from an address is issued, and a write request for storing data read from the transfer source storage device is made to the transfer destination storage device, and the read address of the address buffer is changed. And a control unit for performing data transfer while updating. Over data transfer device. 2. A data transfer device for performing data transfer between a plurality of storage devices in accordance with a data transfer command from an arithmetic processing device, comprising: an address buffer for storing an address of a transfer source storage device in data transfer; Reads the address of the storage device of the transfer source in the data transfer from the predetermined storage device, stores the read address of the storage device of the transfer source in the address buffer, and stores the address of the transfer source stored in the address buffer. Issues a read request for reading data from the address of the storage device, issues a write request for storing the data read from the transfer source to the transfer destination storage device, and updates the read address of the buffer. And a control unit for performing data transfer while performing the data transfer. Location. 3. An address conversion table for converting a virtual address into a physical address of a storage device, the data transfer device receiving a supply of a virtual address as an address of a data transfer source and a transfer destination storage device from the arithmetic processing device. 3. The method according to claim 1, further comprising:
A data transfer device according to claim 1.