JPH11225178A - Radio receiver and its method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To maintain time division multiple access(TDMA) timing even when a recessed clock is stopped and to reduce power consumption. SOLUTION: A receiver is provided with a timing control section 9 that selects a clock given to a system timing generating section 10. A recovered clock (PLLCLK) outputted from a recovery clock generating section 5 is given to the system timing generating section 10, which generates a system timing during the reception. The timing control section 9 detects a phase difference between a low frequency clock outputted from a low frequency oscillator 6 and the reversed clock before the end of reception to obtain a timing to preset the recovered clock and selects the low frequency clock for the system timing generating section 10. Then the recovered clock generating section 5 is stopped before the preset timing. At the preset timing, the recovered clock generating section 5 is started to select the recovered clock for the system timing generating section 10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a radio receiving apparatus and method, and more particularly, to a radio receiving apparatus and a radio receiving apparatus capable of generating a system timing from a low-frequency clock during non-reception to thereby stop a reproduction clock generation unit. About the method.

[0002]

2. Description of the Related Art TDMA (Time Division)
In a digital wireless telephone adopting the on-multiple-access method, when a TDMA reception frame is formed from a received signal, the frame is formed at a timing following the baud timing based on the transmission-side baud timing. .

FIG. 6 is a block diagram showing a configuration of a conventional radio receiving apparatus provided in a TDMA radio telephone.

[0004] In this conventional radio receiving apparatus, a signal transmitted from a base station is received via an antenna 13 and the received signal is input to a receiving section 1. The receiving unit 1 outputs a local transmission signal (in FIG.
(Referred to as “LOCAL”) and converted into an intermediate frequency signal (referred to as “IF” in the figure). Here, the local transmission signal is generated by the synthesizer 2 based on the signal output from the high-precision oscillator 3, and is output to the mixer provided in the reception unit 1. As the high-precision oscillator 3, an oscillator with high frequency accuracy such as VCTCXO is used.

The intermediate frequency signal output from the receiver 1 is detected by the demodulator 4 and output to the reproduced clock generator 5 and the data determiner 7 as a demodulated signal. This detection is performed according to a modulation scheme negotiated with the base station.

[0006] The reproduction clock generator 5 is provided with a demodulated signal and a low-frequency clock output from the low-frequency oscillator 6 (in the figure,
Based on the “BCLK”, a reproduced clock (“PLLCLK” in the figure) that follows the baud timing on the transmission side
Is generated). The baud timing is included in the demodulated signal, and the reproduced clock generator 5 is provided with a baud timing extractor for extracting the baud timing from the demodulated signal. The reproduction clock is generated by a PLL (Phase Locke) provided in the reproduction clock generation unit 5.
d Loop) circuit.

On the other hand, the data judging section 7 samples the demodulated signal output from the demodulating section 4 using the reproduced clock as a sampling clock, and converts the digital baseband signal into the synchronous position detecting section 8 and the frame data generating section 11. Output to

[0008] The synchronous position detecting section 8 detects a synchronous word contained in the digital baseband signal and outputs a synchronous trigger (denoted as “TRG” in the figure) to the system timing generating section 10.

The system timing generator 10 generates a frame timing (in the figure,
“FTIM”)) and outputs the frame data to the frame data generation unit 11.

[0010] The frame data generator 11 constructs frame data from the digital baseband signal according to the frame timing and outputs the frame data to the audio codec 12.

The audio codec 12 decodes frame data by a predetermined method, converts the data into audio data, and outputs the audio data to a speaker.

In the conventional radio receiving apparatus configured as described above, in order to reduce current consumption, the receiving operation is stopped while frames other than the frame being received by the apparatus are being transmitted from the base station. Intermittent reception is performed.

In the non-receiving section where the receiving operation is stopped, the baud timing cannot be extracted from the received signal, so that a reproduced clock that follows the baud timing cannot be generated, and the clock runs by itself.

Here, since it is necessary to maintain the TDMA frame timing even during the non-receiving period as described above, it is necessary to increase the accuracy of the reproduced clock in accordance with the non-receiving period. For example, if the non-receiving section is 1 second, ±
Accuracy of about 5 ppm is required.

In order to obtain such a high-precision reproduction clock, conventionally, a high-precision reference clock is provided separately from the low-frequency oscillator 6, and the frequency error of the reproduction clock is corrected based on this reference clock. .

[0016]

However, as described above, in the conventional radio receiving apparatus, it is necessary to run the reproduced clock by itself with high accuracy. The means for correcting the frequency error cannot be stopped.

Here, the reproduced clock generation unit and the reference clock used for correcting the frequency error both operate at high speed and consume a large amount of current, which has been a problem in reducing the current consumption.

As a configuration in which the TDMA frame timing is not maintained during the non-reception period, a method of eliminating the above-described correction means and stopping the reproduction clock to reduce current consumption can be considered. According to the method, it is necessary to start up the entire apparatus before starting reception and generate timing following the baud timing again, and the reception operation section becomes long.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a radio receiving apparatus and a radio receiving method that can maintain TDMA timing even when the reproduction clock is stopped, and can reduce power consumption.

[0020]

In order to achieve the above object, according to the first aspect of the present invention, a low frequency clock is generated in a radio receiving apparatus which receives a signal following a baud timing on a transmitting side. A low-frequency clock generation unit, a reproduction clock generation unit that generates a reproduction clock from the low-frequency clock, a phase lock unit that locks the reproduction clock to the phase of the baud timing, and a phase locked by the phase lock unit. Phase difference detecting means for detecting a phase difference between a reproduced clock and the low frequency clock during a first reception period; and a predetermined phase difference detection unit for determining whether a second reception period is during a non-reception period following the first reception period. Phase presetting means for retaining the phase difference detected before the time and presetting the phase of the reproduction clock based on the retained phase difference. And wherein the Rukoto.

According to a second aspect of the present invention, in the first aspect of the present invention, reference clock generating means for generating a reference clock having a frequency higher than the low frequency clock;
Frequency error detecting means for detecting a frequency error of the low-frequency clock based on the generated reference clock, wherein the phase presetting means presets a phase of the reproduced clock based on the phase difference and the frequency error. It is characterized by doing.

According to a third aspect of the present invention, in the first or the second aspect of the present invention, a function of stopping functions other than the low frequency clock generating means, the system timing generating means and the phase presetting means is provided. Means is provided.

According to a fourth aspect of the present invention, a reproduced clock is generated from a low-frequency clock, and the reproduced clock is locked to a phase of a baud timing on a transmitting side included in a received signal. In the wireless receiving method of receiving a signal following the baud timing by generating a system timing based on the received clock, the phase of the reproduced clock whose phase is locked and the position of the low-frequency clock before the end of the reception are determined. After detecting the phase difference and determining the timing and phase for presetting the reproduction clock from the phase difference, the system timing is generated based on the low frequency clock, and then the generation of the low frequency clock and the generation of the system timing are performed. Stop processing other than generation and execution of the preset until the timing of the preset, and Based on the timing of the preset, after executing the preset the system timing and generating from the preset reproduction clock.

According to a fifth aspect of the present invention, in the fourth aspect of the present invention, the phase relationship is detected,
A frequency error of the low frequency clock is detected, and the preset timing is obtained based on the phase relationship and the frequency error.

[0025]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, an embodiment of a radio receiving apparatus according to the present invention will be described in detail with reference to the accompanying drawings.

First, the outline of the present invention will be described with reference to FIG. FIG. 1 is a block diagram illustrating a configuration of a wireless reception device according to the present invention.

The radio receiving apparatus according to the present invention is provided with a timing control section 9 for switching a clock input to a system timing generating section 10, as shown in FIG. The recovered clock (PLLCLK) is input to a system timing generator 10 to generate a system timing such as a frame timing (FTIM). Before the reception is completed, the timing controller 9 controls the low frequency clock output from the low frequency oscillator 6. (B
CLK) and the reproduced clock, the timing for presetting the reproduced clock is obtained from the phase difference, and then the clock input to the system timing generator 10 is switched to the low frequency clock.

Thereafter, the reproduction clock generation unit 5 is stopped until the timing of the preset, and when the preset timing comes, the reproduction clock generation unit 5 is activated and the reproduction clock is preset to execute the system timing generation. It operates to switch the clock input to the unit 10 to the recovered clock.

Hereinafter, the configuration of the radio receiving apparatus shown in FIG. 1 will be described in more detail. Here, the configuration and operation of the wireless receiving apparatus shown in FIG. 1 are roughly described with reference to FIG.
Since the configuration is the same as that of the wireless receiving device shown in FIG. 6, the description of the same configuration is omitted in this embodiment, and the description will focus on differences from the wireless receiving device shown in FIG.

The radio reception apparatus shown in FIG. 1 is provided with a timing control section 9 for switching a clock input to a system timing generation section 10 unlike the conventional radio reception apparatus. The reproduction clock generator 5 can be started and stopped in response to a power save signal (indicated as “PSAVE” in the figure), which contributes to a reduction in current consumption.

FIG. 2 is a block diagram showing the configuration of the reproduced clock generator shown in FIG. As shown in the figure, the reproduction clock generation unit 5 includes a multiplier 30 for multiplying the frequency of the low-frequency clock, a preset frequency divider for dividing an input signal by an externally designated frequency division ratio, and presetting. It comprises a type variable frequency divider 31, a baud timing extractor 32 for extracting a baud timing from a demodulated signal, a phase comparator 33 for comparing the phases of two input signals, and a low-pass filter (LPF). .

The operation of the reproduced clock generator 5 configured as described above will be described.
First, a low-frequency clock is input to a multiplier 30, the low-frequency clock is multiplied to a predetermined frequency, and output to a preset-type variable frequency divider 31.

The preset type variable frequency divider 31 divides the frequency of the multiplied signal based on the signal output from the low-pass filter 34 and outputs the frequency-divided signal as a reproduction clock.

On the other hand, the demodulated signal input to the reproduced clock generator 5 is input to the baud timing extractor 32, and is output to the phase comparator 33 after the baud timing is extracted.

A reproduced clock is also input to the phase comparator 33, and the phase comparator 33 compares the phase of the input reproduced clock with the phase of the baud timing. As a result, when there is a phase difference between the two signals, a predetermined voltage is output to the low-pass filter 34 and the preset type variable frequency divider 31 is controlled in a direction to reduce the phase difference. That is, the preset variable frequency divider 31, the phase comparator 33 and the low-pass filter 34 constitute a PLL circuit.

The phase of the reproduced clock generated as described above is locked to the phase of the baud timing.

As shown in FIG. 2, a power save signal (PSAVE) is input to each of the above components, and power is turned on / off according to the value of the signal.

A preset signal (PRESET) is input to the preset type variable frequency divider 31, and the phase of the reproduction clock is preset according to the value of the signal.

Next, referring to FIG.
Will be described. FIG. 3 is a block diagram showing a configuration of the timing control unit shown in FIG.

As shown in the figure, the timing control unit 9 detects a phase difference between the two input signals and a frequency error (one frequency signal) of one of the two signals. Frequency error detector 41 for detecting F1)
And a preset control unit 42 that calculates a preset timing of the preset type variable frequency divider 31 shown in FIG. 2 and outputs a preset signal (PRESET) at the timing obtained as a result, and one of the two input clocks. It comprises a clock changeover switch 43 for selecting one.

The operation of the timing control unit 9 configured as described above will be described.
The detection command signal (DE
T) is output, the phase difference detecting section 40 and the frequency error detecting section 41 respectively output the low frequency clock (B
CLK) and the reproduction clock (PLLCLK) and the reference clock (REFCL) output from the high-precision oscillator 3 shown in FIG. 1 for the low-frequency clock (BCLK).
Perform the detection of the frequency error for K).

Then, the phase difference detecting section 40 outputs the phase difference (P1) obtained as a detection result to the preset control section 42, and the frequency error detecting section 41 outputs the frequency error obtained as the detection result to the preset control section 42. Output to

The preset control unit 42 calculates a preset timing from the detection result obtained as described above and the frequency of the low frequency clock and the frequency of the reproduction clock stored in advance, and holds the result. Here, the preset timing can be obtained as a time M / A or as an integer value M. The calculation of the preset timing and the phase (P2) after the preset is performed based on the following equation.

P2 = N / B / (1 + F1 / 1000000) -M / A-P1 (P2> 0) N / B: Time to maintain timing N: Desired integer B: Frequency of reproduction clock F1: Low frequency clock M: Desired integer A: Frequency of low frequency clock P1: Phase difference between low frequency clock and reproduced clock For example, A = 42 kHz, B = 42 kHz, F1 = + 1
0 ppm, N = 30240, P1 = 10 μs,
P2 = 30.42 [μs] is the preset phase, and M = 30239 is the preset point.

On the other hand, a low-frequency clock and a reproduction clock are input to a clock changeover switch 43 provided in the timing control section 9, and output in response to a clock changeover signal (CLKSW) from the system timing generation section 10. Switch clocks. It is preferable to use an RF switch having good phase characteristics for the clock changeover switch 43.

The radio receiving apparatus according to the present invention is configured as described above. Hereinafter, an operation example of the wireless receiving apparatus according to the present invention will be described with reference to FIG. 4 and FIG.

FIG. 4 is a flowchart showing an execution procedure of a processing cycle executed by the radio receiving apparatus shown in FIG. FIG. 5 is a timing chart showing the state of each signal when the wireless reception device shown in FIG. 1 executes the processing shown in FIG.

First, the system timing generator 10
During signal reception, frame timing is generated based on the recovered clock. At this time, the system timing generation unit 10 determines from the frame timing whether or not it is immediately before the end of the reception (step 100), and if it is immediately before the end of the reception, sends the detection command signal (DET) to the timing control unit 9. Output. If not immediately before the end of the reception, the above determination is repeated.

Upon receiving the detection command signal, the timing control section 9 performs the above-described operation to detect the phase difference between the low-frequency clock and the reproduced clock and to detect the frequency error of the low-frequency clock (step 101). Then, based on the result, the phase and timing for presetting the reproduction clock are calculated (step 102).

The calculated preset timing is a point indicated by an integer M after receiving the detection command signal (DET) as shown in FIG. The preset control unit 42 shown in FIG. 2 holds the preset phase (P2) until this point comes.

Thereafter, the system timing generator 10
Outputs a clock switching signal (CLKSW) to the timing control unit 9 at the same time as or immediately after the end of reception, as shown in FIG. 5, and switches the base clock to a low-frequency clock (step 103).

Then, a power save signal is output to the reproduction clock generator 5, and the power of the reproduction clock is stopped (step 104). At this time, the other reception functions are stopped at the same time.

The processing in steps 103 and 104 may be performed simultaneously with the end of reception, or their procedures may be interchanged.

After the non-reception state as described above,
The system timing generation unit 10 determines whether or not it is just before the start of reception (about several ms) based on the frame timing (FTIM) (step 105). The power of the function stopped at 104 is turned on (step 106).

When the preset timing obtained in step 102 comes (Yes in step 107), the held phase value is output to the reproduction clock generation unit 5 as a preset signal (PRESET) (step 10).
8).

The reproduction clock generator 5 sets the phase of the reproduction clock that has been powered on with this phase value. Here, since the reproduced clock immediately after power-on does not completely rise as shown in FIG. 5, the calculation of the preset timing takes this into consideration. Is calculated to start.

After completion of the preset, the system timing generator 10 outputs a clock switching signal (CLKSW) to the timing controller 9 and switches the base clock to the preset reproduced clock (PLLCLK) (step 109). Receive the signal.

Thereafter, the flow returns to step 100 again, and the above operation is repeated.

As described above, according to the present invention, the phase difference between the reproduced clock and the low frequency clock is detected before the reception is completed, and the preset timing and phase of the reproduced clock are obtained based on the phase difference. Is used as a free-running clock, and the phase of the reproduced clock is preset at the preset timing before reception starts, whereby the reproduced clock can follow the baud timing again.

As a result, the reproduction clock generation unit can be stopped in the section where the low-frequency clock is running on its own, so that the current consumption can be further reduced.

Although the above embodiment has been described with reference to the configuration in which the timing controller 9 is provided with the frequency error detector 41 as shown in FIG. 3, when the frequency accuracy of the low frequency oscillator 6 is high, The portion 41 may not be provided.

The above-described calculation of the preset timing and the phase may be executed in the system timing generator 10 and the phase may be output to the timing controller 9 at the timing. With this configuration, the timing control unit 9 can be stopped at the time of power saving.

Further, instead of the preset type variable frequency divider 31 shown in FIG. 2, a Johnson counter or a ring counter may be used and its output may be inputted to the phase comparator 33.

As described above, even when the power is turned off during the non-reception period, if there is an external interrupt process or the like, the detection of the interrupt process is based on the low frequency clock. And cancels the power save of the reproduced clock generation unit 5 according to the content of the processing.
The reproduction clock may be supplied to a processor such as a CPU or a DSP. In this case, the clock input to the system timing generation unit 10 is not switched until the reproduction clock preset ends, and the self-running state with the low frequency clock is continued. When the interrupt processing is completed, the power can be turned off again.

[0065]

As described above, according to the present invention,
Before the end of the reception, the phase difference between the reproduced clock and the low-frequency clock is detected, the preset timing and the phase of the reproduced clock are obtained based on the phase difference, and the low-frequency clock is used as a free-running clock. By presetting the phase of the reproduced clock at the preset timing, the reproduced clock can follow the baud timing again.

As a result, the reproduction clock generation unit can be stopped during the period in which the low-frequency clock runs on its own, so that the current consumption can be further reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a wireless reception device according to the present invention.

FIG. 2 is a block diagram showing a configuration of a reproduced clock generator shown in FIG.

FIG. 3 is a block diagram showing a configuration of a timing control unit shown in FIG. 1;

FIG. 4 is a flowchart showing an execution procedure of a processing cycle executed by the wireless reception device shown in FIG. 1;

FIG. 5 is a timing chart showing the state of each signal when the wireless reception device shown in FIG. 1 executes the processing shown in FIG. 4;

FIG. 6 is a block diagram showing a configuration of a conventional wireless receiving device provided in a TDMA wireless telephone.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Receiving part, 2 ... Synthesizer, 3 ... High precision oscillator, 4
... Demodulation section, 5 reproduction clock generation section, 6 low-frequency oscillator, 7 data determination section, 8 synchronous position detection section, 9 timing control section, 10 system timing generation section, 11
... Frame data generator, 12 ... Audio codec, 13
... Antenna, 30 ... Multiplier, 31 ... Preset type variable frequency divider, 32 ... Baud timing extractor, 33 ... Phase comparator, 34 ... Low-pass filter (LPF), 40 ... Phase difference detector, 41 ... Frequency error detection Unit, 42: preset control unit, 43: clock changeover switch.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H04L 27/227 H04L 27/22 B

Claims (5)

[Claims] 1. A radio receiving apparatus for receiving a signal following a baud timing on a transmitting side, comprising: a low-frequency clock generating means for generating a low-frequency clock; and a reproduced clock for generating a reproduced clock from the low-frequency clock. Generating means; phase lock means for locking the reproduced clock to the phase of the baud timing; and a phase difference between the reproduced clock whose phase is locked by the phase lock means and the low frequency clock during a first reception period. A phase difference detecting means for detecting, during a non-reception period following the first reception period,
And a phase presetting means for retaining a phase difference detected a predetermined time before the reception period of the above and presetting a phase of a reproduced clock based on the retained phase difference. 2. A reference clock generating means for generating a reference clock having a higher frequency than the low frequency clock; and a frequency error detecting means for detecting a frequency error of the low frequency clock based on the generated reference clock. The phase presetting means presets a phase of the reproduction clock based on the phase difference and the frequency error.
The wireless receiving device according to claim 1. 3. The wireless reception according to claim 1, further comprising a function stopping means for stopping functions other than the low frequency clock generating means, the system timing generating means, and the phase presetting means. apparatus. 4. A reproduced clock is generated from a low frequency clock, the reproduced clock is locked to a phase of a baud timing on a transmitting side included in a received signal, and a system timing is generated based on the locked reproduced clock. Thus, in the wireless reception method for receiving a signal following the baud timing, detecting a phase difference between the phase-locked reproduction clock and the low-frequency clock before the end of the reception, After obtaining the timing and phase for presetting the reproduction clock from the above, the system timing is generated based on the low-frequency clock, and then the generation of the low-frequency clock, the generation of the system timing, and the execution of the preset are performed. Stop the process until the timing of the preset, the timing of the preset Based on, after executing the preset radio receiving method, characterized in that the system timing generated from the preset reproduction clock. 5. The apparatus according to claim 4, wherein the phase relation is detected, a frequency error of the low frequency clock is detected, and the preset timing is obtained based on the phase relation and the frequency error. Wireless reception method.