JP2003304164A - Portable telephone device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a portable telephone device capable of easily and accurately eliminating sensitivity deterioration of a received frequency and an occurrence of a receiving level measurement error with a simple configuration. <P>SOLUTION: In this portable telephone device having a radio part having an antenna, an analog baseband part to which an output of the radio part is connected, a digital baseband part connected to the analog baseband part, and a control part 105 for controlling each of the parts, the control part 105 changes frequencies of a system clock, a bus clock, a CPU clock, etc., used in the portable telephone device according to the received frequency. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mobile phone device, and more particularly to a mobile phone device for changing frequencies of a system clock, a bus clock, a CPU clock and the like (hereinafter abbreviated as clock) according to a reception frequency.

When a radio channel in which an integral multiple of a frequency of a clock or the like corresponds to a reception frequency is used, the frequency of the clock or the like is controlled to a frequency deviated from a frequency of an integral fraction of the reception frequency.

The clock or the like is characterized by using a frequency oscillated by a PLL circuit type oscillator using a high-order frequency of about several tens of kHz which does not affect the radio frequency as a reference frequency or a frequency obtained by dividing the frequency. There is.

The reference frequency is 32.768k of the clock CLK.
Hz is used.

The frequency of the clock or the like is changed by changing the frequency division number of the PLL circuit type oscillator.

The frequency of the clock or the like is changed within the time until the frequency when the frequency of the PLL circuit of the local oscillator of the receiving section for switching the radio channel is switched to converge to a predetermined range.

When the frequency of the clock or the like is switched, the circuit for designating the frequency division number of the divider of the PLL circuit for the clock or the like is changed so that the strobe signal of the serial data for designating the frequency of the PLL of the local oscillator of the receiving unit is started up. At the same time.

Since the clock and the like are generated by dividing the oscillation frequency of one PLL circuit, it is possible to change the frequencies of all the clocks and the like by changing the number of divisions of one PLL circuit.

[0009]

2. Description of the Related Art In a portable telephone device as shown in FIG. 9, clocks of various frequencies are used. When an integer multiple of the clock frequency matches the received frequency of the portable telephone device, the received frequency is used. In the existing wireless channel, reception sensitivity deterioration and reception level measurement error occur.

FIG. 11 shows a case in which the synchronization clock of the data bus is 1
The result of measuring the receiving sensitivities of all the receiving channels when 0 MHz is used is shown.

As shown in FIG. 11, 81 times 10 MHz
A marked deterioration in sensitivity is seen at frequencies of 82 times and 83 times.

As shown in FIG. 10, in particular, the case where radiation is emitted from the flexible printed boards at the connecting portions of the upper and lower casings and received by the antenna is remarkable.

FIG. 1 is a block diagram of a general portable telephone device. The details of the control unit 105 in this are shown in FIG.
Is shown in.

In FIG. 7, reference CLK oscillator 1051
, A frequency signal of 14.4 MHz is oscillated, and the frequency signal is divided by 4 by the PLL circuit 1053 to obtain 3.6.
The comparison reference frequency is set to MHz.

The oscillation frequency of the voltage controlled oscillator 1055 is set to 1
Divide by 4 and perform PLL control by phase comparison.
0.4 MHz is used for the CPU clock.

Reference CLK1 oscillator 1051 with 14.4M
The frequency signal of Hz is oscillated, and the PLL circuit 1054
The frequency is divided by 4, and the comparison reference frequency is set to 3.6 MHz.

The oscillation frequency of the voltage controlled oscillator 1056 is set to 1
Divide by 0 and perform PLL control by phase comparison.
MHz is used for the DSP clock.

FIG. 3 is a detailed view of the display section 110.

LC receiving CPU clock 1201
The D controller 1101 divides the CPU clock by 5 and uses it as a data clock. Frequency is 10.08MHz
Becomes

FIG. 8 is a detailed view of the photographing unit when the photographing unit is added.

The oscillator 1147 oscillates 9 MHz and is used as a data clock.

As another conventional example having substantially the same purpose as the present invention, there is a technique disclosed in Japanese Patent Laid-Open No. 2000-244421.

The wireless communication device disclosed in this publication is a wireless communication device that selectively receives a desired desired wave and an undesired interfering wave within a predetermined reception frequency band. In the case where the interfering wave is a non-modulated wave, it is provided with a judging means for judging whether the received signal is a desired wave or an interfering wave by examining the signal bandwidth of the received signal, A receiving unit that performs frequency conversion into a signal of a predetermined intermediate frequency by using at least one frequency converting unit, demodulates the signal of the intermediate frequency to generate received data, and an electric field that detects the electric field strength of the signal in the receiving unit. The determination means includes a strength detecting means and a local oscillating portion for generating a local oscillation signal and supplying the local oscillation signal to the frequency converting means, and the determining means uses the electric field strength detecting means to generate a first signal when the local oscillation signal has a first frequency. Detecting a second field strength when the second frequency is intensity and predetermined frequency shift, the first
It is determined whether the received signal is a desired wave or an interfering wave, based on the difference between the electric field strength of 1 and the second electric field strength.

[0024]

However, with the above frequency configuration, the standard comparison frequency of 3.6M is used.
An integral multiple of 10 Hz of the data clock frequency of the display unit.
At a reception frequency corresponding to an integral multiple of 08 MHz and an integral multiple of 9 MHz of the data clock frequency of the image capturing unit, a problem occurs that causes sensitivity deterioration and reception level measurement error.

Further, the conventional example disclosed in the above publication has a problem that the structure becomes complicated.

In view of the above-mentioned conventional circumstances, the present invention has been made to solve the above-mentioned problems inherent in the prior art. Therefore, the object of the present invention is to reduce sensitivity and reception at the reception frequency with a simple structure. It is an object of the present invention to provide a new mobile phone device capable of easily and accurately removing the occurrence of a level measurement error.

[0027]

In order to achieve the above object, a portable telephone device according to the present invention includes a radio section having an antenna, an analog baseband section to which an output of the radio section is connected, and the analog section. In a mobile phone device having a digital baseband unit connected to the baseband unit and a control unit for controlling each unit, the control unit is a system clock, a bus clock, a CPU clock, etc. used in the mobile phone unit ( The frequency of (hereinafter abbreviated as a clock or the like) is changed according to the reception frequency.

When using a radio channel in which an integral multiple of the frequency of the clock or the like corresponds to the reception frequency, the control means shifts the frequency of the clock or the like from a frequency that is a fraction of the integer of the reception frequency. Take control.

A frequency oscillated by a PLL circuit type oscillator or a frequency obtained by dividing the frequency is used as the clock or the like, which has a high frequency of about several tens of kHz which does not affect the radio frequency as a reference frequency.

The control means includes a first PLL circuit and a first PLL circuit.
A first PLL oscillator including a voltage-controlled oscillator, a second PLL oscillator including a second PLL circuit and a second voltage-controlled oscillator, and the first and second
Control circuit connected to the PLL circuit for controlling the frequency division ratio of each PLL circuit, a reference CLK generator for supplying a reference CLK to the control circuit, and a source clock of a watch for supplying to the control circuit. PL in the first and second PLL circuits
A clock CLK generator that generates a clock CLK used as a comparison reference frequency of L, a CPU provided between the first voltage controlled oscillator and the control circuit, the second voltage controlled oscillator, and the control circuit. And a DSP provided between and.

The reference frequency is set to 32.
It can be 768 kHz.

The frequency of the clock or the like is changed by the PLL.
This is done by changing the frequency division number of the circuit type oscillator.

The change of the frequency of the clock or the like is performed within the time until the frequency when the frequency of the PLL circuit of the local oscillator of the receiving section for switching the wireless channel is switched to converge to a predetermined range.

When the frequency of the clock or the like is switched, the designation of the frequency division number of the frequency divider of the PLL circuit of the clock or the like is changed by setting the strobe signal of the serial data for the frequency designation of the PLL of the local oscillator of the receiving unit. It is done at the same time as raising.

By generating the clocks and the like by dividing the oscillation frequency of one PLL circuit, it is possible to change the frequencies of all clocks and the like by changing the division number of one PLL circuit.

In the mobile phone system, when the radio frequency channel is assigned by the base station, the frequencies of the clocks are selectively switched according to the assigned radio frequency channel.

The first PLL circuit is the clock 3 of the clock CLK.
By frequency-dividing the frequency of the first voltage-controlled oscillator by 1538 with 2.768 kHz as a reference frequency, the first PLL oscillator outputs a frequency signal of 50.397184 MHz and the frequency is controlled by the control circuit. When the number is set to 1539, it is 50.429952.
The second PLL circuit generates a frequency signal of MHz, and the second PLL circuit divides the frequency of the second voltage-controlled oscillator by 1100 using 32.768 kHz of the clock CLK as a comparison reference frequency, so that the second PLL oscillator outputs 36 MHz. .0448
When the frequency signal of MHz is output and the frequency division number is set to 1099 under the control of the control circuit, it is 36.0.
A frequency signal of 12032 MHz is generated.

The frequency division number of the first PLL circuit is set to 153.
8, the frequency division number of the second PLL circuit is 1100, CPU
Clock is 50.397184MHz, DSP clock is 36.0448MHz, and data clock is 10.07.
A case where the control circuit controls the first and second PLL oscillators so that the frequency becomes 94368 MHz is set to the first frequency related state, and the frequency division number of the first PLL circuit is set to 153.
9, the frequency division number of the second PLL circuit is 1099, CPU
Clock is 50.4299524MHz, DSP clock is 36.012320MHz, data clock is 1
The case where the control circuit controls the first and second PLL oscillators so that the frequency becomes 0.0859904 MHz is regarded as the second frequency-related state.

In the first frequency-related state, deterioration of reception sensitivity is caused in the first, second, and third channels, and in the second frequency-related state, deterioration of reception sensitivity is caused in the fourth, fifth, and sixth channels, respectively. Utilizing the fact that both channels are different, the control circuit is configured such that the first and second P circuits are in a normal state.
The LL circuit is set to the first frequency-related state, and
In the frequency-related state, the second frequency-related state is set only when the first, second, and third channels that are reception sensitivity deterioration channels are used.

[0040]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will now be described in detail with reference to the drawings for each preferred embodiment thereof.

FIG. 1 is a block diagram showing an example of the first embodiment according to the present invention.

[0042]

[Structure of First Embodiment] Referring to FIG. 1, the present invention is applied to a portable telephone device as shown in FIG.
The antenna 101 is connected to the wireless unit 102, the output of the wireless unit 102 is connected to the analog baseband unit 103, and the analog baseband unit 103 is described below.
Is a microphone 111, a speaker 112, and a receiver 1.
13 and the digital baseband unit 104.

The battery 107 is connected to the power supply unit 106,
This power supply is supplied from the power supply unit 106 by the wireless unit 102, the analog baseband unit 103 and the digital baseband unit 10.
4, the control unit 105, the key operation unit 109, and the display unit 110.

The control section 105 includes a radio section 102, an analog baseband section 103 and a digital baseband section 104.
Is connected to the key operation unit 109 and the power supply unit 106, and controls each.

The control section 105 is connected to the connection flexible printed board, and further, the display section 1 is connected by the bus 120.
Connected to 10.

The above is the same in the conventional portable telephone device.

The configuration of the control unit 105, which is the first essential point of the present invention, will be described in detail with reference to FIG.

FIG. 2 is a block diagram showing an embodiment of the control unit 105 shown in FIG.

Referring to FIG. 2, the reference clock generator 1
051 is connected to the control circuit 1059,
The reference CLK is supplied to 59.

The clock CLK generator 1052 is the control circuit 10
The clock CLK that is connected to 59 and is output is used as the clock of the clock of the clock and also as the clock of various timers.

Further, the clock CLK output from the clock CLK generator 1052 is the same as that of the first PLL circuit 1053 and the second PLL circuit 1053.
Is supplied to the PLL circuit 1054 of the
Used for comparison reference frequencies of 3,1054.

The first PLL circuit 1053 is connected to the voltage controlled oscillator 1055 and constitutes a first PLL oscillator.

The output of the voltage controlled oscillator 1055 is the CPU
It is connected to 1057 and supplies the CPU clock to the CPU 1057.

The CPU 1057 is connected to the control circuit 1059 by a bus and performs various controls according to programs.

The control circuit 1059 is the first PLL circuit 1
It is connected to 053 and controls the division ratio.

The second PLL circuit 1054 is connected to the voltage controlled oscillator 1056 and constitutes a second PLL oscillator.

The output of the voltage controlled oscillator 1056 is a DSP.
(Digital Signal Processor)
Connected to 1058, supplies DSP clock to DSP 1058.

The oscillators 1055 and 1056 may be voltage-controlled oscillators or current-controlled oscillators, and the same operation is possible.

The DSP 1058 is bus-connected to the control circuit 1059 and performs digital signal calculation processing such as encoding / decoding processing.

The control circuit 1059 controls the second PLL circuit 1
054 is connected to control the frequency division ratio.

The control circuit 1059 is connected to an external circuit by an external IO and performs various controls.

Next, the configuration of the control unit 105, which is the second essential point of the present invention, will be described in detail with reference to FIG.

The control unit 105 is connected to the display unit 110 by the bus 120 as described in FIG.

For details of the bus 120, the control unit 105 supplies an internally generated CPU clock to the LCD driver 1102 through a connection line 1201 and is connected to the LCD controller 1101 through a data bus 1202. Take control.

The LCD controller 1101 divides the CPU clock to generate a data clock. LCD
The controller 1101 supplies a data clock to the LCD driver 1102 via the data clock line 1105.

Further, the LCD controller 1101 is connected to the LCD driver 1102 by a data bus 1106 and transmits image information.

The LCD driver 1102 has a bus 1104.
Thus, the LCD cell 1103 is connected and the LCD cell is driven.

[0068]

[Operation of First Embodiment] Next, the operation of the first embodiment of the present invention will be described.

First, the operation of the control section 105 will be described in detail with reference to FIG.

The first PLL circuit 1053 has a clock CLK.
32.76 of the clock CLK output from the generator 1052
Voltage-controlled oscillator 10 with 8 kHz as comparison reference frequency
The frequency of 55 is divided by 1538 to generate the first PLL circuit 1
It is supplied to the phase comparator in 053. This phase comparator
A control voltage is supplied to the voltage controlled oscillator 1055 so that the divided frequency matches the comparison reference frequency.

In this way, the first PLL circuit 105
The first PLL oscillator composed of 3 and the voltage controlled oscillator 1055 stably supplies the frequency of 50.397184 MHz to the CPU 1057 as the CPU clock.

When the frequency division number is set to 1539 under the control of the control circuit 1059, the voltage controlled oscillator 1055 oscillates at 50.249952 MHz stably in this case.

The second PLL circuit 1054 has a clock CLK.
32.76 of the clock CLK output from the generator 1052
Voltage-controlled oscillator 10 with 8 kHz as comparison reference frequency
The frequency of 56 is divided by 1100 to generate the second PLL circuit 1
Supply to the phase comparator in 054. This phase comparator
A control voltage is supplied to the voltage controlled oscillator 1056 so that the divided frequency matches the comparison reference frequency.

In this way, the second PLL circuit 105
The second PLL oscillator, which is composed of 4 and the voltage-controlled oscillator 1056, stably supplies the frequency of 36.0448 MHz to the DSP 1058 as the DSP clock.

If the frequency division number is set to 1099 under the control of the control circuit 1059, the voltage controlled oscillator 1056 oscillates 36.012032 MHz stably in this case.

Next, the operation of the display section 110 will be described in detail with reference to FIG.

The LCD controller 1101 has a connection line 1
The CPU clock is received from the control unit 105 via 201. The LCD controller 1101 divides the CPU clock by 5 to generate a data clock, supplies the data clock to the LCD driver 1102 from the data clock line 1105, and further outputs data from the bus 1106 to form a synchronous data bus.

The operation of the above-described first embodiment of the present invention will be described more specifically.

Here, the frequency relationship in the first state is that the frequency division number of the first PLL circuit 1053 = 1538, the second P
When the control circuit 1059 controls the PLL circuits 1053 and 1054 so that the frequency division number of the LL circuit 1054 is 1100, CPU clock = 32.768 kHz × 1538 = 5
0.397184 MHz DSP clock = 32.768 kHz × 1100 = 3
6.0448 MHz data clock = 50.397184 MHz / 5 = 1
It becomes 0.0794368 MHz.

In this case, the reception frequency range is 810
At ~ 828MHz, it is an integer multiple of the CPU clock,
There is no order for the reception frequency.

In the DSP clock, the 23rd order is 829.
It becomes 0304 MHz (761 ch).

In the data clock, the 81st is 816.
The 82nd order of 4346MHz (257ch) becomes 826.5141MHz (660ch).

Therefore, these three frequencies cause deterioration of reception sensitivity.

Here, the frequency relationship in the second state is that the control circuit 1059 sets the frequency division number of the first PLL circuit 1053 to 1539 and the frequency division number of the second PLL circuit 1054 to 1099. When controlling each PLL circuit, CPU clock = 32.768 kHz × 1539 = 5
0.4299524 MHz, DSP clock = 32.768 kHz × 1099 = 3
6.012032 MHz, data clock = 50.429952 MHz / 5 = 1
It becomes 0.0859904 MHz.

In this case, the reception frequency range is 810
At ~ 828MHz, it is an integer multiple of the CPU clock,
There is no order for the reception frequency.

In the DSP clock, the 23rd order is 828.
It becomes 2767 MHz (731 ch).

In the data clock, the 81st order is 816.
The 82nd order of 9652 MHz (279 ch) becomes 827.0512 MHz (682 ch).

Therefore, these three frequencies cause deterioration of reception sensitivity.

Thus, in the first state, 761
3 channels of ch, 257 ch, and 660 ch cause deterioration of reception sensitivity, and in the second state, 731 ch and 279
Although 3 channels of ch.682 channel cause deterioration of reception sensitivity, both channels are different channels.

In order to avoid this, when the above 3CH is used, the control circuit 1059, in a normal condition, is
PLL circuit 1053 and PLL circuit 10
54 is set, and the frequency division number in the second state is set only when the reception sensitivity deterioration channel in the first state is used.

By carrying out such control, it is possible to control the mobile phone system and make a call without degrading the reception sensitivity in all channels.

Further, even in the peripheral level detection, it is possible to prevent erroneous detection.

The specific control is as follows in the channel designation sequence of the mobile phone: When the power is turned on, the control circuit 1059 specifies frequency division in the first state.

2. In the control unit 105, the channels that specify the frequency channel to the wireless unit 102 are 761 and 257.
-Determine which is 660.

3. If the determination result is No, the frequency division number in the first state is designated at the same time when the frequency is designated to the wireless unit 102.

If the determination result is Yes, the wireless unit 102
At the same time when the frequency division number is specified to, the frequency division number in the second state is specified.

According to the present invention, the frequency division number is designated at the same time as the frequency designation to the radio section 102. Rewrite the frequency register.

[0098]

Second Embodiment Next, a second embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 4 shows the first embodiment of the present invention shown in FIG.
FIG. 9 is a block configuration diagram showing an example of a mobile phone device according to a second embodiment of the present invention in which a photographing unit 114 is added to the mobile phone device according to the embodiment.

In the case of the second embodiment, the control unit 105 and the photographing unit 114 are connected by the bus 121, and control the photographing unit 114 and receive photographing data.

FIG. 5 is a block diagram showing the details of the photographing section 114.

Referring to FIG. 5, the photographing section 114 comprises a camera 1143, a camera control section 1142, and a camera interface section 1141. The camera interface section 1141 has an oscillator 1147 for generating a camera clock. And capacitor 1148 and switch 1149
Are connected.

The control unit 105 controls the bus 121 to use the photographing unit 11.
4 is connected.

The asynchronous data bus 1212 is connected to the camera interface section 1141 and receives data.

The camera interface section 1141 is connected to the camera control section 1142, the data bus 1146 and the data clock 1145.

The camera control section 1142 has the camera 1143.
It is connected with the bus 1144 to control the camera. The camera control unit 1142 also performs data processing on the captured data.

In the oscillator 1147, the switch 1149 is turned off.
At N time, it oscillates a frequency of 9 MHz, and switches 114
When 9 is OFF, it is adjusted so as to oscillate at a frequency of 9.01 MHz. This frequency is also used as a data clock and supplied to the camera control unit 1142.

Here, when the data clock is 9 MHz, 90 times is 810 MHz (0 ch) and 91 times is 81.
9MHz (360ch), 92 times is 828MHz (72
0ch), which also causes deterioration of reception sensitivity in the channel of this reception frequency.

Therefore, when using this channel, the control unit 105 sends the clock change data to the photographing unit 114 to perform control.

The photographing unit 1 which has received the clock change data
14, the camera interface unit 1141 turns off the switch 1149 to set the oscillation frequency to 9.01 MHz.
And

If the data clock is 9.01 MHz, 90 times becomes 810.09 MHz (4 ch) and 91 times becomes 819.91 MHz (396 ch).

Therefore, the above 0ch / 360ch / 72
On channel 0, reception sensitivity does not deteriorate.

FIG. 6 shows a configuration in which the second embodiment according to the present invention shown in FIG. 5 is further improved.

Referring to FIG. 6, the control unit 105 determines that the CP
The U clock 1211, the camera interface 114
Supply to 1.

The camera interface section 1141 divides this frequency by 6 and uses it as the data clock 1145.

In this case as well, a channel that causes deterioration of reception sensitivity occurs, but the CPU is not
Avoided by changing the clock frequency.

The structure shown in FIG. 6 has an effect that the circuit is simpler than the structure shown in FIG.

The same effect can be obtained by changing the comparison reference frequency instead of changing the frequency division number of the PLL.

For example, 4 of the reference frequency of 14.4 MHz is used.
If 3.6 MHz of the frequency division is used as the reference comparison frequency of the PLL, the 225th order becomes 810 MHz, but 14.4 MH
By setting 4.8 MHz, which is a division of z by 3, as the reference comparison frequency of the PLL, an integral multiple of 4.8 MHz will not become 810 MHz.

[0120]

The present invention is constructed and operates as described above, and according to the present invention, the following effects can be obtained.

Even in a channel in which the reception frequency is a frequency that is an integral multiple of the frequency of the clocks, there is no deterioration in reception sensitivity,
Good reception can be performed and reception level measurement can be accurately performed.

The reason is that when a channel corresponding to an integral multiple of the frequency of clocks is specified, the frequency of clocks is changed.

[Brief description of drawings]

FIG. 1 is a block diagram of a general mobile phone device to which the present invention is applied, showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing the first embodiment of the present invention and showing an example of a control unit which is a main part of the present invention.

FIG. 3 is a block configuration diagram showing a first embodiment according to the present invention and showing a functional example of a control unit which is a main part of the present invention.

FIG. 4 is a block diagram showing a second embodiment according to the present invention and is a block configuration in the case where a photographing unit is added to the first embodiment.

5 is a block configuration diagram showing details of an imaging unit in FIG.

FIG. 6 is a block diagram showing an improved modified example of FIG.

FIG. 7 is a block diagram of a control unit according to the related art.

FIG. 8 is a block diagram of a photographing unit according to a conventional technique.

FIG. 9 is a front view showing the external appearance of the open / close type mobile phone device to which the present invention is applied in the open state.

10 (a) is a schematic side view of the open / close type mobile phone device shown in FIG. 9 in a closed state, and FIG. 10 (b) is a schematic side view in an open state.

FIG. 11 is a characteristic curve diagram showing reception sensitivities of all reception channels.

[Explanation of symbols]

101 ... antenna 102 ... Wireless unit 103 ... Analog baseband section 104 ... Digital baseband section 105 ... Control unit 106 ... Power supply unit 107 ... Battery 109 ... Key operation unit 110 ... Display 111 ... Microphone 112 ... speaker 113 ... Receiver 114 ... Imaging unit 120 ... bus 121 ... bus 1051 ... Reference CLK generator 1052 ... Clock CLK generator 1053 ... PLL circuit 1054 ... PLL circuit 1055 ... Voltage controlled oscillator 1056 ... Voltage controlled oscillator 1057 ... CPU 1058 ... DSP 1059 ... Control circuit 1101 ... LCD controller 1102 ... LCD driver 1103 ... LCD glass 1104 ... bus 1105 ... Data clock line 1106 ... Data bus 1141 ... Camera interface section 1142 ... Camera control unit 1143 ... Camera 1145 ... Data clock 1147 ... Oscillator 1148 ... Capacitor 1149 ... Switch 1201 ... CPU clock connection line 1202 ... Data bus 1212 ... data bus

Claims (14)

[Claims] 1. A radio unit having an antenna, an analog baseband unit to which an output of the radio unit is connected, a digital baseband unit connected to the analog baseband unit, and control means for controlling each unit. In the mobile phone device having the above, the control means changes the frequency of a system clock, a bus clock, a CPU clock, etc. (hereinafter abbreviated as a clock, etc.) used in the mobile phone device according to a reception frequency. Mobile phone device. 2. The control means shifts the frequency of the clock or the like from a frequency that is an integral fraction of the reception frequency when using a radio channel in which an integral multiple of the frequency of the clock or the like corresponds to the reception frequency. The mobile phone device according to claim 1, further comprising controlling the frequency. 3. A frequency oscillated by a PLL circuit type oscillator, or a frequency obtained by dividing the frequency, is used as the reference frequency for the clock or the like having a higher order of several tens of kHz that does not affect the radio frequency. The mobile phone device according to claim 2, which is further characterized. 4. The first control unit includes a first PLL oscillator including a first PLL circuit and a first voltage controlled oscillator, a second PLL circuit and a second voltage controlled oscillator. A second PLL oscillator, a control circuit connected to the first and second PLL circuits for controlling the frequency division ratio of each PLL circuit, and a reference CLK generator for supplying a reference CLK to the control circuit. , A clock source clock is supplied to the control circuit, and P is supplied to the first and second PLL circuits.
A clock CLK generator that generates a clock CLK used as a LL comparison reference frequency, a CPU provided between the first voltage controlled oscillator and the control circuit, the second voltage controlled oscillator, and the control circuit. DSP provided between and
The mobile phone device according to any one of claims 1 to 3, further comprising: 5. The reference frequency is set to 3 of the clock CLK.
The mobile phone device according to claim 3, further characterized by using 2.768 kHz. 6. The frequency of the clock or the like is changed by PL
4. The mobile phone device according to claim 3, further comprising changing the frequency division number of the L-circuit type oscillator. 7. The frequency of the clock or the like is changed within a time until the frequency when the frequency of the PLL circuit of the local oscillator of the receiving unit that switches the wireless channel is switched to converge to a predetermined range. The mobile phone device according to any one of claims 1 to 6. 8. When switching the frequency of the clock or the like,
The modification of the designation of the frequency division number of the frequency divider of the PLL circuit such as the clock is performed at the same time when the strobe signal of the serial data designating the frequency of the PLL of the local oscillator of the receiving unit is started. 7. The mobile phone device according to 7. 9. The PLL or the like is generated by dividing the oscillation frequency of one PLL circuit.
4. The mobile phone device according to claim 3, further characterized in that the frequencies of all clocks and the like can be changed by changing the frequency division number of the circuit. 10. The mobile phone system according to claim 2, further comprising: when a radio frequency channel is assigned by a base station, the frequencies of the clocks are selectively switched according to the assigned radio frequency channel. The described mobile phone device. 11. The mobile phone device according to claim 3, further comprising changing the reference comparison frequency of the PLL of the clocks. 12. The first PLL circuit divides the frequency of the first voltage controlled oscillator by 1538 with 32.768 kHz of the clock CLK as a reference frequency for comparison, whereby the first PLL oscillator has a frequency of 50.397184 MHz. In the case where the frequency signal is output and the frequency division number is set to 1539 under the control of the control circuit, 50.42995
A frequency signal of 2 MHz is generated, and the second PLL circuit divides the frequency of the second voltage controlled oscillator by 1100 using 32.768 kHz of the clock CLK as a comparison reference frequency, whereby the second PLL oscillator outputs 36 MHz. .044
When a frequency signal of 8 MHz is output and the frequency division number is 1099 under the control of the control circuit, 36.
The mobile phone device according to claim 4, further comprising generating a frequency signal of 012032 MHz. 13. The frequency division number of the first PLL circuit is 15
38, the frequency division number of the second PLL circuit is 1100, CP
U clock is 50.397184MHz, DSP clock is 36.0448MHz, and data clock is 10.0.
A case where the control circuit controls the first and second PLL oscillators to have a frequency of 794368 MHz is set as a first frequency-related state, and the frequency division number of the first PLL circuit is 153.
9, the frequency division number of the second PLL circuit is 1099, CPU
Clock is 50.4299524MHz, DSP clock is 36.012320MHz, data clock is 1
13. The second frequency relation state is set when the control circuit controls the first and second PLL oscillators so that the frequency becomes 0.0859904 MHz.
The mobile phone device according to. 14. In the first frequency-related state, the first,
In the second and third channels, in the second frequency-related state, the fourth, fifth, and sixth channels cause reception sensitivity deterioration, respectively, and both of them are different channels. Sets the first and second PLL circuits to the first frequency-related state in a stationary state, and sets the first, second, and third reception sensitivity deterioration channels to the first frequency-related state in the first frequency-related state. 14. The mobile phone device according to claim 13, further comprising setting the second frequency-related state only when a channel is used.