JP2008311838A - Receiver - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a receiver for finely switching clock frequency and also stably switching clock frequency so as not to interfere with clock signal of a digital circuit, resulting in deterioration of signal receiving state. <P>SOLUTION: The receiving apparatus 1 includes a signal receiving unit 10 for selectively receiving signals of a plurality of frequency bands, digital circuits 12 to 14 operating on the basis of the clock signal, and a clock supplying circuit 16 for supplying the clock signal. The clock supplying circuit 16 is constituted with a frequency variable PLL circuit to switch the oscillation frequency of the PLL circuit with a control means 14 when the frequency band of the signal received with the signal receiving unit 10 is interfered with the frequency of the clock signal of the clock supplying circuit 16. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a receiving device that receives, for example, a radio signal or a broadcast signal.

  For example, a receiver for digital broadcasting usually includes a tuner unit (signal receiving unit) that receives a broadcast signal and a digital circuit that performs various signal processing. Some analog broadcast receivers have a built-in tuner and a digital circuit for performing various signal processing.

  Further, for example, a receiving device that receives a wireless signal such as a wireless LAN has a built-in signal receiving unit that receives a wireless signal by switching a plurality of receiving channels and a digital circuit that performs various digital processes.

  When the signal receiving unit and the digital circuit are built in this way, if the reception frequency band of the signal receiving unit and the clock frequency of the digital circuit are in a multiple relationship, the signal of the digital circuit is, for example, a power circuit or a ground line May be mixed into the signal receiving unit as noise and cause a decrease in reception sensitivity.

In order to solve such a problem, several techniques for switching the frequency of the clock signal so that the reception frequency and the harmonics of the clock frequency do not match have been proposed (for example, Patent Documents 1 to 3). .
JP 2005-136618 A JP 2004-032649 A Japanese Patent Laid-Open No. 2000-066872

  In terrestrial digital broadcasting and the like, the number of reception channels is large, and the frequency of the carrier signal over all channels uses a very wide band of 470 MHz to 770 MHz. Therefore, in order to avoid interference between the received signal and the clock signal of the digital circuit in such a receiving apparatus, it is necessary to switch the frequency of the clock signal finely according to the receiving channel.

  However, as shown in the above prior art, in a configuration in which the frequency of the clock signal is changed by switching a plurality of clock generation circuits, the oscillation frequency is slightly different in order to enable fine switching of the clock frequency. This requires a large number of clock generation circuits, which increases the number of circuits and increases the cost.

  In addition, when switching the frequency of the clock signal without any ingenuity, a whisker-like signal is mixed into the clock signal at the time of switching, which can cause a problem that the digital circuit malfunctions. Sex was considered. For example, it is considered that the whisker-like signal described above is mixed into the clock signal when the signal switching operation is performed at the moment when the clock signal rises.

  An object of the present invention is to enable a clock signal to be finely switched so that a signal reception state does not deteriorate due to interference of a clock signal in a receiving apparatus that receives a signal. It is an object of the present invention to provide a receiver capable of stably switching a clock signal without generating whisker-like noise.

  In order to achieve the above object, the present invention includes a signal receiver that selectively receives signals in a plurality of frequency bands, a digital circuit that operates based on a clock signal, and a clock supply circuit that supplies the clock signal. In the receiving device, the clock supply circuit includes a frequency variable PLL circuit, the clock signal is generated by the PLL circuit, and control means for switching and controlling the oscillation frequency of the PLL circuit is provided. The control means is configured to switch the oscillation frequency of the PLL circuit when the frequency band of the signal received by the signal receiving unit and the frequency of the clock signal of the clock supply circuit interfere with each other.

  Preferably, a data table in which a plurality of reception channels that can be received by the signal reception unit and the setting contents of the oscillation frequency of the PLL circuit that does not interfere with the frequency band of the reception channel are stored in association with each other. Preferably, the control means has a stored storage means, and the control means is configured to switch the oscillation frequency of the PLL circuit according to the setting contents of the data table of the storage means when the reception channel is changed.

  Preferably, the apparatus further comprises sensitivity detection means capable of detecting deterioration in reception sensitivity, and the control means switches the oscillation frequency of the PLL circuit when it is determined that reception sensitivity has deteriorated based on detection by the sensitivity detection means. It is better to configure as follows.

  Here, as the sensitivity detection means, for example, means for detecting the error rate of the error correction processing of the modulation signal or means for detecting a control signal of an AGC (Automatic Gain Control) amplifier that amplifies the received signal can be applied.

  Specifically, the variable frequency PLL circuit includes a first frequency divider that divides an oscillation signal having a predetermined frequency, a voltage-controlled oscillator that continuously changes the frequency of the oscillation signal based on a control signal, A second divider for dividing the oscillation signal of the voltage controlled oscillator, a phase comparator for comparing the divided signals of the first divider and the second divider, and an output of the phase comparator A loop filter for extracting a low-frequency component signal, and the frequency division ratio of the first frequency divider and the frequency division ratio of the second frequency divider can be switched.

  According to the present invention, even when the frequency of the received signal covers a very wide band, it is possible to switch the clock frequency in various ways without providing a large number of clock generation circuits. Furthermore, it is possible to switch the clock frequency stably without mixing so-called whisker noise in the clock signal. As a result, problems such as noise being mixed into the received signal from the digital circuit can be avoided, deterioration of the received signal can be prevented, and malfunction of the digital circuit can be avoided when the clock frequency is switched. can get.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[First Embodiment]
FIG. 1 is a block diagram showing the internal configuration of the receiving apparatus according to the first embodiment of the present invention.

  The receiving apparatus 1 of this embodiment is a broadcast receiving apparatus that receives, for example, terrestrial digital one-segment broadcasting (so-called one-segment broadcasting) and displays and outputs it on a display unit. An antenna AN that inputs a broadcasting signal, a broadcasting signal, and the like Tuner 10 for selectively receiving a plurality of channels, IF (intermediate frequency) demodulator 11 for demodulating video data and audio data from the received broadcast signal, and decoder circuit for decoding video data and audio data 12, an LCD controller 13 that drives a display unit (for example, a liquid crystal display) (not shown) based on the decoded video signal to output video, a microcomputer 14 that serves as control means for controlling each unit, and an oscillation signal having a predetermined frequency And a variable frequency type that generates a clock signal CLOCK based on the oscillation signal A PLL (Phase Locked Loop) circuit 16, and a bus 17 for connecting the microcomputer 14 and each unit. In addition, although not shown, an amplifier and a speaker for receiving a sound signal from the decoder circuit 12 and outputting the sound, and an operation unit for inputting a channel selection operation from the user are provided. The tuner unit 10 and the IF demodulator 11 are covered with a shield case 18 so that noise from the digital circuit is hardly mixed.

  Of the above configuration, for example, the decoder circuit 12, the LCD controller 13, and the microcomputer 14 are digital circuits that operate in response to the supply of a clock signal.

  The microcomputer 14 includes a CPU (Central Processing Unit) that executes a control program, a RAM that provides a working memory space for the CPU, a non-volatile memory that stores control data and a control program, and the like. In addition to the user interface processing program that switches the processing content of each unit based on the operation input from the user, the control program changes the clock frequency by changing the setting of the PLL circuit 16 when the reception channel is switched. A processing program is included. Further, the control data includes a data table (see FIG. 3) that represents the correspondence between the reception channel and the setting contents of the PLL circuit 16.

  FIG. 2 is a detailed configuration diagram of the frequency variable PLL circuit 16 shown in FIG.

  The variable frequency PLL circuit 16 is connected to the bus 17 and is capable of writing a value from the microcomputer 14, and a first division that divides the oscillation signal of the reference frequency Fref from the oscillator 15 by 1 / M. A frequency divider 22, a VCO (Voltage Controlled Oscillator) 23 that continuously changes the oscillation frequency by voltage control, a second frequency divider 24 that divides the output of the VCO 23 by 1 / N, and a first frequency divider 22 And a phase comparator 25 that compares the phase of the output of the second frequency divider 24, and a loop filter 26 that extracts a low frequency component from the output of the phase comparator 25. The output of the loop filter 26 is supplied to the VCO 23 as a control voltage. The output of the VCO 23 is supplied to the outside as a clock signal.

  In the frequency variable PLL circuit 16, the frequency division ratio M of the first frequency divider 22 and the frequency division ratio N of the second frequency divider 24 can be changed by rewriting the value of the register 21. ing. Therefore, the frequency Fout of the clock signal CLOCK can be finely changed by changing the M value and the N value.

  FIG. 3 shows an example of a data table stored for changing and controlling the clock frequency.

  As described above, the non-volatile memory of the microcomputer 14 stores a data table representing the correspondence between the reception channel and the M value and N value of the PLL circuit 16 set corresponding thereto. ing. For example, as shown in FIG. 3, the data table is obtained by dividing the continuous reception channel into a plurality of values and calculating the M of the PLL circuit 16 so that the harmonics of the clock signal CLOCK do not overlap the reception frequency band for each division. A value and an N value are stored respectively. Further, the M value and the N value registered in each section are set so that the clock frequency is in a range that does not hinder the operation of the digital circuit.

  According to the receiving apparatus 1 configured as described above, for example, when the reception channel is changed by a user operation, the CPU in the microcomputer 14 causes the PLL corresponding to the reception channel changed from the data table of FIG. The M value and N value of the circuit 16 are read. If these are different from the current M value and N value settings, the M value and N value are written into the register 21 of the frequency variable PLL circuit 16 via the bus 17. Thereby, the frequency dividing ratio of the first frequency divider 22 and the second frequency divider 24 of the PLL circuit 16 is switched, and the frequency of the clock signal CLOCK is changed.

  The change of the frequency of the clock signal CLOCK is realized by changing the frequency dividing ratio of the first frequency divider 22 and the second frequency divider 24 of the PLL circuit 16, so that whisker noise does not occur. The frequency of the clock signal is changed stably. Further, since the clock frequency after this change is set in the data table of FIG. 3 so as not to have a multiple relationship with the frequency band of the reception channel, the reception sensitivity is not adversely affected.

  As described above, according to the receiving apparatus 1 of this embodiment, it is possible to switch the clock frequency in multiple stages and finely without providing a large number of clock generation circuits. Therefore, even in a receiving apparatus having a wide reception frequency, the clock frequency can be switched so that the clock signal does not interfere with the reception signal in all reception channels.

  In addition, since the clock signal is generated by the PLL circuit 16 and the frequency of the clock signal is changed by switching the frequency dividing ratio of the internal frequency dividers 22 and 24, whisker-like noise is generated in the clock signal CLOCK when the frequency is changed. The frequency of the clock signal CLOCK can be changed stably without being generated. Accordingly, it is possible to obtain an effect that no malfunction occurs in the digital circuit that operates in response to the clock signal CLOCK.

  The present invention is not limited to the above embodiment, and various modifications can be made. For example, in the above embodiment, the setting value of the clock signal corresponding to the reception channel is stored in the data table in advance, but for example, the reception frequency band and the clock frequency are not calculated by using such a data table. It is also possible to obtain an M value and an N value that do not have a multiple relationship, and to set them when the reception channel is changed.

  Further, after changing the reception channel of the tuner unit 10, it is once determined whether or not the clock frequency and the reception frequency are in a multiple relationship. If there is a multiple relationship, the M value and N value of the PLL circuit 16 are determined. By changing the clock frequency, the clock frequency may be changed to avoid the multiple relationship.

[Second Embodiment]
The receiving apparatus 1 of the second embodiment is different only in the control operation of the microcomputer 14 that switches the clock frequency, and other configurations are substantially the same as those of the first embodiment. Therefore, only different points will be described.

  FIG. 4 is a diagram illustrating an example of a data table stored in the receiving apparatus according to the second embodiment.

  In the second embodiment, a data table as shown in FIG. 4 is stored in the nonvolatile memory of the microcomputer 14 as control data for appropriately changing the clock frequency. In this data table, M values and N values determined so that clock frequencies are appropriately distributed for a plurality of patterns are registered. In this data table, even if the reception frequency and the clock frequency have a multiple relationship in a certain pattern, the clock frequency in each pattern is appropriately distributed so that a clock frequency that does not have a multiple relationship in other patterns is always found. Thus, the M value and the N value are registered. Further, the M value and the N value of each pattern are set to values such that the clock frequency is in a range that does not interfere with the operation of the digital circuit.

  FIG. 5 is a flowchart showing the processing procedure of the clock frequency changing process executed in the second embodiment.

  In the second embodiment, the CPU 14 of the microcomputer 14 is configured to execute a clock frequency changing process as shown in FIG. This clock frequency changing process is started, for example, when a channel changing operation is performed, started when a change in reception state is detected, or started every predetermined period. You may comprise so that.

  When this processing is started, first, in step S1, reception sensitivity confirmation processing is performed. Specifically, for example, it is performed by confirming the magnitude of the control signal of the AGC amplifier of the tuner unit 10 or confirming the error rate of the error correction circuit of the IF demodulator 11. And it is discriminate | determined whether this receiving sensitivity has fallen below the predetermined threshold value (step S2).

  As a result, if it is determined that the value has fallen below the threshold value, the pattern in the data table in FIG. 4 is switched (step S3). The patterns can be switched in any order as long as each pattern is selected in a single cycle such as “Pattern A → Pattern B” and “Pattern B → Pattern C”.

  Then, again in steps S1 and S2, the reception sensitivity confirmation process and the discrimination process are performed. When the reception sensitivity does not drop below the threshold value, the clock frequency change process is terminated.

  As described above, according to the receiving apparatus of this embodiment, it is possible to switch the clock frequency in multiple stages and finely without providing a large number of clock generation circuits, and the receiving apparatus has a wide receiving frequency. However, in all reception channels, the clock frequency can be switched so that the clock signal does not interfere with the reception signal.

  Further, since the clock signal is generated by the PLL circuit 16, it is possible to stably change the frequency of the clock signal CLOCK, thereby preventing a malfunction in a digital circuit that operates by receiving the clock signal CLOCK. There is an effect.

  The present invention is not limited to the above embodiment, and various modifications can be made. For example, in the above embodiment, the M value and N value of a plurality of patterns of PLL circuits are registered in advance in the data table, and the configuration in which the setting pattern of the PLL circuit is changed according to this data table is shown. Each time, an M value and an N value that appropriately change the clock frequency in a plurality of patterns may be obtained by arithmetic processing and set.

  In the above embodiment, a one-segment broadcasting television receiver is exemplified as the receiving device. However, a digital circuit such as a terrestrial digital broadcasting receiver, a terrestrial broadcasting receiver, or a receiver that receives a wireless signal such as a wireless LAN is used. The present invention can be applied to various built-in receiving devices. In addition, the details specifically described in the embodiments can be changed as appropriate without departing from the spirit of the invention.

It is a block diagram which shows the internal structure of the receiver of 1st Embodiment of this invention. FIG. 2 is a configuration diagram illustrating details of the frequency variable PLL circuit of FIG. 1. It is a figure which shows an example of the data table memorize | stored in order to perform switching control of a clock frequency. It is a figure which shows an example of the data table for switching control of the clock frequency in 2nd Embodiment. It is a flowchart which shows the process sequence of the clock frequency change process performed in 2nd Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Receiver 10 Tuner part 11 IF demodulator 12 Decoder 13 LCD controller 14 Microcomputer 15 Oscillator 16 Frequency variable PLL circuit 21 Register 22 First frequency divider 23 VCO
24 Second frequency divider 25 Phase comparator 26 Loop filter

Claims (5)

In a receiving device including a signal receiving unit that selectively receives signals in a plurality of frequency bands, a digital circuit that operates based on a clock signal, and a clock supply circuit that supplies the clock signal,
The clock supply circuit has a frequency variable type PLL circuit, and the clock signal is generated by the PLL circuit.
Control means for switching and controlling the oscillation frequency of the PLL circuit;
The control means includes
A receiving apparatus that switches an oscillation frequency of the PLL circuit when a frequency band of a signal received by the signal receiving unit and a frequency of a clock signal of the clock supply circuit interfere with each other. A memory that stores a data table in which a plurality of reception channels that can be received by the signal reception unit and the setting contents of the oscillation frequency of the PLL circuit that does not interfere with the frequency band of the reception channel are stored in association with each other. Having means,
The control means includes
2. The receiving apparatus according to claim 1, wherein when the receiving channel is changed, the oscillation frequency of the PLL circuit is switched according to the setting contents of the data table of the storage means. It is equipped with sensitivity detection means that can detect degradation of reception sensitivity
The control means includes
2. The receiving apparatus according to claim 1, wherein the oscillation frequency of the PLL circuit is switched when it is determined that reception sensitivity has deteriorated based on detection by the sensitivity detection means. The frequency variable type PLL circuit includes:
A first frequency divider that divides an oscillation signal of a predetermined frequency;
A voltage-controlled oscillator that continuously changes the frequency of the oscillation signal based on the control signal;
A second divider for dividing the oscillation signal of the voltage controlled oscillator;
A phase comparator for comparing the frequency-divided signals of the first frequency divider and the second frequency divider;
A loop filter for extracting a low frequency component signal from the output of the phase comparator;
The receiving apparatus according to any one of claims 1 to 3, wherein the frequency dividing ratio of the first frequency divider and the frequency dividing ratio of the second frequency divider are switchable. In a receiving device including a signal receiving unit that selectively receives signals in a plurality of frequency bands, a digital circuit that operates based on a clock signal, and a clock supply circuit that supplies the clock signal,
The clock supply circuit includes:
A first frequency divider that divides an oscillation signal of a predetermined frequency;
A voltage-controlled oscillator that continuously changes the frequency of the oscillation signal based on the control signal;
A second divider for dividing the oscillation signal of the voltage controlled oscillator;
A phase comparator for comparing the frequency-divided signals of the first frequency divider and the second frequency divider;
A loop filter for extracting a low frequency component signal from the output of the phase comparator;
A variable frequency PLL circuit capable of switching between a frequency dividing ratio of the first frequency divider and a frequency dividing ratio of the second frequency divider;
Control means for switching and controlling the oscillation frequency of the PLL circuit;
A memory that stores a data table in which a plurality of reception channels that can be received by the signal reception unit and the setting contents of the oscillation frequency of the PLL circuit that does not interfere with the frequency band of the reception channel are stored in association with each other. Means,
With
The control means includes
A receiving apparatus characterized in that, when the receiving channel is changed, the oscillation frequency of the PLL circuit is switched in accordance with the setting contents of the data table of the storage means.

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