JP2008066823A - Digital signal reception apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve such a problem that a tuner section needs to be powered on even during other than a desired program in consideration of a stabilization time of an AGC voltage and electric power is wasted accordingly. <P>SOLUTION: The digital signal reception apparatus is provided with a control unit 46 which receives an RFAGC voltage output from an AGC control unit 39a and a signal of time 25bb of the desired program output from a demodulator 43, and before a symbol needed to view the desired program starts, a source voltage is supplied from the control unit 46 to a power terminal 45 of the tuner unit 32 after an RFAGC voltage output from the control unit 46 is supplied to an AGC control terminal 37a. Consequently, the expected purpose can be attained. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a digital signal receiving apparatus that receives a digital signal having a transmission frame composed of time-division symbols.

  A conventional digital signal receiving apparatus will be described below. The conventional digital signal receiving apparatus 1 is composed of a tuner unit 2 and a demodulation unit 3 as shown in FIG.

  The tuner unit 2 includes an antenna terminal 5 to which a digital signal received by the antenna 4 is input, a bandpass filter 6 to which the digital signal input to the antenna terminal 5 is supplied, and an output of the bandpass filter 6 The connected RF amplifier 7, the output of the RF amplifier 7 is connected to one input, and the other input is a mixer 9 connected to the output of the oscillator 8 controlled by the PLL circuit 17, The AGC controller 9a to which the output signal from the mixer 9 is input, the IF amplifier 10 to which the output of the mixer 9 is connected, and the output terminal 11 to which the output of the IF amplifier 10 is connected. .

  The demodulator 3 connected to the output terminal 11 of the tuner unit 2 includes a demodulator input terminal 12 connected to the output terminal 11 of the tuner unit 2, an AD converter 18 connected to the demodulator input terminal 12, The AGC controller 18a to which the output signal from the AD converter 18 is input, the demodulator 13 connected to the output of the AD converter 18, the demodulation output terminal 14 to which the output 13a of the demodulator 13 is connected, and the demodulation The control unit 15 to which the output 13b of the converter 13 and the output of the AGC controller 9a and the output of the AGC controller 18a are respectively input and the power supply terminal 16 of the tuner unit 2 are included. The output from the control unit 15 was connected to the AGC control terminal 7a of the RF amplifier 7 and the AGC control terminal 10a of the IF amplifier 10, respectively.

  The operation of the digital signal receiving apparatus configured as described above will be described below. The antenna 4 receives the digital signal 21. FIG. 2A shows an example of the configuration of one frame of the digital signal 21. As shown in FIG. 2A, one frame of the digital signal 21 is mainly composed of a frame synchronization symbol 22 and a transmission symbol 23 following the frame synchronization symbol 22.

  The transmission symbol 23 includes a plurality of transmission symbols 23A, 23B, and 23C. Of these transmission symbols 23, one transmission symbol 23A is composed of 23A-aa, 23A-bb, and 23A-cc, and transmission symbol 23B is composed of 23B-aa, 23B-bb, and 23B-cc, and is a transmission symbol. 23C is comprised by 23C-aa, 23C-bb, and 23C-cc.

  Among the digital signals 21 having the transmission frames as described above, when viewing aa programs, they can be viewed by performing signal processing after selecting 23A-aa, 23B-aa, and 23C-aa. When viewing a bb program, it can be viewed by performing signal processing after selecting 23A-bb, 23B-bb, and 23C-bb. Similarly, when viewing a cc program, 23A-cc, 23B-cc, and 23C-cc can be signaled and viewed after selection.

  For example, when the user wants to watch a bb program, as shown in FIG. 2B, the tuner unit only receives the time 24 for receiving the frame synchronization symbol 22 and the time 25bb for receiving the bb program among the transmission symbols 23. If the power of 2 is turned on, the bb program can be received.

  Accordingly, the power supply terminal 16 of the tuner unit 2 can be turned off at times other than the bb program broadcast time, such as the aa program broadcast time and the cc program broadcast time. That is, power saving of the digital signal receiving apparatus 1 can be achieved.

As prior art document information related to the invention of this application, for example, Patent Document 1 is known.
JP 2005-510115 A

  However, in such a conventional digital signal receiving apparatus 1, for example, when viewing a bb program, an AGC stabilization time 27 (described later) from when the power terminal 16 of the tuner unit 2 is turned on until the RFAGC voltage is stabilized. Was necessary). In consideration of the AGC stabilization time 27, it is necessary to turn on the power supply terminal 16 of the tuner unit 2 in advance.

  Accordingly, the present invention has been made to solve this problem, and an object of the present invention is to provide a digital signal receiving apparatus that saves power by considering the AGC stabilization time.

  In order to achieve this object, the digital signal receiving apparatus of the present invention includes a control unit to which the first AGC voltage output from the first AGC controller and the symbol output from the demodulator are input, The first AGC voltage output from the control unit is supplied to the first AGC terminal before the start of the symbol necessary for viewing the desired program among the symbols, and then the tuner unit sends the first AGC voltage to the first AGC terminal. The power supply voltage is supplied.

  Thereby, the intended purpose can be achieved.

  As described above, the present invention provides a control unit to which the first AGC voltage output from the first AGC controller and the symbol output from the demodulator are input. The first AGC voltage output from the control unit is supplied to the first AGC terminal before the start of the symbol necessary for viewing, and then the power supply voltage is supplied from the control unit to the tuner unit. In addition, power can be saved by supplying power to the tuner section after supplying the first AGC voltage.

  Therefore, for example, in a portable digital signal receiving apparatus using a battery as a power source, the life of the battery can be extended.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is a block diagram of a digital signal receiving apparatus according to Embodiment 1 of the present invention. As shown in FIG. 1, the digital signal receiving apparatus 31 in the present embodiment includes a tuner unit 32 and a demodulation unit 33.

  The tuner unit 32 includes an antenna terminal 35 to which the digital signal 21 received by the antenna 34 is input, a bandpass filter 36 to which the digital signal input to the antenna terminal 35 is supplied, and an output of the bandpass filter 36. Are connected to one input, a mixer 39 to which the output of the oscillator 38 is connected to the other input, and an output from the mixer 39. An AGC controller 39a to which signals are input, an IF amplifier 40 to which the output of the mixer 39 is connected, and an output terminal 41 to which the output of the IF amplifier 40 is connected.

  Further, a PLL circuit 49 is connected to the oscillator 38 for PLL control. Further, the output of the oscillator 38 is connected to one input of a bandpass filter 36, an RF amplifier 37, and a mixer 39 to control each of them.

  On the other hand, the demodulation unit 33 connected to the output terminal 41 of the tuner unit 32 includes a demodulation input terminal 42 connected to the output terminal 41 of the tuner unit 32, an AD converter 50 connected to the demodulation input terminal 42, An AGC controller 50a to which an output signal from the AD converter 50 is input, a demodulator 43 connected to the output of the AD converter 50, an output terminal 44 to which the output 43a of the demodulator 43 is connected, and a demodulator 43, the controller 46 to which the output of the AGC controller 39a and the output of the AGC controller 50a are respectively input, and the AGC control terminal 37a and the IF of the RF amplifier 37 to which the output from the controller 46 is respectively connected. The amplifier 40 includes an AGC control terminal 40 a, a power supply terminal 45 of the tuner unit 32, and a memory 47 connected to the controller 46.

  Further, a shield element 48 (not shown) is provided between the oscillator 38 and these elements so that the output of the oscillator 38 does not leak to one input of the band-pass filter 36, the RF amplifier 37, and the mixer 39. Is provided.

  The operation of the digital signal receiving apparatus 31 configured as described above will be described below.

  First, the frame configuration of the digital signal 21 will be described. As shown in FIG. 2A, the frame structure of the digital signal 21 is composed of a frame synchronization symbol 22 and a transmission symbol 23 following the frame synchronization symbol 22. The service identification symbol 22b (not shown) is required in the same manner as the frame synchronization symbol 22, but is omitted in the following description.

  Note that the basic structure of the digital signal 21 has been described using, for example, DVBH. However, the digital signal 21 can be similarly applied to a DAB system that uses a transmission signal as time division.

  Next, the operation of the digital signal receiving device 31 will be described. In the digital signal 21 received from the antenna 34, the interference signal is suppressed by the band pass filter 36. In the RF amplifier 37, the gain is controlled by the RFAGC voltage output from the AGC controller 39a. The IF amplifier 40 is gain-controlled by the IFAGC voltage output from the AGC controller 50a.

  The digital signal receiver 31 is selected by mixing the output signal of the oscillator 38 whose oscillation frequency is controlled by the PLL circuit 49 with the mixer 39. The frequency output from the mixer 39 is about 50 MHz lower than the input frequency of the mixer 39, or suddenly converted to a baseband frequency. The frequency output from the mixer 39 is set as an intermediate frequency.

  FIG. 2B shows signals and time necessary for receiving the bb program. In order to receive this bb program, it is necessary to receive at time 24 corresponding to the frame synchronization symbol 22 and at time 25bb corresponding to each of the transmission symbols 23A-bb, 23B-bb, and 23C-bb. The time is the power-on time of the tuner unit 32. The on-time 25bb is, for example, 0.5 sec, and the time for one frame is, for example, about 5 sec.

  The control signal shown in FIG. 2B is output from the output 43b of the demodulator 43. When this control signal is input to the controller 46, the RFAGC voltage and the IFAGC voltage output from the AGC controller 39a and the AGC controller 50a are turned on and off by the controller 46 to be AGC control terminals 37a, 40a.

  Similarly, the broadcasting time 25aa (not shown) of the aa program is 0.5 sec, and the broadcasting time 25cc (not shown) of the cc program is 0.5 sec.

  The intermediate frequency from which the bb program is selected is gain-controlled by the IF amplifier 40 and output from the output terminal 41 of the tuner unit 32. The intermediate frequency output from the output terminal 41 is converted into a digital signal by the AD converter 50 via the demodulation input terminal 42 of the demodulator 33.

  The digital signal converted into a digital signal by the AD converter 50 is input to the demodulator 43 and demodulated, and the demodulated digital signal 21 shown in FIG. 2A or 3A is output from the output terminal 44. Is output.

  Further, the controller 46 cuts out only the frame synchronization symbol 22 and the time 25bb from the digital signal 21 such as the transmission symbol 23A-bb, 23B-bb, 23C-bb of the bb program. The power to the power supply terminal 45 of the tuner unit 32 is turned on for times 24 and 25bb which are the cut signals. Further, the power to the power supply terminal 45 is basically turned off at times other than the time 24 for receiving the frame synchronization symbol 22 and the time 25bb for receiving the bb program. Thereby, only 23A-bb, 23B-bb, and 23C-bb can be selected and viewed, and power saving of the power supply can be achieved.

  However, when receiving the frame synchronization symbol 22 or the transmission symbols 23A-bb, 23B-bb, and 23C-bb, the RFAGC voltage and the IFAGC voltage are not immediately stabilized, and it takes time to stabilize. In consideration of this stabilization time, it is necessary to turn on the power to the power supply terminal 45 of the tuner unit 32 before the time 25bb starts.

  Hereinafter, a digital signal receiving apparatus capable of saving power by considering the AGC stabilization time will be described.

  FIG. 3A shows signal levels of the frame synchronization symbol 22 and the transmission symbol 23A with respect to time. In FIG. 3A, transmission symbols 23A-aa, 23A-bb, and 23A-cc each have a period 25. Further, a guard interval period 26 is provided between the frame synchronization symbol 22 and the transmission symbols 23A-aa, 23A-bb, and 23A-cc to prevent multipath interference.

  FIG. 3B shows a power supply state to the power supply terminal 16 to the tuner unit 2 with respect to time in the conventional example. Even if power is supplied to the power supply terminal 16 as shown in FIG. 3B, a time for stabilizing the AGC voltage is required. For this reason, for example, when viewing a bb program, it is necessary to turn on the power supply terminal 16 of the tuner unit 2 at a time point 27a prior to viewing the bb program in consideration of the AGC stabilization time 27. . Thus, the bb program was watched.

  FIG. 3C shows the supply state of the RFAGC voltage and IFAGC voltage of the tuner unit 32 with respect to time in the present embodiment.

  These RFAGC voltage and IFAGC voltage are stored in the memory 47 at the time when 23A-bb, 23B-bb, and 23C-bb are selected, for example, when a bb program is received.

  The stored RFAGC voltage and IFAGC voltage are respectively supplied to the RF amplifier 37 and the AGC control terminals 37a and 40a of the IF amplifier 40 at a time point 28a earlier than the transmission symbol 23A-bb by time 28. This is the same for both the frame synchronization symbol 22, the transmission symbols 23B-bb, and 23C-bb. That is, the RFAGC voltage and the IFAGC voltage are supplied to the control terminals 37a and 40a of the RF amplifier 37 and the IF amplifier 40 from the time point 28a earlier than the respective symbols by the time 28, respectively.

  As a result, after time 28a, electric charges are charged in the respective capacitors connected to the RFAGC control terminal and the IFAGC control terminal.

  FIG. 3D shows a state of power supply to the power supply terminal 16 to the tuner unit 32 with respect to time in the present embodiment. As shown in FIG. 3D, the power supply to the power supply terminal 16 to the tuner unit 32 is supplied to a time point 29a that is earlier than the transmission symbol 23A-bb by a time 29.

  The same applies to the frame synchronization symbol 22, the transmission symbols 23B-bb, and 23C-bb.

  Thus, at the time point 28a, the RFAGC voltage and the IFAGC voltage are supplied to the AGC control terminals 37a and 40a. The time point 28a may be between the end time point 22a of the frame synchronization symbol 22 and the time point 29a when power is supplied to the power supply terminal 16 corresponding to the transmission symbol 23A-bb.

  After the power supply voltage is supplied to the power supply terminal 16 at this time 29a, the RFAGC voltage and the IFAGC voltage are set to predetermined voltages at time 29. That is, the time 29 may be a time for setting the RFAGC voltage and the IFAGC voltage to predetermined voltages. At the same time, this time 29 needs to be set larger than the time during which the oscillation frequency of the oscillator 38 is stabilized.

  As a result, it is not necessary to supply power to the power supply terminal 45 to the tuner unit 32 during the entire stabilization time 27 of the RFAGC voltage and the IFAGC voltage as in the prior art. There is no need to supply power to the power terminal 45. The same applies to the case where the transmission symbol 23B-bb or the transmission symbol 23C-bb is selected.

  Even when only the RFAGC voltage is supplied to the control terminal 37a of the RF amplifier 37 at the time point 28a, the power consumption can be reduced. That is, when the digital signal received by the antenna 34 is at a high level, both the RFAGC voltage and the IFAGC voltage change to perform gain control. In this case, the gain control amount based on the RFAGC voltage is set larger than the gain control amount based on the IFAGC voltage in order to ensure the interference performance.

  For this reason, the gain control amount per unit voltage of the RFAGC voltage becomes large and becomes sensitive to, for example, power supply noise. In order to prevent this, since a capacitor having a large capacity is connected between the AGC control terminal 37a and the ground for charging, the time for stabilizing the RFAGC voltage becomes long.

  On the other hand, the gain control amount per voltage of the IFAGC voltage becomes small, and a capacitor having a small capacity can be used between the AGC control terminal 40a and the ground, so that it is stabilized in a short time.

  That is, as the power consumption reduction effect, the effect of the RFAGC voltage is large, and the effect of IFAGC is small.

  The mixer 39 may be direct conversion. In this case, the mixers 39b and 39c are used instead of the mixer 39, a digital signal is supplied to one input of the mixers 39b and 39c, and the signal of the oscillator 38 is input to the other input of the mixer 39b. Then, a signal obtained by changing the phase of the signal of the oscillator 38 by 90 degrees is input to the other input of the mixer 39c.

  Thereby, I and Q signals are output from the mixers 39b and 39c. As described above, when direct conversion is performed using the mixers 39b and 39c, the influence of the image interference signal does not occur. Further, the outputs of the mixers 39b and 39c are connected to an LPF (low-pass filter), and integration is easy.

  Further, a mixer 39d (not shown) and a BPF 39d (not shown) may be inserted between the RF amplifier 37 and the mixer 39 in this order. In this case, the intermediate frequency signal output from the mixer 39d is connected to the BPF 39d. For example, the adjacent interference signal can be sufficiently suppressed by the BPF 39d, so that the digital signal receiving device 31a resistant to the interference signal can be realized.

(Embodiment 2)
FIG. 4 is an explanatory diagram of signal switching while the digital signal receiving device 31 according to the second embodiment is moving. Control when the digital signal receiving apparatus 31 moves from the first cell 51a to the second cell 52a adjacent to the first cell 51a will be described.

  When the digital signal receiving device 31 moves from the reception range 51 from the first cell 51a to the reception range 52 of the second cell 52a, there is a reception range 53 in which signals output from both the cells 51a and 52a can be received together. To do. When entering the reception range 53, the radio wave of the cell 52a is received during the broadcast of a program other than the desired program, and the broadcast RFAGC voltage and IFAGC voltage output from the cell 52a are stored in the memory 47.

  Then, the received radio wave is switched to the cell 52a, and the control of the RFAGC voltage and the IFAGC voltage is also switched. This enables smooth switching even during movement.

  In the digital signal receiving apparatus of the present invention, power can be saved by supplying the AGC control voltage and then supplying power to the tuner. Therefore, the digital signal receiving apparatus can be applied particularly to a portable digital signal receiving apparatus.

1 is a block diagram of a digital signal receiving apparatus according to Embodiment 1 of the present invention. (A) is a time chart of a frame structure of a digital signal, (b) is a time chart when a bb program is received. (A) is a time chart of frame synchronization symbols and transmission symbols, (b) is a time chart of power supply voltage supplied to the tuner power supply terminal 16 in the conventional example, and (c) is an RFAGC voltage in the first embodiment. IFAGC voltage time chart, (d) is a time chart of power supply voltage supplied to the tuner power supply terminal 45 Explanatory drawing of signal switching while the digital signal receiving apparatus in the second embodiment is moving Block diagram of a conventional digital signal receiver

Explanation of symbols

31 Digital Signal Receiver 32 Tuner 35 Antenna Terminal 37 RF Amplifier 38 Oscillator 39 Mixer 39a AGC Controller 43 Demodulator 44 Output Terminal 45 Power Terminal 46 Controller

Claims (6)

In a digital signal receiving apparatus for receiving a digital signal having a transmission frame composed of time-division symbols, an antenna terminal to which the digital signal is input, a digital signal from the antenna terminal is supplied, and gain control is performed. A first amplifier having a possible first AGC terminal, and a first mixer having the output of the first amplifier supplied to one input and the output of the oscillator connected to the other input; A tuner unit including a first AGC controller that outputs a comparison voltage obtained by comparing a signal level output from the first mixer with a predetermined first reference value; and output from the tuner unit The first AG output from the first AGC controller is provided with a demodulator to which the received signal is supplied and an output terminal from which the demodulated signal from the demodulator is output. A control unit for inputting a voltage and a symbol output from the demodulator is provided, and is output via the control unit before the start of a symbol necessary for viewing a desired program among the symbols. A digital signal receiving apparatus that supplies a power supply voltage from the control unit to the tuner unit after supplying the first AGC voltage to the first AGC terminal. The digital signal receiving apparatus according to claim 1, wherein the first mixer is a direct conversion. The digital signal receiver according to claim 1, wherein a second mixer is inserted between the first mixer and the first amplifier. A second amplifier having a second AGC terminal capable of gain control between the first mixer and the output of the tuner section; and a signal level output from the second amplifier is set to a predetermined second level. And a second AGC controller that outputs a comparison voltage compared to the reference value of the signal, and is output from the control unit before the start of the symbol necessary for viewing the desired program among the symbols. The power supply voltage is supplied from the control unit to the tuner unit after supplying the first AGC voltage and the second AGC voltage to the first AGC terminal and the second AGC terminal, respectively. Digital signal receiver. 4. The digital signal receiving apparatus according to claim 3, wherein a memory is connected to the control unit, and the first and second AGC voltages output from the control unit are stored in the memory. When moving from the first cell to the second cell adjacent to the first cell, the first AGC voltage and the second AGC in the second cell at a time other than receiving the selected symbol. The digital signal receiving apparatus according to claim 5, wherein the digital signal receiving apparatus acquires voltages and stores the first AGC voltage and the second AGC voltage in a memory.

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