JPH07288499A - Clock intermittent demodulation circuit and intermittent reception demodulation device - Google Patents

Abstract

PURPOSE:To provide an intermittent demodulation circuit which can quickly start the phase control and can shorten the ON time of a receiver by providing a circuit which stops in a power OFF state after holding the frequency and the phase of a symbol clock and a circuit which always oscillates. CONSTITUTION:A reference clock 36 is always oscillated, and the power supplies of other circuits are intermittently turned on and off to wait for reception of the clocks 36. In a power ON state, a reception circuit 32 and a detection identifying circuit 34 demodulate the received signals and send the timing detection signals contained in the demodulation data to a BTR circuit 35 as the clock control signals. A U/P counter 47 operates by the output of a phase detector 46 to change the dividion ratio of a variable division circuit 48 and to set the phsse difference at zero between a symbol clock fS and the signal 39. When the power supply is turned off, the output of the counter 47 is set at zero and the division ratio is set at 1/n. The clock fS keeps its phase that is set right before the signal 39 is cut. In a power ON state, the phase is detected in a state set right before the power supply is turned off. Thus the phase control is quickly started.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to intermittent clock demodulation and intermittent reception of digital mobile communication equipment and the like.

[0002]

2. Description of the Related Art Conventionally, there is a clock demodulating circuit of this type shown in FIG. In the figure, 1 is an antenna, 2 is a receiver, 3 is a demodulator, 4 is a detector and discriminator in the demodulator, 5
Is a BTR (Bit Timing Recovery circuit) in the demodulator, 6
Is a reference clock oscillator that supplies a clock of the frequency at which the BTR is based. 7 is power ON / OFF of the receiver 2
Control signal, 8 is an IF signal input to the demodulator 3, and 9 is B
A control signal of TR3, 10 is a symbol clock f _s generated by BTR3, 11 is demodulated data, 12 is an original clock of BTR3, and 13 is a power save signal of demodulation circuit 3. Further, there is FIG. 4 for explaining the operation of FIG. In FIG. 4, the horizontal axis represents time, and the vertical axis represents “H” and “L” logic levels. In the figure, 14 is a receiver power ON / OFF signal, 15 is a receiver power ON timing, 16 is a demodulator power ON timing, 17 is a timing to start demodulating correct data, 18 is a receiver OFF and demodulator power down And 19 indicates the length of one cycle of intermittent standby.

Next, the operation will be described. The BTR and the reference clock oscillator are so-called phase loop control circuits (P
LL). The signal input from the antenna 1 is converted into an IF signal 8 by the receiver 2 and input to the demodulator 3. In the demodulator 3, the detection discriminator 4 demodulates the data 11 and sends the control signal 9 to the BTR 5. In the BTR 5, the oversampling clock 12 input from the oscillator 6 is phase-controlled and frequency-divided based on the control signal 9, and the symbol clock 10 is sent to the outside of the detection discriminator 4 and the demodulator. The basic operation of the BTR will be described.
The BTR gives a timing clock (symbol clock f _s ) for identifying the received and detected signal. In normal operation, the clock component included in the detected signal is extracted and the symbol clock f _s as an output also includes the received wave. Reproduce so as to follow the clock component. As for the control accuracy, assuming that the oscillation frequency of the reference clock is n × f _s , the clock is reproduced with the phase of one clock, that is, the accuracy of 360 ° / n. Further, since the control speed is configured such that the 360 ° / n phase is shifted once for each reproduction clock m (m is an arbitrary natural number), for example, the time ΔT _d required to shift the α ° phase is ΔT _d = α × (1/360 ° / n) × (m / f _s ).

Next, the operation of the digital reception demodulation circuit shown in FIG. 3 when performing intermittent reception will be described with reference to FIG. In FIG. 4, the reception demodulation circuit repeats ON and OFF of the receiver at a constant interval 19. Receiver ON, O
The FF signal 14 turns on the receiver at the timing 15.
The demodulator 3 is powered on and starts to operate at a timing 16 after the receiver rises and stabilizes. Until the timing 17 when the demodulator 3 powers on and outputs correct data, there is a large phase difference between the phase of the BTR f _s and the clock component included in the detection signal. It takes time to follow until the phase difference becomes zero. That is, T _d 'in FIG. 4 becomes longer. After the reception, at timing 18, the receiver power is turned off and the demodulator power down is performed. This is repeated at a constant cycle T _s '19.

[0005]

Since the conventional digital communication demodulation circuit is constructed as described above, it takes a relatively long time from the power-on of the demodulator to the output of correct data, and as a result, the receiver There is a problem that it is necessary to take a long time to turn on the power.

The present invention has been made in order to solve the above problems. An intermittent demodulation circuit in which the time from the power-on of the demodulator to the output of correct data is shortened and the receiver is on. It is an object of the present invention to obtain an intermittent demodulation device whose time is shortened.

[0007]

A clock intermittent demodulation circuit according to the present invention has a demodulation circuit for intermittently turning on and off the power supply and demodulating a received signal which has been awaited and received, and a reference clock which is always turned on and has a power supply. When off, a phase control circuit that outputs the phase difference and the frequency difference between the clock control signal from the demodulation circuit and the oscillation frequency based on the reference clock within a constant value while holding the frequency and phase of the symbol clock for the received signal Equipped with.

Furthermore, the phase control circuit counts up or down the phase difference at the phase comparator that compares the difference between the clock control signal from the demodulation circuit and the output of the variable frequency divider circuit described below. And a variable frequency dividing circuit that changes the frequency division ratio from the specified 1 / n to 1 / n + 1 or 1 / n-1 when the up / down counter exceeds a predetermined value. It is a phase control circuit.

The intermittent reception demodulator according to the present invention includes a receiving circuit for intermittently turning on and off the power source for standby reception, a demodulation of a reception signal of the reception circuit to obtain demodulation data, and a timing detection in the reception signal. A demodulation circuit that gives a signal to the phase control circuit as a clock control signal, and has a reference clock that is always powered on.When the power is on, the phase and frequency of the clock control signal from the demodulation circuit and the oscillation frequency based on the reference clock The symbol clock for demodulated data is output so that the difference becomes zero, and when the power is off, the phase difference between the clock control signal and the oscillation frequency based on the reference clock and the frequency difference are set within a certain value to set the frequency and phase of the symbol clock. And a phase control circuit for holding and outputting.

Furthermore, the phase control circuit counts up or counts down the phase difference at the phase comparator which compares the difference between the clock control signal from the demodulation circuit and the output of the variable frequency dividing circuit described later. And a variable frequency dividing circuit that changes the frequency division ratio from the specified 1 / n to 1 / n + 1 or 1 / n-1 when the up / down counter exceeds a predetermined value. It is a phase control circuit.

[0011]

In the intermittent clock demodulation circuit according to the present invention, the phase control circuit is always powered on in contrast to the receiving circuit whose power is intermittently turned on and off, and the phase control circuit is receiving the receiving circuit while the receiving circuit is powered off. A clock is generated based on the phase immediately before the power is turned off.

Further, in more detail, the phase circuit compares the extracted clock from the demodulation circuit with the clock of the variable frequency divider circuit, and if there is a difference, counts up or counts down and the counter output shows a predetermined value. When it exceeds, the variable frequency dividing circuit changes the frequency dividing ratio and generates and outputs clocks having different frequencies.

The intermittent reception demodulator according to the present invention generates a symbol clock by performing phase control for normal demodulated data when the power of the receiving circuit is on, and when the power is off, the phase and frequency immediately before that. Continues to output the symbol clock, and when power is turned on, phase control is started from the phase and frequency.

Further, more specifically, the phase circuit compares the extracted clock from the demodulation circuit with the clock of the variable frequency divider circuit, and if there is a difference, it counts up or counts down, and the counter output shows a predetermined value. When it exceeds, the variable frequency dividing circuit changes the frequency dividing ratio and generates and outputs clocks having different frequencies.

[0015]

【Example】

Example 1. An embodiment of the intermittent clock demodulation circuit of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of this embodiment. In the figure, 31 is a receiving antenna, 32 is a receiver, and 33 is a demodulator as a whole. Three
4 is a detection identification circuit in the demodulator, 35 is a BT in the demodulator
R (Bit Timing Recovery circuit), 36 is a reference clock oscillator for BTR. 37 is a receiver power control signal,
44 is a gate, 46 is a phase comparator, 47 is an up / down counter, and 48 is a variable frequency dividing circuit. Further, FIG. 2 is an operation timing chart corresponding to the conventional FIG. A horizontal axis represents time, and one cycle in which the receiver is turned on and off is TS indicated by 49. Reference numeral 15 is a power-on, 16 is a timing when the demodulator is powered on, and 50 is a timing when the demodulator is in a steady state.

Next, the operation will be described while describing the names of signals. The received signal input from the antenna 31 is
In the receiver of 32, it is converted into the control signal 38, is input to the demodulator of 33, is demodulated by the detection discriminator 34 of the demodulator 33, and output data 43 is output. At this time, the timing is detected and the phase control signal 39 is sent to the BTR 35. The BTR 35 and the reference clock generator 36 are always on. In FIG. 4, the demodulator 33 is operating normally as a whole in the state where the demodulator after timing 16 is turned on, and at this time the detection discrimination circuit 3
4 from the phase control signal 39 to the phase comparator 4 in the BTR 35.
Added to 6. The BTR is a signal 4 which is either up, down, or zero depending on the output of the phase comparator.
5, the up / down counter 47 counts up or down based on the command of the command signal 45. Then, when the up / down counter is increased by a predetermined amount of m, the frequency division ratio designating signal changes from 1 / n to n +.
It changes so that it becomes one-half, and based on this, the variable frequency dividing circuit changes to n + 1. Then, the oversampling clock nf _s output from the reference clock oscillator 36 is variably divided, fed back to the phase comparator as the symbol clock f _s 40, and given to the detection discrimination circuit as a timing signal.

To supplement this operation based on FIG. 2, the intermittent demodulation circuit is turned on at a constant interval TS49.
Turned off. At timing 15, the power is turned on, and until timing 51 at which the power is turned off, all the receivers are powered on and the standby operation is performed. When the receiver turns on at the timing of 15, the BT
The parts other than R reach the normal state. Timing 16
Then, the gate 44 shown in FIG. 1 is controlled so that the output of the phase comparator causes the up / down counter to be up, down, or zero. In this state, with the symbol clock,
If there is a phase difference with the phase control signal 39 from the detection identification circuit, the variable frequency dividing circuit shifts so as to eliminate it. Then, at the timing 50, the phase difference becomes zero, and the reception timing detected by the detection discrimination circuit matches the symbol clock.

Further, even when the power is turned off at the timing 51, the BTR reception clock oscillator 3 shown in FIG.
6 is a state in which the power is kept on. Therefore, although this portion operates differently from the demodulator, the gate 44 is forcibly turned off because the phase control signal 39 from the detection discrimination circuit disappears. That is, the gate remains closed from the power-off timing 51 to the timing 16 when the next power supply is turned on and all but the BTR are in the steady state. Therefore, the output of the up-down counter is zero, that is, the frequency division ratio designation signal is n. One-half remains specified. Therefore, the symbol timing f _{s of the} output of the variable frequency divider circuit simply maintains the reference clock divided by 1 / n. Further, the phase holds the phase immediately before the control signal 39 is cut off. Subsequent phase shifts are determined by the accuracy of the phase error included in the oversample clock 42. Assuming that the time during which the gate 44 is cut off is T _i in the figure, the phase shift amount Δθ during this period is Δθ = 360 ° × Δf × T _i . When the length and period of T _i are constant as in the case of intermittent reception, if Δf is designed accurately, Δθ can be suppressed within a certain constant value. That is, it is possible to reduce the value of Δθ between T _i , and to suppress the amount of phase shift that occurs at the timing 16 at which the power supply is turned on next, except for the BTR, which is in the steady state. Therefore, the time from the timing 16 to the timing 50 or the timing T _{d of the} steady state 50 from the timing of the power-on 15
Can be shortened.

Example 2. In the first embodiment, the gate 44 is turned on and off by using the control signal 46 from the outside. However, the gate 44 itself may be powered on or off.

Example 3. The first embodiment refers to the intermittent clock demodulation circuit. However, if it is applied to the intermittent reception demodulation device incorporating this clock intermittent demodulation circuit, the time T _d after power-on shown in FIG. 2 is shortened, and therefore the entire repetition period T _s can be shortened. Alternatively, the power-off cycle T _i can be lengthened. By doing so, it is possible to reduce the power consumption of the power supply for the receiver, and it is possible to shorten the time for turning on the power supply of the receiver.

[0021]

As described above, according to the present invention, the demodulation circuit for turning on / off the power supply and the phase control circuit for keeping the phase difference and the frequency difference at zero when the other circuit is always turned on and the power supply is off are provided. The phase difference that the demodulator circuit controls even when the power is turned on starts control, and as a result, the phase difference is detected from the state immediately before the power is turned off. There is.

Furthermore, since the up-down counter and the variable frequency dividing circuit are provided, there is an effect that it is easy to hold the phase difference at power-off to zero.

Further, according to the intermittent reception demodulation device of the present invention, the demodulation circuit for turning on / off the power supply and the phase control circuit for keeping the phase difference and the frequency difference at zero when the other circuit is always turned on and the power supply is off are provided. , The demodulation circuit starts control as the phase difference to be controlled even when the power is turned on is within a certain value, and as a result, the phase difference is detected from the state immediately before the power is turned off. There is an effect that power consumption is reduced by shortening the

Furthermore, since the up-down counter and the variable frequency dividing circuit are provided, it is easy to hold the phase difference of zero, and the following operation is guaranteed when the power is turned on.

[Brief description of drawings]

FIG. 1 is a block diagram of a clock intermittent demodulation circuit that is an embodiment of the present invention.

FIG. 2 is a timing chart illustrating the time relationship of the operation of the clock intermittent demodulation circuit of FIG.

FIG. 3 is a block diagram of a conventional digital reception demodulation circuit.

FIG. 4 is a timing chart illustrating the operation of a conventional digital reception demodulation circuit.

[Explanation of Codes] 31 Reception Antenna 32 Receiver 33 Digital Demodulator 34 Detection Discrimination Circuit 35 BTR (Bit Timing Recovery Circuit) 36 Reference Clock Oscillator 44 Gate 46 Phase Comparator 47 Up / Down Counter 48 Variable Divider Circuit

Claims (4)

[Claims] 1. A demodulation circuit for intermittently powering on and off and demodulating a received signal that has been received in standby, a clock control signal from the demodulation circuit and the reference clock when the power is turned off, and has a reference clock. A clock intermittent demodulation circuit including a phase control circuit for holding and outputting a frequency and a phase of a symbol clock for a received signal with a phase difference between the oscillation frequency and the oscillation frequency within a constant value. 2. The phase control circuit includes a phase comparator for comparing a difference between a clock control signal from the demodulation circuit and an output of a variable frequency divider circuit described later, and a phase difference is counted up by the output of the phase comparator or It is composed of an up-down counter that counts down, and a variable frequency dividing circuit that changes the frequency division ratio from a prescribed 1 / n to 1 / n + 1 or 1 / n-1 when the up / down counter exceeds a predetermined value. The clock intermittent demodulation circuit according to claim 1, which is a phase control circuit. 3. A receiving circuit for intermittently turning on and off the power source to perform stand-by reception, demodulating a received signal of the receiving circuit to obtain demodulated data, and phase control using a timing detection signal in the received signal as a clock control signal. The demodulation circuit to be supplied to the circuit and the reference clock that is always turned on, and when the power is turned on, demodulation data is set so that the phase difference between the clock control signal from the demodulation circuit and the oscillation frequency based on the reference clock is zero. Output the symbol clock for
An intermittent reception demodulation device comprising: a phase control circuit that outputs the phase difference and the frequency difference between the clock control signal and the oscillation frequency based on the reference clock within a constant value when the power is turned off, while maintaining the frequency and phase of the symbol clock. 4. The phase control circuit further comprises a phase comparator for comparing a difference between a clock control signal from the demodulation circuit and an output of a variable frequency divider circuit, which will be described later, and counts up the phase difference with the output of the phase comparator. It is composed of an up-down counter that counts down, and a variable frequency dividing circuit that changes the frequency division ratio from a prescribed 1 / n to 1 / n + 1 or 1 / n-1 when the up / down counter exceeds a predetermined value. 4. The intermittent reception demodulator according to claim 3, which is a phase control circuit.