JP3154624B2 - Digital data receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital data receiving apparatus used for automobile telephones, portable telephones, cordless telephones, MCA, and the like.

[0002]

2. Description of the Related Art FIG. 3 shows an example of a conventional digital data receiving apparatus. In FIG. 3, reference numeral 31 denotes a demodulation unit integrated circuit;
2 is an antenna, 33 is a receiver, 34 is a local oscillator, 35
Denotes a temperature-compensated crystal oscillator (hereinafter abbreviated as TCXO),
36 is a demodulator, 37 is a transmission clock recovery circuit, 38 is an oscillation circuit, 40 is a power switch, 41 is a CPU (Central Processing Unit), and 42 is an oscillation circuit. Reference numeral 44 denotes reproduced data, 45 denotes a clock, 46 denotes a power control signal, 47 denotes a transmission clock, and 48 denotes a clock reproduced signal.

In the above configuration, the antenna 32, the receiver 33, and the demodulator 36 generate reproduced data 44 from the received radio waves. The TCXO 35 generates a high-precision clock 45, and the local oscillator 34 divides and multiplies the clock 45 to generate a signal for selecting a frequency of a radio wave to be received.
The power of the TCXO 35 is supplied by a power control signal 46 controlled by the CPU 41 and a switch 40. The transmission clock reproducing circuit 37 is a digital P / P having a variable frequency dividing circuit.
During reception, the demodulator 36 reproduces a transmission clock 47 synchronized with the detected clock reproduction signal 48 during reception. In the non-reception time in which the data receiving apparatus performs intermittent reception (periodically receiving only the time when the incoming data of its own device is sent) in the incoming call waiting state, the transmission clock reproducing circuit 37 outputs the signal from the oscillation circuit 38. The transmission clock 47 is kept in synchronization with the base station by fixedly dividing the clock. CP
U41 is operated by the clock of the oscillation circuit 42.

As described above, in the conventional digital data receiving apparatus, reproduction of the transmission clock with the base station during intermittent reception, synchronization of the transmission clock with the base station, and synchronization maintenance of the transmission clock during intermittent non-reception are performed, respectively. It is possible.

[0005]

However, in the above-mentioned conventional digital data receiving apparatus, the oscillation circuit 38 needs to generate a high-precision clock in order to hold the transmission clock with high precision during intermittent non-reception. The oscillation circuit 38 could not be reduced in size and cost.

Further, since the CPU 41 operates on the clock of the oscillation circuit 42, the current consumption of the oscillation circuit 42 cannot be reduced.

The present invention solves such a conventional problem. A high-precision clock generated by a TCXO used in a receiver is shared by a transmission clock recovery circuit and a CPU, and during intermittent non-reception. An excellent digital device that can hold a transmission clock with high precision, and furthermore, a built-in CPU in the demodulation unit integrated circuit and supplies the operating clock of the CPU inside the integrated circuit to reduce current consumption in the oscillation circuit. It is an object to provide a data receiving device.

[0008]

According to the present invention, in order to achieve the above object, a capacitor, an inverter with a feedback resistor, and a frequency divider are provided between a TCXO and a transmission clock recovery circuit to transmit a clock signal of the TCXO. It can be used in a clock recovery circuit.

The present invention also provides an operation clock from an oscillation circuit for providing a clock for starting operation of the CPU from a state where the digital data receiving device is stopped and the TCXO is stopped, and a TCXO for normal operation. The operation clock from the switch is switched by a switch.

[0010]

Therefore, according to the present invention, the DC component of the clock generated by the TCXO is removed by the capacitor, amplified to the CMOS level by the inverter, and supplied to the transmission clock reproducing circuit via the frequency dividing circuit.
The TCXO can be shared by the local oscillator and the transmission clock recovery circuit.

[0011] The present invention also relates to a case where the power supply is turned off.
The CPU and TCXO are stopped, and the operation of the device is
Start by power on interrupt to At the start of the operation, the CPU operates with a clock from an oscillation circuit that can be controlled by the CPU, then operates TCXO, and sets the clock to T
By switching to the operation clock from the CXO and stopping the oscillation circuit controlled by the CPU, current consumption can be reduced.

[0012]

FIG. 1 shows the configuration of an embodiment of the present invention. In FIG. 1, 1 is a demodulation unit integrated circuit, 2 is an antenna, 3 is a receiver, 4 is a local oscillator, 5 is a temperature compensated crystal oscillator (TCXO), 6 is a demodulator, 7 is a transmission clock recovery circuit, and 8 is A capacitor, 9 is an inverter with a feedback resistor, 10 is a frequency divider, 11 is a CPU, 12 is an oscillator power switch, 13 is a device power switch, 14 is an oscillation circuit,
Reference numeral 15 denotes a clock switch. Reference numeral 21 denotes reproduced data, 22 denotes a clock, 23 denotes a power switch 12
, A power switch control signal 24, an on / off request signal for the power switch 13, 25 and 26 operating clocks of the CPU 11, 27 a clock switching control signal, 28 a reproduced transmission clock, and 29 a clock reproduction signal.

In the above configuration, the antenna 2, the receiver 3, and the demodulator 6 generate reproduced data 21 from the received radio waves. The TCXO 5 generates a high-precision clock 22, and the local oscillator 4 divides and multiplies the clock 22, and generates a signal for selecting a frequency of a radio wave to be received. Also TC
The power of the XO5 is supplied by a power switch control signal 23 controlled by the CPU 11 and the oscillator power switch 12. The transmission clock recovery circuit 7 removes the DC component of the clock 22 generated by the TCXO 5 by the capacitor 8, converts the DC component to a CMOS level by the inverter 9, and operates with the clock generated by the frequency divider 10. The transmission clock recovery circuit 7 is composed of a digital PLL provided with a variable frequency dividing circuit, and the clock recovery signal 29 detected by the demodulator 6 during reception.
To reproduce the transmission clock 28 synchronized with. In the non-reception time during which the data receiving apparatus performs intermittent reception (periodical reception of only the time at which the incoming data of its own device is sent) in the incoming call waiting state, the transmission clock recovery circuit 7 sets the TCX
The high-precision clock 22 from O5 is fixedly divided to keep the transmission clock 28 in synchronization with the base station. On the other hand, CPU
11 is an operation clock 26 of the oscillation circuit 14 or TCX
The operation is performed by an operation clock 25 obtained by dividing the clock 22 of O5, and the clock is switched by a control signal 27 and a switch 15.

Next, an operation by switching the power supply switch 13 on and off will be described with reference to FIG.
The power of the device is turned on / off by turning on the demodulation unit integrated circuit 1
This is performed in software by an interrupt generated by the device power switch 13 to the CPU 11. In the power-on state, the TCXO 5 is stopped. Therefore, when the power of the apparatus is turned on, the CPU 11 receives the power-on interrupt, operates the oscillation circuit 14, selects the operation clock 26, and starts processing. The CPU 11 immediately sends the power switch control signal 23
Turns on the oscillator power switch 12 to turn on the power of the TCXO5. Thereafter, the CPU 11 sets the operation clock 2
6 is switched to the operation clock 25 from the TCXO 5, the oscillation circuit 14 is stopped, the current consumption in the oscillation circuit 14 is reduced, and the operation shifts to the normal operation. On the other hand, when the device is turned on from power on, the oscillation circuit 14 is operated by an interrupt generated by the device power switch 13 and the operation clock is set to 25.
To 26. Thereafter, the CPU 11 turns off the power switch 12 by the power switch control signal 23 and
Turn off the power of CXO5. Further, after performing the stop processing of the device, the CPU 11 waits for a power-on interrupt, and terminates the stop processing of the oscillation circuit 14.

As described above, according to the above-described embodiment, since the transmission clock recovery circuit 7 is operated by the high-precision clock generated by the TCXO 5, the high-precision clock is used even during the non-intermittent reception performed in the incoming call waiting state. Synchronous holding is possible. Further, by sharing the clock between the receiver 3 and the demodulator 6, the number of oscillation circuits can be reduced. Further, during normal operation, the operation clock of the CPU 11 is set to TC
Since the signal is supplied from the XO 5, the oscillation circuit 14 for supplying the operation clock of the CPU 11 can be stopped, and low current consumption can be realized. The frequency generated by the TCXO 5 is an integral multiple of the least common multiple of the PLL comparison frequency of the local oscillator 4 of the receiver 3 and the digital PLL of the transmission clock recovery circuit 7 of the demodulator 6.

[0016]

According to the present invention, as is apparent from the above embodiment, the transmission clock recovery circuit operates a high-precision clock generated by the TCXO through a capacitor, an inverter, and a frequency dividing circuit, and the local clock of the receiver can be obtained. Since it is shared, it is possible to maintain synchronization with a high-precision clock even during non-reception of intermittent reception performed in the incoming call waiting state. Further, by sharing a clock between the receiver and the demodulator, the number of oscillation circuits can be reduced. Further, during the normal operation, the CPU operating clock is frequency-divided from the TCXO and supplied inside the integrated circuit. During that time, the oscillation circuit that supplies the CPU operating clock can be stopped, thereby reducing current consumption. Can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a digital data receiving device according to an embodiment of the present invention.

FIG. 2 is a flowchart showing an operation of the apparatus by switching on / off a main power switch.

FIG. 3 is a block diagram showing a configuration of a digital data receiving apparatus in a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Demodulation part integrated circuit 2 Antenna 3 Receiver 4 Local oscillator 5 Temperature compensated crystal oscillator (TCXO) 6 Demodulator 7 Transmission clock regeneration circuit 8 Capacitor 9 Inverter with feedback resistor 10 Divider circuit 11 CPU 12 Oscillator power switch 13 Device power supply Switch 14 Oscillator 15 Clock switch 21 Reproduced data 22 Clock 23 Power switch control signal 24 On / off request signal 25, 26 is operating clock 27 Clock switching control signal 28 Transmission clock 29 Clock reproduced signal

Claims (2)

(57) [Claims] 1. A receiver for receiving a radio wave through an antenna, a demodulator for demodulating reproduced data from the received radio wave,
A local oscillator that selects a frequency of a radio wave received by the receiver using a clock from a temperature-compensated crystal oscillator, and a transmission clock recovery circuit that recovers a transmission clock synchronized with a clock recovery signal detected by the demodulator, The temperature-compensated crystal oscillator includes a capacitor connected in series between the transmission clock recovery circuit, an inverter with a feedback resistor, a frequency dividing circuit, and a CPU for controlling power supplied to the temperature-compensated crystal oscillator. Digital data receiving device. 2. An oscillation circuit for supplying an operation clock of a CPU when the temperature-compensated crystal oscillator is stopped, and a clock switch for switching the operation clock of the CPU between the temperature-compensated crystal oscillator and the oscillation circuit. The digital data receiving device according to claim 1, further comprising a switch.