JP2000049682A - Portable telephone terminal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a portable telephone terminal with which intermittent reception is enabled even in the case of using the widely used oscillator for a clock of 32.768 kHz or the like and the intermittent reception can be continued even when an oscillation frequency is deviated by a temperature change or a change with time. SOLUTION: In the case of intermittent reception, a system control circuit 10 outputs a stop signal to a gate means 99 after the end of receiving processing, stops the supply of bit clocks to a bit counter 91, calculates the counted value of an intermittent counter 94 at the power supply times to a TCXO 14 from the time scheduled to next perform the reception, sets the counted value to a TCXO wakeup position setting means 95, calculates the counted value of the intermittent counter at the times to operate the bit counter again and sets the counted value to a bit counter wake-up setting means 97. Besides, after a value for minimizing an error is calculated and set to the bit counter, the TCXO is stopped.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a portable telephone terminal which performs intermittent reception of periodic reception, and more particularly to a technique for reducing power consumption and cost of intermittent reception in a portable telephone terminal. It is about.

[0002]

2. Description of the Related Art The operation of a portable telephone terminal is performed during a call during which the terminal is always operating, and in a standby state in which only call information, which is intermittently sent from a base station and informs the presence or absence of a call from its own station, is received. There is time. During standby, only the call information is intermittently received, so this is called intermittent reception. A method of reducing power consumption during intermittent reception is described in Japanese Patent Application Laid-Open No. 4-170823.
FIG. 17 shows a configuration example of a conventional mobile phone terminal, and its operation will be described below.

[0003] In the configuration shown in FIG.
Is shared by the transmission circuit 4 'and the reception circuit 3', and transmits and receives radio waves. The transmission circuit 4 'and the reception circuit 3' transmit and receive data via the interface unit 11 'and are connected to the microphone 12 and the speaker 13. The interface unit 11 'includes both A / D and D / A converters, converts an audio signal from the microphone 12 into a digital signal, supplies the digital signal to the transmitting circuit 4', and also receives the digital signal.
Is converted into an audio signal and supplied to the speaker 13. A system control circuit (microcomputer) 10 performs overall control.

[0004] High-speed counter 9'-1 and low-speed counter 9 '
Reference numeral -2 constitutes a frame counter, and performs timing management of a signal digitally transmitted in a frame unit such as a TDMA system. The relationship between the high-speed counter 9'-1 and the low-speed counter 9'-2 is such that when the high-speed counter 9'-1 overflows, the low-speed counter 9'-2 is counted up. The high-speed counter 9'-1 is connected to a first reference oscillator 14 'with high precision and a frequency fck. The low-speed counter 9'-2 has an overflow signal of the high-speed counter 9'-1 and an oscillation frequency, for example. An output signal of a low-speed second reference oscillator 15 ′ such as fck / 512 is selected and supplied by a switch 22 controlled by the system control circuit 10. Further, the low-speed counter 9'-2 is supplied with a signal for adjusting a frame shift from the base station from the receiving circuit 3 '.

[0005] Such a portable telephone terminal is operated by a power supply using a secondary battery 18, and power is supplied to a receiving circuit 3 'and an interface section 11' via a switch 20 'controlled by a system control circuit 10. , Transmission circuit 4 '
Is supplied with power via a switch 19 ′ also controlled by the system control circuit 10. Further, the first reference oscillator 14 ′ and the second reference oscillator 15 ′ are supplied with power alternatively to one selected by the switch 23 controlled by the system control circuit 10. The first mentioned above
Although the reference oscillator 14 ′ has a large current consumption of several mA,
Very high accuracy of ± several ppm, the second reference oscillator 1
5 ′ has a very small current consumption of several μA, but several tens of pp
m and accuracy is low.

During a normal call and during a receiving operation during intermittent reception, the switches 22 and 23 are connected to the a side, and the first
The reference oscillator 14 'and the high-speed counter 9'-1 become active, the second reference oscillator 15' becomes inactive, and the frame can be managed with an accuracy of 1 bit or less.

Next, a period during which reception is not performed during intermittent reception,
In the so-called non-operation period, the switches 22 and 23 are connected to the i side, the first reference oscillator 14 'and the high-speed counter 9'-1 are in the non-operation state, and the second reference oscillator 15' is in the operation state. Becomes The clock supplied to the low-speed counter 9'-2 becomes the clock of the second reference oscillator 15 ', but since the frame is managed by the low-speed counter 9'-2, it is necessary to generate the reception timing after sleep. And intermittent reception can be continued.

As described above, the power consumption can be reduced by stopping the first reference oscillator 14 'during sleep during intermittent reception and using the second reference oscillator 15' with low power consumption. .

[0009]

However, as described above, the conventional portable telephone terminal uses the low-speed counter 9'-2 as described above.
In order to switch between counting up with the overflow signal of the high-speed counter 9'-1 operating with the output signal of the first reference oscillator 14 'or counting up with the output signal of the second reference oscillator 15', The oscillation frequency of the first reference oscillator 14 'had to be an integral multiple of the second reference oscillator 15'. Therefore, the first reference oscillator 1
When the oscillation frequency of 4 'changes, the second reference oscillator 15'
Had to change the frequency. Further, when the oscillation frequency of the second reference oscillator 15 'becomes a special frequency that is not widely used, the reference oscillator of that frequency becomes expensive, which has a problem that the price of the mobile phone terminal is affected. Further, the accuracy of the second reference oscillator 15 'is low, and if the oscillation frequency changes due to a temperature change or an aging change, in the worst case, the reception position after the intermittent shifts, the timing of the frame cannot be managed, and the intermittent reception becomes impossible. There was a problem that it became impossible.

[0010] An object of the present invention is to solve the above problem.
Even if a widely used clock oscillator such as 32.768 kHz is used irrespective of the frequency of the second reference oscillator 15 ', intermittent reception becomes possible, and the oscillation frequency of the second reference oscillator 15' It is an object of the present invention to provide a mobile phone terminal capable of continuing intermittent reception even when the mobile phone terminal shifts due to temperature change or aging change.

[0011]

In order to achieve the above object, a portable telephone terminal according to the present invention comprises a timing reproducing circuit for reproducing and outputting a bit clock of received data from a received signal, and a receiving signal from a base station. A UW (unique word) string, which is a synchronization bit string included in the received data string, and outputs a UW detection signal; a system control circuit for controlling the entire operation of the mobile phone terminal; A secondary battery that supplies power to the terminal, a first reference oscillator that supplies a reference clock required for transmission and reception operations of the mobile phone terminal, and a power supply of the secondary battery to the first reference oscillator; Supplying a switch for disconnecting, a power control unit for controlling connection / disconnection of the switch, and a clock for generating timing necessary for the mobile phone terminal to perform intermittent reception A second reference oscillator that, the UW
A timing control unit that establishes synchronization with the base station based on the detection signal and generates various timings. Here, the timing control unit is a bit counter which is set to a preset value by the UW detection signal, counts up by the bit clock, and can be set to an arbitrary value by the system control circuit, An intermittent counter that is initialized by a detection signal and counts up by a clock generated by the second reference oscillator, first setting means that can be set to an arbitrary value by the system control circuit, and the system control A second setting unit that can be set to an arbitrary value by a circuit, and comparing the set values of the intermittent counter and the first setting unit,
A first comparing means for generating a first coincidence signal when they match, a second value for comparing the set values of the intermittent counter and the second setting means, and generating a second match signal when they match And gate means for supplying and stopping the bit clock supplied from the timing recovery circuit to the bit counter. When the mobile phone terminal performs intermittent reception, after the reception process is completed, the system control circuit outputs a stop signal to the gate means to supply a bit clock to the bit counter. Calculating the count value of the intermittent counter at the power supply time of the first reference oscillator in the first setting means from the scheduled time of the next stop of reception, and setting the count value; Calculating and setting a count value of the intermittent counter at a time at which the bit counter is re-operated, a time at which the bit counter is re-operated with respect to the scheduled time, and the bit counter is re-operated by the intermittent counter Calculate the error with the time
Calculate and set a value such that the error is minimized in the bit counter, output a power stop signal to the power control unit,
The power control unit releases the switch to stop the first reference oscillator, and when the value of the intermittent counter becomes equal to the value set in the first setting means, the first control unit outputs the first reference oscillator.
The comparison means outputs a first coincidence signal to the power supply control section, the power supply control section connects the switch, operates the first reference oscillator, and sets the intermittent counter to the second setting means. The second comparing means outputs a second coincidence signal to the gate means, and the gate means supplies a bit clock to the bit counter to operate the bit counter. And perform reception.

Further, the portable telephone terminal according to the present invention is
When performing intermittent reception, after the reception process is completed, the U
If the UW column cannot be detected by the W detection circuit, the system control circuit sets the set values to be set in the first setting means and the second setting means calculated from the next scheduled reception time by 2 respectively. When the UW column is not detected by the UW detection circuit when performing the next reception after setting to the first setting unit and the second setting unit, the system control circuit includes: A first setting unit calculated from a scheduled reception time, and a second setting unit.
The setting values to be set in the setting means are tripled, respectively.
The first setting means and the second setting means are set.

Further, in the portable telephone terminal according to the present invention, the timing control section captures the bit counter value immediately before the bit counter is set to a preset value by the UW detection signal. The system control circuit outputs a stop signal to the gate means to stop supply of a bit clock to the bit counter, when receiving processing is completed, when receiving intermittently, The bit counter is UW
A difference between a value set by the detection signal and a value captured by the bit counter value capturing means is calculated, and the difference is added to a value set in the bit counter to set the value in the bit counter.

Further, in the portable telephone terminal according to the present invention, the system control circuit calculates a difference between a value set by the UW detection signal by the bit counter and a value captured by the bit counter value capturing means. Then, the calculation of the difference is performed after several reception processes, an average value of the difference is calculated, and the average value of the difference is added to the value set in the bit counter, and the result is set in the bit counter.

Further, when the mobile phone terminal according to the present invention intermittently performs reception, after the reception process is completed, the UW
When a UW column is not detected by the detection circuit, the system control circuit doubles the difference or the average value of the difference to a value set in the bit counter, adds the value, and sets the value in the bit counter. Further, when performing the next reception, if the UW detection circuit cannot detect the UW column, the system control circuit multiplies the value set in the bit counter by three times the difference or the average value of the difference. The values are added and set in the bit counter.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings. The following embodiment of the present invention exemplifies a case where the present invention is applied to a PHS (Personal Handyphone System) using a TDMA / TDD system as a communication system.

FIG. 1 is a block diagram showing the configuration of the mobile phone terminal according to the first embodiment of the present invention. In the configuration shown in FIG. 1, the antenna 1 transmits and receives radio waves to and from a base station. The antenna switch 2 connects the transmitting unit 4 and the antenna 1 at the time of transmission, and connects the receiving unit 3 and the antenna 1 at the time of reception to share the antenna 1 for transmission and reception. The receiving unit 3
The received signal received from the antenna 1 is converted into a low frequency signal. The transmission unit 4 converts the modulated signal from the modulation unit 6 into a high-frequency transmission signal.

The demodulation unit 5 decodes the signal supplied from the reception unit 3 into a digital data sequence and outputs the digital data sequence to the channel codec unit 8. In addition, the demodulation unit 5 includes a timing reproduction circuit 5a that reproduces a bit clock of a digital data string from a signal supplied from the reception unit 3. Note that the timing recovery circuit 5a outputs a free-run clock as a bit clock when a reception signal is not supplied from the reception unit 3. The modulation unit 6 includes a channel codec unit 8
Π / 4 shift digital data string supplied from
The signal is modulated into an SK signal and output to the transmission unit 4. The PLL frequency synthesizer 7 supplies a reference clock to the receiving unit 3 and the transmitting unit 4.

The channel codec unit 8 performs framing / deframing, scrambling / descrambling, error detection, concealment, and the like of TDMA / TDD, which is a PHS communication system. Further, the channel codec section 8 converts the decoded data supplied from the demodulation section 5 into a frame synchronization U
UW that outputs a UW detection signal when detecting a W signal sequence
It has a detection circuit 8a.

The timing control unit 9 generates and controls various timings for performing a transmission / reception operation. The detailed configuration of the timing control unit 9 will be described later. The system control circuit 10 is configured by a microcomputer or the like, and controls the overall operation of the mobile phone terminal.

The audio interface 11 expands the information data from the channel codec 8 by ADPCM,
It is converted to an audio signal by a D / A converter and output from a speaker 13, and an input audio signal from a microphone 12 is converted to a digital signal by an A / D converter, ADPCM-compressed, and output to a channel codec unit 8. I do.

The TCXO 14 is a high-precision clock source composed of a temperature-compensated crystal oscillator.
2 MHz, the PLL frequency synthesizer 7, the demodulation unit 5,
It is supplied to the timing controller 9. The clock oscillator 15 is a clock source that consumes low current and has an oscillation frequency of, for example, 32.7.
68 MHz is supplied to the timing controller 9. here,
The first reference oscillator 14 'described in the prior art is TCXO1
4, the second reference oscillator 15 ′ becomes the clock oscillator 15,
Each corresponds. The TCXO control unit 16 controls the TXCO1
The power supply and disconnection of 4 are performed using the switch 17.

The secondary battery 18 supplies power to the portable telephone terminal. During transmission, a switch 19 controlled by the system control circuit 10 is connected, and power is supplied to the transmission unit 4 and the modulation unit 6. At the time of reception, the system control circuit 10
Is connected to the switch 20, which is controlled by the
Power is supplied to the demodulation unit 5. At the time of transmission or reception, the switch 2 controlled by the system control circuit 10
1 is connected, and power is supplied to the PLL frequency synthesizer 7. Although the switches 19, 20, and 21 are controlled by the system control circuit 10, the switches 19 to 21 are controlled by the timing generated by the timing control unit 9. Is also good.

FIG. 2 is a block diagram showing a configuration of the timing control section 9 in FIG. The timing control section 9 converts a bit counter 91 that counts up with a bit clock supplied from the timing reproduction circuit 5 a, a slot counter 92 that counts up with an overflow signal of the bit counter 91, and a clock supplied from the clock oscillator 15. A frequency dividing circuit 93 that divides the frequency by two, an intermittent counter 94 that counts up with a clock supplied from the frequency dividing circuit 93, a TCXO wake-up position setting means 95, and a count value of the intermittent counter 94 and a TCXO wake-up position setting means 95 A first comparing means 96 for comparing the set value and outputting a coincidence signal when they match, a bit counter wake-up position setting means 97, a count value of the intermittent counter 94 and a set value of the bit counter wake-up position setting means 97 And compare
A second comparing means 98 for outputting a coincidence signal when they coincide with each other
And gate means 99 capable of stopping the supply of the bit clock to the bit counter 91 by a stop signal from the system control circuit 10 and starting the supply of the bit clock by the coincidence signal from the second comparing means 98. You.

The TCXO wake-up position setting means 95 and the bit counter wake-up position setting means 97
More arbitrary values can be set. Although the values of the bit counter 91 and the slot counter 92 change due to the count-up operation, they can be set to arbitrary values by the system control circuit 10.

The count range of the intermittent counter 94 in the timing control section 9 having the above configuration needs to be larger than the intermittent reception cycle when the portable telephone terminal performs intermittent reception.
The frequency dividing circuit 93 lowers the count clock in order to increase the count range of the intermittent counter 94. If the count range of the intermittent counter 94 is sufficiently larger than the intermittent reception cycle, the frequency dividing circuit 93 May be omitted. When the count range of the intermittent counter 94 is smaller than the intermittent reception cycle, the frequency dividing circuit 93 may set the frequency to two or more.

FIG. 3 is a diagram showing a frame structure in the PHS. As shown in FIG. 3, in PHS, 1 in 5 ms.
A frame is composed, and one frame is composed of eight slots. In the figure, Rx1 to Rx4 are a reception period, and Tx1 to Tx4 are a transmission period. Of these, Rx1 and Tx1,
Alternatively, the mobile phone terminal communicates with the base station using one slot for each frame, such as Rx3 and Tx3, in which the transmission and reception interval is 2.5 ms for each frame.

One slot is 625 μs and is composed of a bit string of 240 bits. Therefore, the bit clock is 1 / (625 μs) × 240 = 384 kHz. The bit configuration shown in FIG. 3 shows the bit configuration of a control physical channel for performing intermittent reception.

FIG. 4 shows the relationship between the bit counter 91 and the slot counter 92. As shown in FIG. 4, the bit counter 91 outputs 240 bits to the timing recovery circuit 5.
When the bit counter value changes from 239 to 0, the bit counter 91 overflows and the slot counter 9
2 counts up. Therefore, the bit counter 91
Overflows every 625 μs.

The slot counter value m in FIG.
When the slot counter value is 7, the bit counter 91 overflows and the slot counter 92 counts up.
2 overflows and becomes 0.

Based on this, timing management such as bits, slots, and frames necessary for transmission and reception of the portable telephone terminal is performed. The timing management of frames or more is performed by the system control circuit 10 by, for example, generating an interrupt signal in the system control circuit 10 when the slot counter 92 overflows.

FIG. 5 shows an example of the operation at the time of reception by the portable telephone terminal. FIG. 1 shows an example in which a received signal of Rx1 is assigned to a slot counter value of 0. As shown in FIG. 5, the PLL frequency synthesizer 7 operates stably until the received signal is received. In this example, the slot control value is 5, that is, the bit counter value 200 three slots before the receiving slot is used. The switch 10 is connected to the switch 21 with the slot counter value 7, that is, the bit counter value 120 one slot before the receiving slot, so that the receiving unit 3 and the demodulating unit 5 operate stably. At a preset timing before the reception slot allocated in this way, the switch 2
0, the switch 21 is connected, and power is supplied to the PLL frequency synthesizer 7, the receiving unit 3, and the demodulating unit 5 to perform reception. The switches 20 and 21 are released after the reception is completed. The timing for connecting and disconnecting the switches 20 and 21 is generated by the bit counter 91 and the slot counter 92 in the timing controller 9.
Similarly, in the transmission operation, the switch 19 and the switch 21 are connected and transmission is performed at a preset timing before the transmission position.

During intermittent reception, the portable telephone terminal periodically repeats the receiving operation and the non-operating operation, and does not transmit. In the mobile phone terminal, the operation of the TCXO 14 is stopped to reduce power consumption during the period of non-operation. Hereinafter, the first case in which the mobile phone terminal of the present embodiment performs the intermittent reception operation will be described.
An example of the operation will be described in detail.

During the reception operation during the intermittent reception, the UW detection circuit 8a included in the channel codec section 8 detects the UW sequence in the data structure of the reception signal shown in FIG. When the UW sequence is detected from the received signal, the UW detection circuit 8a
The UW detection signal is output to the timing controller 9. In the timing controller 9, the UW detection signal is connected to a bit counter 91, a frequency divider 93, and an intermittent counter 94.

When the UW detection signal is input to the bit counter 91 of the timing controller 9, the bit counter value is set to, for example, 100, and the reception signal from the base station and the bit counter 91 are synchronized. Thereby, UW
The data after the signal sequence is taken into the system control circuit 10 via the channel codec unit 8, and the receiving process is performed. The UW detection signal is also input to the frequency dividing circuit 93 and the intermittent counter 94 at the same time, and each is reset.

FIG. 6 shows a frequency dividing circuit 93 and an intermittent counter 94.
Shows an operation reset by the UW detection signal. FIG.
As shown in the figure, the frequency dividing circuit 93 and the intermittent counter 94
After being reset by the W detection signal, the intermittent counter 94 becomes 1 at the first rising edge of the output clock of the clock oscillator 15. If the intermittent counter 94 always counts up from 1 after UW detection, the time until the value of the intermittent counter 94 becomes 1 becomes an error. This error is from 0 to one cycle of the output clock of the clock oscillator 15, that is, 1 / (32.768 kHz). When the processing of the received signal is completed, the system control circuit 10 outputs a stop signal to the gate unit 99 to stop supplying the bit clock to the bit counter 91 and stop the bit counter 91.

FIG. 7 shows an example of the configuration of the gate means 99. 9
9-1 is an SR flip-flop, and 99-2 is an AND gate. When a stop signal is input from the system control circuit 10 to the gate means 99, the SR flip-flop 9
The output of 9-1 becomes 0, the bit clock is closed by the AND gate 99-2, and the clock supply to the bit counter 91 stops. When a match signal is input from the second comparing means 98 to the gate means 99, the output of the SR flip-flop 99-1 becomes 1, the gate of the AND gate 99-2 is opened, and the clock to the bit counter 91 is output. Supply is started. Here, the next TC depends on how many frames later the received signal from the next base station is located.
The time until the XO 14 is turned on can be calculated.

FIG. 8 shows a timing example of the wake-up position of the TCXO 14 and the wake-up position of the bit counter 91 at the time of intermittent reception. Upon receiving the UW detection signal, the bit counter 91
Since the count value is set to 100, 140/240 × 62 from the UW detection position to the end of the reception slot.
5 μs. The next reception position is assumed to be n frames later, the wake-up position of the TCXO 14 is assumed to be t slots before the next reception slot position, and the time from the UW detection position of the received signal to the TCXO wake-up position for performing the next reception is defined as the time. Tt
Assuming that x, Ttx is given by: Ttx = 140/240 × 625 μs + 625 μs × (8 × n−1−t) = 625 μs × (140/240 + 8 × n−1−t) Equation (1) Equation (1) above It becomes what is shown in.

In order for the timing control section 9 to generate the timing shown in FIG. 5 to connect the switches 20 and 21 for the next reception, the bit counter 91 is operated three slots before the reception slot. Assuming that the time from the UW detection position of the received signal to the re-operation of the bit counter is Tbit, Tbit is: Tbit = 140/240 × 625 μs + 625 μs × (8 × n−1−3) = 625 μs × (140/240 + 8) × n-4) Expression (2) Expression (2) given above.

The time of Ttx−Tbit, that is, Ttx−Tbit = 625 μs × (t−3) (3) is the time from when power is supplied to the TCXO 14 until oscillation is sufficiently stabilized. Let t be such that

The TCXO wake-up position setting means 95 has Tt
If the intermittent counter value after x hours is set, the TCXO control unit 16 will use
14 can be woken up, and if the intermittent counter value after the Tbit time is set in the bit counter wake-up position setting means 97, the bit counter 91 is woken up by the gate means 99 with the coincidence signal of the second comparing means 98. It becomes possible. The method of calculating the set values set in the TCXO wake-up position setting means 95 and the bit counter wake-up position setting means 97 will be described below.

FIG. 9 shows an example of the coincidence signal generation timing of the first comparing means 96. As shown in FIG. 9, the intermittent counter 94 counts up at the rising edge of the output clock of the clock oscillator 15. First comparing means 96
After the set value of the TCXO wake-up position setting means 95 matches the count value of the intermittent counter 94, a match signal is generated at the first falling edge of the clock oscillator 15. That is, 1/1/3 of the output clock of the clock oscillator 15
Two clocks later, a coincidence signal is generated. The second comparing means 98 also generates a coincidence signal at the same timing.

If the intermittent counter value from the UW detection position of the received signal to Ttx is Ctx, the intermittent counter 94 is a clock having a cycle of 2 / (32.768 kHz) and counts up from 1 instead of 0. (Ctx-1) / (16.384 kHz) + A + B = Ttx Expression (4) Expression (4) holds.

Here, A in the expression (4) indicates that after the count value of the intermittent counter 94 shown in FIG. 9 matches the set value of the TCXO wake-up position setting means 95, a match signal is output from the first comparing means 96. A = 1 / (2 × 32.768 kHz) Expression (5) Expression (5)

In the equation (4), B represents an error from the time the UW is detected by the intermittent counter 94 shown in FIG. The adjustment amount is set to ± 1/2 clocks from the above expression. B = 1 / (2 × 32.768 kHz) Expression (6) Expression (6)

From the equations (4), (5) and (6), (Ctx-1 + 1/2) / (16.384 kHz) = Ttx Equation (7) The above equation (7) is obtained, and Ctx is Since it is an integer, Ctx = int {16.384 kHz × Ttx + 1/2} (8) Expression (8) is obtained. Here, int {X} is the maximum integer not exceeding X.

From equation (1) and equation (8), Ctx
Is as follows: Ctx = int {10.24 × (8 × n−0.417−t) +1/2} = int {81.92 × n−10.24 × t−3.77} (9) It is expressed by the above equation (9).

Similarly, from the UW detection position of the received signal, Tb
If the intermittent counter value up to it is Cbit, (Cbit-1) / (16.384 kHz) + A + B = Tbit (10) Expression (10) The above expression (10) holds.

From equations (5), (6) and (10), (Cbit-1 + 1/2) / (16.384 kHz) = Tbit (11) The above equation (11) is obtained, where Cbit is an integer. Therefore, Cbit = int {16.384 kHz × Tbit + 1/2} (12) Expression (12) is obtained.

From the expressions (2) and (12), Cb
It is expressed as: Cbit = int {10.24 × (8 × n−3.417) +1/2} = int {81.92 × n−34.49} Expression (13) Expression (13) expressed.

Therefore, before the system control circuit 10 enters the non-operating state of the intermittent reception, the Ct calculated by the equation (9) is used.
x is input to the TCXO wake-up position setting means 95, and the Cbit calculated by the equation (13) is input to the bit counter wake-up position setting means 9
7 respectively.

Here, when the bit counter 91 is operated again, the slot cycle and the count-up cycle of the intermittent counter 94 do not have a relationship of an integral multiple even if there is no error in the oscillation accuracy of the clock oscillator 15. As shown in FIG. 10, the ideal slot value and the slot value generated by the intermittent counter 94 have at most-
An error of one count occurs. At the time of actual use, the error of the oscillation accuracy of the clock oscillator 15 is also added, so that the maximum error is further increased.

Since Ttx sets the power-on position of the TCXO 14, if t is set so that the oscillation stabilization time of the TCXO 14 in equation (3) becomes longer than the above-mentioned error, the bit clock accuracy is not required. , Tbit, when the error is large, the deviation between the next scheduled reception position and the position of the received signal from the base station becomes large.

Normally, as shown in FIG. 11, the UW detection circuit 8a controls the UW so that an undesired UW is not erroneously detected.
UW only in the section of several tens of bits before and after the W detection scheduled position
Window control is performed to perform detection. Here, the UW detection scheduled position is defined as the bit counter value of the reception slot being 1
00 is the timing. If the above error increases, the UW position of the received signal from the base station deviates from the expected UW detection position by more than window control, and the UW detection circuit 8a cannot detect the UW.

Then, assuming that there is no error in the oscillation accuracy of the clock oscillator 15, the error between Tbit and Cbit calculated by the equation (13) is subtracted from the values of the bit counter 91 and the slot counter 92, and the value is obtained. Bit counter 9
1. By setting the value in the slot counter 92, the error can be minimized and the ideal slot value in FIG. 10 can be matched. Set values to be set in the bit counter 91 and the slot counter 92 are Bbit and Bslt, respectively.
The calculation method is shown below.

Set value Bb set in bit counter 91
It is a value obtained by subtracting 240 from a value obtained by converting β into the number of bits of the bit counter 91, where β is a value after the decimal point of the count clock of the intermittent counter 94 rounded down by int {X} in Expression (13) and β. Become. Therefore, Bb
It is represented by Bbit = 240−β / (16.384 kHz) × 384 kHz (14) Expression (14)

From the equation (13), β = β = {81.92 × n−34.49} −Cbit β = {81.92 × n−34.49} −int {81.92 × n− 34.49｝ Expression (15) Expression (15) is obtained.

Since the value Bslt set in the slot counter 92 is 5 when the error is 0, the value Bslt is: Bslt = 5-1 = 4 (Bbit ≠ 240) = 5 (Bbit = 240) ) (16)

The system control circuit 10 performs the above-mentioned Bbi
t and Bslt are set in the bit counter 91 and the slot counter 92, respectively. When Bbit = 240, 0 is written to the bit counter 91. After that, the system control circuit 10 outputs a TCXO stop signal for stopping the TCXO 14 to the TCXO control unit 16, stops the TCXO 14, and enters a non-operating state of intermittent reception.

Here, an example of the configuration of the TCXO control unit 16 is shown in FIG. 16-1 is an SR flip-flop. The TCXO stop signal is set to TC from the system control circuit 10.
When input to the XO control unit 16, the output of the SR flip-flop 16-1 becomes 0. The switch 17 controlled by the TCXO control unit 16 is released when the output of the TCXO control unit 16 is 0, and is connected when it is 1. Therefore, when the TCXO stop signal is input from the system control circuit 10, the power supply to the TCXO 14 is stopped, and the first comparing means 9
When a match signal is input from 6, the power supply to the TCXO 14 is supplied.

Since the clock oscillator 15 does not stop even in the non-operating state, the intermittent counter 94 counts up with the clock supplied from the frequency dividing circuit 93. When the set value Ctx set in the TCXO wake-up position setting means 95 matches the count value of the intermittent counter 94, the first comparison means 96
A match signal is output to the TCXO control means 16 and
Power supply to the XO 14 is started. Further, when the count value of the intermittent counter 94 matches the set value Cbit of the bit counter rising position setting means 97, a match signal is output from the second comparing means 98 to the gate means 99, and the operation of the bit counter 91 is restarted. . Bit counter 91
Indicates that the count value is Bbit, and the slot counter 92 indicates Bs.
Counting is started from lt. Second comparing means 9
The coincidence signal of 8 is also output to the system control circuit 10 as a wake-up interrupt signal for notifying that the bit counter 91 has woken up. After the wake-up of the bit counter, the timing control unit 9 operates with the bit clock generated based on the TCXO 14, and the receiving operation can be performed.

FIG. 13 shows a flowchart of the operation of the present embodiment. When the reception processing shown in the processing 101 is completed, the system control circuit 10 outputs a stop signal to the gate means 99 and outputs the bit counter 91 as shown in the processing 102.
Stop the operation of. Then, as shown in process 103,
The value Ctx calculated by the equation (9) is sent to the TCXO wake-up position setting means 95 and the value Cbit calculated by the equation (13)
Is set in the bit counter wake-up position setting means 97, respectively. Here, the same effect can be obtained even if the execution order of the processing 102 and the processing 103 is switched. Next, the value Bbit calculated by the equations (14) and (15) is set in the stopped bit counter 91, and the value Bslt calculated by the equation (16) is set in the slot counter 92, respectively. Thereafter, as shown in process 105, a TCXO stop signal is output to the TCXO control means 16 to stop the operation of the TCXO 14.

During intermittent reception, the system control circuit 10 can maintain intermittent reception by repeating the processes 101 to 106 for each reception operation.

By the way, at the end 101 of the receiving process, the UW
If the detection is not successful, the value set in the TCXO wake-up position setting means 95 in the process 103 is twice the value of Ctx,
The value set in the bit counter wake-up position setting means 97 is C
A value twice the bit is set. If UW cannot be detected twice more consecutively, the set value of the TCXO wake-up position setting means 95 is set to a value three times Ctx, and the set value of the bit counter wake-up position setting means 97 is set to a value three times Cbit. Set each.

With the above operation, even if the oscillation frequency of the TCXO 14 as the first reference oscillator described in the conventional example is not an integral multiple of the oscillation frequency of the clock oscillator 15 as the second reference oscillator. , The timing of the intermittent reception can be maintained, and the intermittent reception can be performed.

FIG. 14 is a block diagram showing the configuration of the timing control section 9 in the mobile phone terminal according to the second embodiment of the present invention. Note that, in FIG. 14, the same reference numerals are given to components that perform the same operations as those described in the first embodiment.

The bit counter value capture means 910 in FIG. 14 captures the bit counter value immediately before the value of the bit counter 91 is set to 100 when the UW detection signal is supplied from the UW detection circuit 8a. .

Hereinafter, the operation of this embodiment will be described in detail. The operation similar to the operation example of the first embodiment is performed from the first reception to the transition to the non-operating state of the intermittent reception. Thereafter, when the set value of the TCXO wake-up position setting means 95 matches the count value of the intermittent counter 94 from the non-operating state of intermittent reception, a match signal is generated from the first comparing means 96, and the TCXO control section 16 sets the switch 17 to Connect and T
Power supply to the CXO 14 is started. Thereafter, when the set value of the bit counter rising position setting means 97 matches the count value of the intermittent counter 94, a match signal is generated from the second comparing means 98, and the supply of the bit clock from the gate means 99 to the bit counter 91 is restarted. , The bit counter 91 starts operating. Thereafter, reception is performed in the reception slot.

During reception, when the UW detection signal is supplied to the timing control section 9 in the UW detection circuit 8a, the bit counter value capture means 910 captures the value immediately before the value of the bit counter 91 is set to 100. . Here, if there is no deviation in the timing from the previous reception to the reception, the counter value of the bit counter 91 becomes 100
Is the UW detection expected position, the bit counter value capturing means 910 captures the bit counter value 99. However, if the oscillation accuracy of the clock oscillator 15 is poor, an error occurs in the value captured by the bit counter value capturing means 910. Assuming that the bit counter value captured by the bit counter value capturing means 910 is eb, the number of bits for this error is γ
Then, γ is given by γ = 99−eb (17) Expression (17)

After completion of the reception processing, the system control circuit 10 stops the bit counter 91, as in the operation example of the first embodiment, and sets the TCXO wake-up position setting means 95 to the value calculated by the equation (9). Ctx is stored in the bit counter wake-up position setting means 97 by the value Cbit calculated by the equation (13).
Are set respectively. Thereafter, in the operation example of the first embodiment, the value Bbi calculated from Expressions (14) and (15) is used.
Although t is set in the bit counter 91 and the value Bslt set in equation (16) is set in the slot counter 92, in the operation of the present embodiment, the set values set in the bit counter 91 and the slot counter 92 are set to the UW detection schedule. The value is set in consideration of the position and γ, which is an error of the bit counter value capturing means 910.

The method of calculating the set values set in the bit counter 91 and the slot counter 92 in the operation of the present embodiment will be described below. Value Bb set in bit counter 91
Since it ′ is a value obtained by adding γ to Bbit, Bbi
From equation (17), t ′ is expressed as Bbit ′ = mod {(Bbit + γ) / 240} = mod {(Bbit + 99−eb) / 240} (18) Equation (18) above. However, mod @ X /
Y｝ is a remainder obtained by dividing X by Y.

The value Bslt ′ to be set in the slot counter 92 is as follows: Bslt ′ = Bslt + int {(Bbit + γ) / 240} = Bslt + int {(Bbit + 99−eb) / 240} (Equation (19)) Is represented.

Accordingly, the control circuit 10 sets the bit counter 91 to the value Bbit 'calculated by the equation (18) and the slot counter 92 to the value Bsl calculated by the equation (19).
t ′ is set. Then, the TCXO control unit 1
Then, a TCXO stop signal is output to No. 6 and the intermittent reception is disabled. The subsequent operation is the same as the operation example of the first embodiment described above.

FIG. 15 is a schematic diagram showing the operation of the present embodiment. FIG. 15 shows a case where β = 0 calculated by Expression (15) for simplification of the description. During non-operation during intermittent reception, timing management is performed by an intermittent counter 94 that counts up based on the output clock of the clock oscillator 15. Due to the error of the oscillation frequency of the clock oscillator 15, in the reception after the non-operation, the UW detection expected position and the UW that detected the UW from the reception signal from the base station are received.
An error γ occurs at the detection position. Therefore, in the present embodiment, the error γ is removed by adding the error γ to the set values of the bit counter 91 and the slot counter 92 in advance.

FIG. 16 shows a flowchart of the operation of the present embodiment. Operations from processing 101 to processing 103 are the same as the operations in the first embodiment. Thereafter, as shown in process 107, the system control circuit 10 reads the bit counter value eb captured by the bit counter value capturing means 910. The error γ is calculated from this eb and equation (17), Bbit ′ is calculated from equation (18), and Bslt ′ is calculated from equation (19). Thereafter, as shown in step 108, Bbit 'is set in the bit counter 91 and Bslt' is set in the slot counter 92.
As shown in FIG. 5, a TCXO stop signal is output to the TCXO control unit 16 to stop the TCXO 14. Processing 10
Step 2 may be performed before the process 107 or before the process 108. During intermittent reception, processing 1
By repeating the process 106 from 01, it is possible to maintain intermittent reception.

By the way, at the end 101 of the receiving process, the UW
If the detection cannot be performed, the value set in the TCXO wake-up position setting means 95 in the process 103 is twice the value of Ctx, and the value set in the bit counter wake-up position setting means 97 is the same as in the operation of the first embodiment. Double Cbit. Also,
The values Bbit 'and Bslt' set in the bit counter 91 and the slot counter 92 in the process 108 are (17)
The value of γ calculated by the equation is doubled, and Bb is again calculated from the equation (18).
It 'is set again by calculating Bslt' from equation (19), respectively. If UW cannot be detected twice more consecutively, the value set in the TCXO wake-up position setting means 95 in the process 103 is three times Ctx, and the value set in the bit counter wake-up position setting means 97 is three times Cbit. And Also, the values Bbit 'and Bslt' set in the bit counter 91 and the slot counter 92 in the process 108
Multiplies γ calculated from equation (17) by three, and again (1
Bbit 'is calculated from equation (8), and Bslt' is calculated from equation (19), and reset.

As described above, in the operation example of this embodiment, even if the accuracy of the oscillation frequency of the clock oscillator 15 is deviated, the deviation is detected and the bit counter 9 is detected.
1. Since the position of the receiving slot can be shifted by the set value of the slot counter 92, it is possible to accurately perform the reception after the non-operation of the intermittent reception. Further, even when the oscillation accuracy of the clock oscillator 15 gradually increases due to a temperature change, an aging change, or the like, the amount of the error can be sequentially updated, so that intermittent reception can be performed.

Further, γ calculated from the equation (18) includes an error generated when the intermittent counter 94 is reset at the UW detection position, as shown in FIG. 6, so that this error is absorbed. Γ calculated from equation (17)
The same effect as in the operation example of the second embodiment can be obtained by performing the above-mentioned operation by setting the average of several reception slots to γ.

In the above-described embodiment, an example is shown in which the present invention is applied to a PHS. However, the present invention can be applied to any portable terminal that performs an intermittent receiving operation.

[0080]

As described above, the portable telephone terminal according to the present invention, at the time of intermittent reception, uses the intermittent counter 9 operated by the clock oscillator 15 from the time until the next reception position.
By calculating the count value of No. 4 and generating the power-on timing of the TCXO 14 and the timing for the next reception, the TCXO 14 can be stopped during the non-operation of the intermittent reception to reduce power consumption. Can be. When generating the timing of the reception position from the count value of the intermittent counter 94, the ideal slot position and the intermittent counter 9 are used.
4 is set in the bit counter 91 and the slot counter 92 so that the TCXO 14
Even if the oscillation frequency is not an integral multiple of the oscillation frequency of the clock oscillator 15, the timing of the intermittent reception can be accurately generated, and the intermittent reception can be performed.

The oscillation error of the clock oscillator 15 is represented by U
By detecting from the W detection position and the UW detection expected position, and adding the error to the values set in the bit counter 91 and the slot counter 92, it is assumed that the oscillation frequency of the clock oscillator 15 has shifted due to temperature change and aging. Also, the timing of the intermittent reception position can be adjusted, and intermittent reception can be performed.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a mobile phone terminal according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a timing control unit in FIG. 1;

FIG. 3 is an explanatory diagram showing a frame configuration in a PHS.

FIG. 4 is an explanatory diagram showing a relationship between a bit counter and a slot counter in the first embodiment of the present invention.

FIG. 5 is an explanatory diagram showing an operation example at the time of reception in the first embodiment of the present invention.

FIG. 6 is an explanatory diagram showing an example of a reset operation of a frequency dividing circuit and an intermittent counter based on a UW detection signal in the first embodiment of the present invention.

FIG. 7 is an explanatory diagram showing a configuration example of a gate means in FIG. 2;

FIG. 8 is an explanatory diagram showing a timing example of a TCXO wake-up position and a bit counter wake-up position during intermittent reception according to the first embodiment of the present invention.

FIG. 9 is an explanatory diagram showing an example of a generation timing of a coincidence signal of the first comparing means in the first embodiment of the present invention.

FIG. 10 is an explanatory diagram showing an error between an ideal slot value and a slot value generated by an intermittent counter in the first embodiment of the present invention.

FIG. 11 is an explanatory diagram showing window control at the time of UW detection in the first embodiment of the present invention.

12 is an explanatory diagram illustrating a configuration example of a TCXO control unit in FIG. 1;

FIG. 13 is a flowchart illustrating an operation according to the first exemplary embodiment of the present invention.

FIG. 14 is a block diagram illustrating a configuration of a timing control unit of a mobile phone terminal according to a second embodiment of the present invention.

FIG. 15 is an explanatory diagram showing an outline of an error adjustment operation in the second embodiment of the present invention.

FIG. 16 is a flowchart illustrating an operation according to the second embodiment of the present invention.

FIG. 17 is a block diagram illustrating a configuration of a mobile phone terminal according to the related art.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 antenna 2 antenna switch 3 reception unit 4 transmission unit 5 demodulation unit 5 a timing reproduction circuit 6 modulation unit 7 PLL frequency synthesizer 8 channel codec unit 8 a UW detection circuit 9 timing control unit 10 system control circuit 11 audio interface unit 12 microphone 13 speaker 14 TCXO 15 Clock oscillator 16 TCXO control unit 17 Switch 18 Secondary battery 19 Switch 20 Switch 21 Switch 91 Bit counter 92 Slot counter 93 Divider circuit 94 Intermittent counter 95 TCXO wake-up position setting means 96 First comparison means 97 Bit counter wake-up position Setting means 98 second comparing means 910 bit counter value capturing means

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hiroshi Imageki F-term in the Semiconductor Division, Hitachi, Ltd. 5--20-1, Kamizuhoncho, Kodaira-shi, Tokyo 5K067 AA43 BB03 BB04 BB08 CC06 CC22 DD25 EE02 EE72 GG11 HH22 HH23 KK13

Claims (5)

[Claims] 1. A portable telephone terminal for intermittently receiving a received signal from a base station, the portable telephone terminal reproduces a bit clock of received data from a received signal and outputs the same, and a timing reproducing circuit for outputting a bit clock from the base station; , A UW (unique word) sequence, which is a synchronization bit sequence included in the received data sequence of the received signal of
A UW detection circuit that outputs a W detection signal; a system control circuit that controls the overall operation of the mobile phone terminal; a secondary battery that supplies power to the mobile phone terminal; A first reference oscillator that supplies a reference clock; a switch that supplies and disconnects power of the secondary battery to the first reference oscillator; a power supply control unit that controls connection and release of the switch; A second reference oscillator for supplying a clock for generating a timing necessary for intermittent reception, a timing control unit for establishing synchronization with a base station by the UW detection signal and generating various timings The timing control unit is set to a value set in advance by the UW detection signal, counts up with the bit clock, and is controlled by the system control circuit. A bit counter which can be set to an arbitrary value; an intermittent counter which is initialized by the UW detection signal and counts up by a clock generated by the second reference oscillator; and an arbitrary value by the system control circuit. A first setting unit that can be set, a second setting unit that can be set to an arbitrary value by the system control circuit, a comparison between the intermittent counter, and a setting value of the first setting unit. First comparing means for generating a first coincidence signal when they match, comparing the set values of the intermittent counter and the second setting means, and generating a second coincidence signal when they match. A second comparing unit; and a gate unit capable of supplying and stopping the bit clock supplied from the timing recovery circuit to the bit counter. When the mobile phone terminal performs intermittent reception, after the reception process is completed, the system control circuit outputs a stop signal to the gate means to stop supplying the bit clock to the bit counter. And calculating and setting a count value of the intermittent counter at a power supply time of the first reference oscillator in the first setting unit from a scheduled time of next reception, and the second setting unit Calculating and setting a count value of the intermittent counter at a time at which the bit counter is re-operated; and a time at which the bit counter is re-operated with respect to the scheduled time, and the bit counter is re-operated by the intermittent counter. Calculating a value that minimizes the error in the bit counter, outputting a power stop signal to the power control unit, The control unit releases the switch to stop the first reference oscillator. When the value of the intermittent counter becomes equal to the value set in the first setting unit, the first comparison unit sets the first comparison unit to the first reference oscillator. To the power control unit, the power control unit connects the switch, operates the first reference oscillator, and sets the intermittent counter equal to the value set in the second setting unit. The second comparing means outputs a second coincidence signal to the gate means, and the gate means supplies a bit clock to the bit counter, operates the bit counter, and performs reception. A mobile phone terminal characterized by the following. 2. The mobile phone terminal according to claim 1, wherein, when receiving intermittently, the U.S.P.
If the UW sequence cannot be detected by the W detection circuit, the system control circuit sets the setting values to be set in the first setting means and the second setting means calculated from the next scheduled reception time by 2 respectively. When the next reception is performed, the UW detection circuit sets U
If the W column cannot be detected, the system control circuit triples the setting values set in the first setting means and the second setting means calculated from the next scheduled reception time, A mobile phone terminal configured to set the first setting means and the second setting means. 3. The mobile phone terminal according to claim 2, wherein the timing control unit captures the bit counter value immediately before the bit counter is set to a preset value by the UW detection signal. The system control circuit outputs a stop signal to the gate means to stop the bit clock to the bit counter, after the reception processing is completed, when the apparatus includes a counter value capturing means and performs intermittent reception. The bit counter calculates a difference between a value set by the UW detection signal and a value captured by the bit counter value capturing means, and adds the difference to a value set in the bit counter to calculate the bit. A mobile phone terminal set in a counter. 4. The mobile phone terminal according to claim 3, wherein said system control circuit comprises: a difference between a value set by said UW detection signal in said bit counter and a value captured by said bit counter value capturing means. Calculating the difference after completion of several reception processes, calculating an average difference, and adding the average difference to a value set in the bit counter and setting the difference in the bit counter. Characteristic mobile phone terminal. 5. The mobile phone terminal according to claim 3, wherein, when receiving intermittently, after the receiving process is completed, the U.S.P.
When the UW column cannot be detected by the W detection circuit, the system control circuit adds and doubles the difference or the average value of the difference to a value set in the bit counter, and sets the value in the bit counter. When the next reception is performed, the UW detection circuit
When a W column cannot be detected, the system control circuit adds the difference or the average value of the difference by three to a value set in the bit counter, and sets the value in the bit counter. Mobile phone terminal.