JPH09321687A - Radio communication equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the radio communication equipment in which power consumption is saved and stable intermittent reception synchronization is obtained. SOLUTION: The radio communication equipment conducting frame intermittent reception of a frame signal is provided with a storage section storing a set value WFN of an intermittent frame number, a synchronization control section generating a timing signal RF of a read frame in a frame timing in response to the setting value WFN, a reception section power supply ON control section generating a reception section power supply ON signal S with a time width in response to the set value WFN, and a power supply section feeding power to the reception section and also provided with a synchronization window control section preferably energizing the detection of a synchronizing signal by a synchronization control section to generate a synchronization window signal W with a time width in response to the set value WFN. Furthermore, the synchronization control section is provided with a count section counting number of intermittent frames SFN in response to the set value WFN of the storage section and generates the reception power supply ON signal S and the synchronization window signal W with a time width in response to the count SFN.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wireless communication device, and more particularly to a wireless communication device for intermittently receiving a frame signal. In a wireless communication device such as a digital mobile phone, it is necessary to sufficiently save power consumption because it is battery-powered. For example, when waiting for an incoming call, intermittent power supply to the receiving unit is performed to intermittently supply a frame signal. Receives power to save power consumption.

[0002]

9 to 11 are diagrams (1) to (3) for explaining the conventional technique. FIG. 9 shows the configuration of a conventional digital mobile phone. In the figure, 10 is a radio section, 11 is an antenna, 12 is an antenna common section, 13 is a transmission section using π / 4QPSK, and 14 is the same reception section.
15 is a frequency synthesizer for channel selection, 16
Is a TDMA control unit.

The part of the radio unit 10 excluding the transmitter 13 is called a receiver 10 '. Further, 20 is a telephone function unit, 21 is a codec (CDEC) that performs code conversion between digital / analog signals, 22 is a baseband processing unit that processes baseband signals such as voice, 23 is a speaker (SPK), Reference numeral 24 is a microphone (MIC), 25 is a display unit (DISP) made of liquid crystal, and 26 is a keyboard unit (KBD) including dial keys and the like.

Reference numeral 30 is an intermittent reception control unit, 31 is a synchronization signal detection unit for detecting a predetermined synchronization word signal in the reception data RD, and 32 is a reference counter unit (BCTR) for counting the nominal period of one frame. , 33 is a frame counter (FCTR) that counts the number of frames (frame number) of received frames, 34 is a frame selection unit that selects a frame (read frame) to be received by itself, and 35 is for supplying power to the reception unit 10 ′. Is a timing generation unit for generating a power-on signal S of the receiving unit and a synchronization window signal W for detecting the synchronization word signal.

Further, 41 is a C for performing main control of the mobile phone.
PU (including memory), 42 is a common bus of the CPU 41,
Reference numeral 43 is a peripheral I / O unit (PIO), 44 is a reference clock generation unit (CG) that generates a reference clock signal CK having a constant frequency, 45 is a battery (BT) such as a replaceable dry battery, and 46 is a reception unit 10 '. Power on / off
Power supply switch unit (PC).

At the time of a call using the digital mobile phone,
The radio frequency signal from the antenna 11 is demodulated into reception data RD by the receiving unit 14 and converted into a PCM code signal by the codec 21. Further, this PCM code signal is converted into an analog signal by the baseband processing unit 22, and the speaker 2
3 is output. Further, the audio signal from the microphone 24 is converted into a PCM code signal by the baseband processing unit 22,
It is converted into transmission data TD by the codec 21. Further, this transmission data TD is modulated into a radio frequency signal by the transmission unit 13 and transmitted from the antenna 11.

In this case, the TDMA control unit 16 connects the base station (not shown) with a predetermined time division multiple access (TDM).
According to the method A), the exchange of call control signals and voice data signals is controlled. FIG. 10 shows an example of the format of a received frame according to the TDMA method. In the figure, the base station repeats and continuously transmits 36 frame signals 00 to 35 by using a predetermined downlink channel. The 36 frame signals 00 to 35 are collectively referred to as a superframe. Further, one frame signal is composed of three slot signals 0 to 3, and each slot signal includes a leading preamble signal PA, a data signal following the leading preamble signal PA, a synchronization word signal SW in the middle portion, and a subsequent data signal. Be done.

The sync word signal SW 'of the frame signal 00 is different from the sync word signals SW of the other frame signals 01 to 35, and the frame signal 00 can be identified by this. However, the sync detection signal SW of the sync signal detection unit 31 is generated when any of the sync word signals SW and SW ′ is detected, and the sync detection signal SW ′ is generated only when the sync word signal SW ′ is detected.

Returning to FIG. 9, when the power of the digital mobile phone is turned on, the CPU 41 first transmits the radio frequency signal in the continuous mode (that is, in order to connect to the nearest base station).
It is received by the intermittent reception designation signal RM = 0). In this continuous mode, the receiver power-on signal S of the timing generator 35
Also, the synchronization window signal W is always ON, so that the synchronization signal detection unit 31 can monitor all the received data RD.

On the other hand, the reference counter section 32 repeats the operation of outputting the frame pulse signal FP every time the nominal period K for one frame is counted based on the reference clock signal CK. That is, it is self-propelled at cycle K. Then, when the synchronization signal detector 31 detects the synchronization word signal SW,
The synchronization detection signal SW is output, and the reference counter unit 32 is restarted accordingly. That is, the reference counter unit 32 is synchronized with this synchronization detection, and thereafter outputs the frame pulse signal FP at this phase.

The frame counter 33 counts the number of received frames based on the frame pulse signal FP of the reference counter section 32. However, at this point, the count value of the frame counter 33 is not necessarily the actual received frame number 00 to
It does not match 35. Therefore, the CPU 41 energizes the synchronization enable signal DE that is turned on for at least one superframe period, and when the synchronization word signal SW ′ is detected in this period, the synchronization detection signal SW ′ is output, As a result, the frame counter 33 is restarted. That is, the frame counter 33 is also synchronized with the received frame numbers 00 to 35.

In this way, when the synchronization of the received frame is obtained, the CPU 41 connects to the base station, and the information (standby received frame number,
Standby reception slot number, etc.) is specified. CPU
Based on these, 41 outputs the standby reception frame number setting value FRN and the standby reception slot number setting value SLN to the intermittent reception control unit 30 via the PIO 43. Receiving this, the synchronization signal detecting unit 31 sets the slot number setting SL.
The sync word signal SW of the reception slot corresponding to N is detected, and the sync detection signal SW (SW ') is output. And
After that, in order to save the power consumption of the battery 45, the radio frequency signal is transmitted in the intermittent reception mode (that is, the intermittent reception designation signal R
Receive with M = 1).

In this discontinuous reception mode, the timing generator 36 receives the frame number set value FRN from the CPU 41.
Specific reading frame timing RF = 1 based on (however, information of the number of intermittent superframes is also included in this example)
Only the section of. That is, the frame selection unit 34
Of the frame count number Q of the frame counter 33, the read frame timing signal RF = only at the timing of the frame corresponding to the received frame number setting value FRN.
Outputs 1. Furthermore, the timing generation unit 35 in this case
Turns on the receiver power ON signal S and the synchronization window signal W only in a limited section of the frame of RF = 1. As a result, the receiver 10 'in this case is
Power is supplied only when the N signal S = 1, so that power consumption is saved.

In FIG. 10, if it is assumed that the standby reception frame number FRN = 02 and the standby reception slot number SLN = 1 assigned to the mobile phone, the reception frame 02 and the reception slot 2 of the reception frame 02 are considered from the viewpoint of saving power consumption. It is preferable to set the receiver power ON signal S = 1 and the synchronization window signal W = 1 immediately before. However, the actual received data RD has some variations in signal amplitude and period depending on the radio wave propagation environment and the like, and the frequency of the reference clock signal CK also varies within each device due to variations among devices and temperature. To do.

Therefore, conventionally, in order to absorb these fluctuations and drifts, the next sync word signal SW is detected in the receiver power ON signal S and the sync window signal W of the timing generator 35. With the wax timing t0 as a reference, a fixed time margin (α,
β), (γ, δ) are provided. FIG. 11 is a timing chart of a conventional intermittent reception operation.

FIG. 11A shows a case where intermittent reception is performed for each superframe. The frame counter 33 in this example has a count capacity for three superframes, and the count value Q repeats counting from 00 to 107. In this case, the CPU 41 outputs the reception frame number setting value FRN = 01, 37, 73, and as a result, the read frame timing signal RF = 1 at each timing of the reception frame number = 01, 37, 73.

In this case, since the synchronization detection SW is obtained at a timing t0, the reference counter unit 32 is restarted (synchronized) RST0 at that time, and one superframe period T thereafter elapses. At the timing of t1, the synchronization window signal W that covers the synchronization word signal SW at that time with sufficient accuracy is generated. The same applies to the power-on signal S for the receiver.

Further, since the synchronization detection SW is obtained also at the next timing of t1, restart RST1 of the reference counter section 32 is performed at that time, so that the subsequent one superframe period T is passed at t2. Even at the timing, the synchronization window signal W is generated so as to cover the synchronization word signal SW at that time with sufficient accuracy. Hereinafter, the same applies.

FIG. 11B shows a case where intermittent reception is performed every three superframes. In this case, the CPU 41 outputs the received frame number setting value FRN = 01, and as a result, each received frame number of two superframes = 0
Read frame timing signal RF = 1 at timing 1
Becomes In this case, the reference detection unit 32 is restarted RST0 at that time because the synchronization detection SW is obtained at a certain timing t0, but the frame is not received at the subsequent timings t1 and t2. Therefore, the reference counter unit 32 is not restarted (synchronized), and therefore the reference counter unit 32 is self-propelled by the timeout TO1 and TO2 for each K count. As a result, an error of one superframe period T '(T'> T in this example) is accumulated in this section, and the synchronization window signal W is output from the synchronization word signal SW at the timing t3 of the third superframe. As shown in the figure, it comes off, and standby reception cannot be properly performed. The same applies when T '<T.

Therefore, conventionally, in consideration of the worst case corresponding to the maximum number of intermittent frames, the gate width of the synchronization window signal W (the same applies to the power ON signal S of the receiver) is set to a wide gate width in advance. In addition, this gate width is uniformly applied to all cases of the number of intermittent frames.

[0021]

However, according to the above-mentioned conventional method, even if the number of intermittent superframes is small, the receiving section 10 'is powered on in an extra time, and it is not possible to sufficiently save power consumption. It was Although it is conceivable to increase the frequency stability of the reference clock generation unit 44, this leads to an increase in the cost of communication equipment.

An object of the present invention is to provide a wireless communication device which can further reduce power consumption with a simple structure and can always obtain stable intermittent reception synchronization.

[0023]

The above-mentioned problem is solved, for example, by referring to FIG.
It is solved by the configuration of. That is, the wireless communication device of the present invention (1) is a wireless communication device that performs frame intermittent reception of a frame signal, and synchronizes with a holding unit that holds the setting value WFN of the intermittent frame number and a reception frame signal of the receiving unit in advance. At the same time, a synchronization control unit that generates a timing signal RF of the reading frame at a frame timing corresponding to the setting value WFN of the holding unit, and a receiving unit having a time width corresponding to the setting value WFN of the holding unit in the urging section of the reading frame. The receiver power source ON control unit that generates the power source ON signal S and the power source unit that supplies power to the receiver unit in the energized section of the receiver power source ON signal S are provided.

In the present invention (1), the holding unit holds the setting value WFN of the number of intermittent frames, the synchronization control unit synchronizes with the reception frame signal of the receiving unit in advance, and the setting value WFN of the holding unit is set. The read frame timing signal RF is generated at the frame timing. Then, the receiver power-on control unit sets the set value WF of the intermittent frame number of the holding unit.
A receiver power ON signal S having a time width corresponding to N is generated.

For example, in the case of WFN = 0, the minimum time width, and in the case of WFN = 1, the next wide time width in consideration of the fluctuation of the radio wave propagation environment and the variation and drift of the reference clock period in this intermittent one frame section. , Again WFN
In the case of = 2, the receiver power ON signal S having a wider time width in consideration of the fluctuations in the intermittent two-frame section is generated. Therefore, in each of the above cases, the power supply unit supplies power to the reception unit within an optimal time width without waste, and power consumption can be further saved.

Preferably, in the present invention (2), a synchronization window control unit for activating the detection of the synchronization signal in the synchronization control unit is provided, and the synchronization window control unit is a holding unit in the activation section of the reading frame. A synchronization window signal W having a time width corresponding to the set value WFN of is generated. For example, in the same manner as above, when WFN = 0, the minimum time width, WFN
When = 1, the synchronization window signal W having the next wider time width is generated. When WFN = 2, the synchronization window signal W having a wider time width is generated. Therefore, stable intermittent reception synchronization can always be obtained regardless of variations in the reception state.

Further, in the present invention (3), preferably, the synchronization control unit includes a counting unit that counts the number of intermittent frames according to the set value WFN of the holding unit, and the receiving unit power ON control unit is the counting unit. The receiver power-on signal S having a time width corresponding to the count number SFN is generated. For example,
When WFN = 0 (0 intermittent frames), this counting unit repeats counting SFN = 0, 0, 0, .... As a result, the receiving unit power ON signal S having the minimum time width can be obtained in each SFN = 0 read frame for each frame.
When WFN = 1 (1 intermittent frame), SFN =
The count of 0, 1, 0, 1, ... Is repeated. As a result, the receiving unit power ON signal S having the next wider time width is obtained in each SFN = 1 read frame every other frame. When WFN = 2 (2 intermittent frames), 0, 1, 2,
The count of 0, 1, 2, ... Is repeated. This gives 2
The reception unit power ON signal S having a wider time width can be obtained for each reading frame of SFN = 2 every frame. Therefore, the same function and effect as those of the present invention (1) can be obtained.

By the way, in this type of wireless communication device, a call origination request may occur during such intermittent (standby) reception. In such a case, it is desired to synchronize with the immediately following frame and operate in continuous mode thereafter. Even in such a case, according to the present invention (3), since the count unit holds the history of the immediately preceding intermittent reception sequence as described above, this is used to optimize the power supply of the reception unit for the immediately following frame. The ON signal S can be generated.

For example, if a call origination request is generated at an intermediate SFN = 1 during intermittent reception with WFN = 2, the content of this SFN = 1 is one intermittent frame so far. Is present (history).
Therefore, in order to synchronize with the immediately following frame, the receiver power ON signal S having an optimum time width is generated in consideration of the information of SFN = 1. The same applies to other cases of SFN = 0,2.

Therefore, according to the present invention (3), even when a transmission request is made during intermittent reception, the power supply ON control of the receiving section can be performed with an optimum time width, and power consumption can be further saved. Further preferably, in the present invention (4), the synchronization control unit is
The synchronization window control unit includes a counting unit that counts the number of intermittent frames according to the set value WFN of the holding unit, and the synchronization window control unit generates the synchronization window signal W having a time width corresponding to the count number SFN of the counting unit.

Therefore, according to the present invention (4), while having the same effect as the above-mentioned present invention (2), the synchronous window control with the optimum time width can be performed even for the transmission request during the intermittent reception. , More reliable synchronization detection can be performed. Further, preferably, in the present invention (5), in the above-mentioned present inventions (1) to (4), the number of intermittent frames is a number in units of superframes, which is a set of a predetermined number of frames.

For example, the set value WFM of the intermittent frame number used in each control and the number of intermittent frames counted by the counting unit are numbers in units of one superframe which is a set of a predetermined number of frames 00 to 35. is there. Therefore, the present inventions (1) to (4) can be applied to discontinuous reception in units of superframes. Moreover, control is easy by managing the number of intermittent frames for each superframe.

Further, in the present invention (6), preferably, the receiver power ON control unit minimizes the set value of the time width of the receiver power ON signal by detecting the synchronization signal in the read frame. By the way, in this type of wireless communication device, when an incoming request is detected in a certain read frame, it is desired to synchronize with the immediately following frame and operate in the continuous mode thereafter. Even in such a case, according to the present invention (6), since the receiver power ON control unit minimizes the set value of the time width of the receiver power ON signal by detecting the synchronization signal in the read frame, simple control is possible. By this, optimum power-on control of the receiving section can be performed for the immediately following frame, and power consumption can be further saved.

Further, in the present invention (7), preferably, the synchronization window control unit minimizes the time width of the synchronization window signal by detecting the synchronization signal in the read frame. Therefore, the optimum synchronization window control can be performed for the immediately following frame by simple control, and more reliable synchronization detection can be performed.

Further, in the present invention (8), preferably, the synchronization control unit normally counts the nominal period K for one frame and initializes the count phase by detecting the synchronization signal. And a correction unit that holds the difference between the count value when the synchronization signal is detected and the nominal period K, and at a predetermined timing when the detection of the synchronization signal cannot be obtained in the read frame at a certain time. The count phase of the reference counter section is returned to the original value by the difference held by the correction means.

In the present invention (8), even if the count phase of the reference counter portion deviates from the normal state due to the synchronization detection of a certain read frame due to changes in the radio wave propagation environment, etc., the synchronization signal is detected in the subsequent read frame. If not,
The count phase of the reference counter section is returned to normal. Therefore, stable and highly reliable synchronization detection can be performed.

Further, preferably, in the present invention (9), in the above-mentioned present invention (1) or (2), a transmitting / receiving unit of the TDMA system, and a telephone function unit for connecting to the transmitting / receiving unit to realize a call function, And a power supply unit driven by a battery. Therefore, it is possible to further reduce the power consumption and prevent the erroneous synchronization of the portable wireless telephone of this kind which is generally popular today.

[0038]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings. Note that the same reference numerals indicate the same or corresponding parts throughout the drawings. FIG. 2 is a diagram showing a configuration of a digital mobile phone according to an embodiment. In the figure, 50 is an intermittent reception control unit, 31 is a synchronization signal detection unit, and 52 is a reference for counting a nominal frame period K based on a reference clock signal CK. Counter part (BCT
R) and 33 are frame counters (FCTR) for counting the number of frames (number) based on the frame pulse signal FP,
56 is a super frame counter (SFC) which counts the number of super frames based on the super frame pulse signal SFP.
TR), 54 is a frame selection unit that outputs the read frame timing signal RF = 1 at the timing of the read frame to be received by itself, and 55 is the power supply of the receiving unit of the receiving unit 10 '.
It is a timing generation unit that generates the signal S and the synchronization window signal W.

The same parts as those in FIG. 9 are designated by the same reference numerals and the description thereof will be omitted. The super frame counter 56 displays P
Number of intermittent superframe settings from IO43 WFN = 0
According to the information of n, the gate signal G is generated so as to be ON for one superframe every n superframes from 0 superframes. For example, whenever WFN = 0, every other superframe when WFN = 1, and W
When FN = 2, G = 1 every two superframes.

The frame selection section 54 outputs PIO to the section of the gate signal G = 1 of the output of the super frame counter 56.
The corresponding frame of the received frame number set value FRN = 0 to 35 from 43 is selected and the read frame timing signal RF = 1 for one frame is output. FIG. 3 is a diagram showing the configuration of the timing generation unit according to the embodiment. In the figure, 55 is a timing generation unit, 61 is a timing decoder (TDEC), 62 is a pulse conversion unit, and FF00-0n ,.
FF10 to 1n are RS-type flip-flop groups, 63 is a dual output port selector (SEL),
64 is a D type register (REG), and 65 to 67 are O
It is an R gate circuit (O).

The timing decoder 61 receives each desired window set / reset timing signal WS0-WSn, WR0 based on the count output Q of the reference counter section 52.
~ WRn and receiver power ON set / reset timing signals SS0-SSn, SR0-SRn. In the pulse converter 62, the FF00 forms the synchronization window signal WT0 which is set at WS0 and reset at WR0. This signal WT0 is PIO4
This corresponds to the synchronization window signal W in the case where the number of intermittent superframe settings WFN = 0 from 3 (received for each superframe). Thereafter, the process proceeds in the same manner, and FF0n becomes WSn.
Form a sync window signal WTn which is set at and reset at WRn. This signal WTn is
This corresponds to the synchronization window signal W in the case of the intermittent superframe set number WFN = n (reception every n superframes).

In this case, each of the above synchronization window signals W
T0 to WTn have a relationship of WT0 <WT1 <... <WTn, and these time widths each require the minimum synchronization word signal SW at the time of each read frame according to the value of the intermittent superframe set number WFN. It is set to the optimum time width that enables accurate detection with a limited window width.

In the same manner, the FF10 has a receiver power supply O which is set at SS0 and reset at SR0.
Form the N signal ST0. This signal ST0 corresponds to the receiver power ON signal S when the intermittent superframe setting number WFN = 0. Thereafter, the same process is performed, and the FF 1n is
A receiver power ON signal STn is set which is set at SSn and reset at SRn. This signal ST
n corresponds to the receiver power ON signal S when the intermittent superframe setting number WFN = n.

In this case, the power-on signal S
T0 to STn are in the relationship of ST0 <ST1 <... <STn, and these time widths are the minimum required for the receiving unit 10 'at the time of each reading frame according to the value of the intermittent superframe set number WFN. ON / OFF with limited time width
It is set to the optimal time width for control. The selector 63 is energized when the intermittent reception designation signal RM = 0 (continuous reception mode) and when the reception frame timing signal RF = 1, and the output signal Q = of the register 64 at that time point is Q =
According to 0 to n, the corresponding one of the synchronization window signals WT0 to WTn and the reception unit power ON signals ST0 to STn is selectively output.

In this case, the input data D of the register 64
Is the number of intermittent superframe settings from PIO43 WFN =
0 to n, and when the intermittent reception designation signal RM = 1 (intermittent reception mode), each read frame timing signal RF =
At the rising edge of 1, the information of WFN = i is registered in advance in the register 6
4 latched. As a result, in the RF = 1 section, the synchronization window signal WTi and the reception unit power ON signal STi of each optimum time width corresponding to the intermittent superframe number WFN = i are output, and the detection of the synchronization word signal SW is thereby performed. Done.

By the way, there is a case where a call origination request is generated in the middle of the reception of such an intermittent superframe, and in such a case, the reception mode is immediately changed to continuous (RM = 0) and synchronized with the immediately following next frame. I want to take In this case, the intermittent reception designation signal RM = 0 during the intermittent reception.
When set to (continuous reception mode), the falling edge causes
Information of the set number WFN = i at that time is set in the register 64. This is because the WFN = i is set with a maximum margin in this example because it is not known how many superframes the intermittent reception has advanced up to this point. As a result, in the next frame, the synchronization word signal SW is detected with a sufficient time width.

When this synchronization detection is obtained, the synchronization signal detector 31 generates the synchronization detection signal SW, which resets the output Q of the register 64 to "0".
In each successive frame thereafter, the synchronization window signal WT0 and the receiver power ON signal ST0 having the minimum time width are provided, thus saving the power consumption. In the case of continuous reception (RM = 0), the OR gate circuits 66, 6
7, the synchronization window signal W and the receiver power ON signal ST may be constantly turned on.

Further, since no reception synchronization is obtained when the power of the apparatus is turned on, a control signal R provided separately is used.
By setting M ′ = 0, the synchronization window signal W and the receiver power ON signal ST may be always ON. FIG.
6 is an operation timing chart of intermittent reception control according to the embodiment. FIG. 4A shows a case where discontinuous reception is performed for each superframe.

In this case, the CPU 41 sets the reception frame number setting value FRN = 01, the intermittent superframe setting number WF.
As a result, N = 0 is output, and as a result, the read frame timing signal RF = 1 at the timing of each received frame number = 01 for each superframe. In this case, the timing generation unit 55 provides the synchronization window signal WT0 and the reception unit power ON signal ST0 of each minimum time width for each superframe, thus saving power consumption.

The superframe numbers 0, 1, 2 in the figure
~ N are those which are synchronized and generated and managed in the own device,
It does not mean that the superframe number is assigned to the received signal itself. FIG. 4B shows a case where intermittent reception is performed every three superframes. CPU4 in this case
1 outputs the received frame number set value FRN = 01, and the intermittent superframe set number WFN = 2, and as a result, the read frame timing signal RF = 1 at the timing of each received frame number = 01, which is a 2-superframe interval. Becomes

In this case, after the synchronization detection at a certain timing t0, the synchronization detection is not performed at each of the subsequent timings t1 and t2, so that by the third superframe, a cyclic error of three superframes (in this example). Then T '>
T) is accumulated, but since a wide synchronization window signal WT2 and a receiver power ON signal ST2 corresponding to the intermittent superframe set number WFN = 2 are provided at the third superframe, the synchronization word signal SW of Can detect properly. Moreover, since the time width of the receiver power ON signal ST2 is set to the minimum required in this case, the power consumption can be further saved.

FIG. 5 is a diagram showing the structure of a timing generator according to another embodiment. In FIG. 5, 55 is a timing generator according to another embodiment, and 68 is a selector (SE).
L) and 69 are differentiating circuits (DIF), and 70 is an OR gate circuit (O). The other parts are shown in FIG.
The same as If necessary, the OR gate circuit 6 of FIG.
6. Add the logic part of 67.

By the way, in the example of FIG. 3 described above, when a call origination request or the like is generated during the intermittent superframe reception,
Immediately after switching to continuous mode (RM = 0) and not knowing how many superframes the intermittent reception has advanced by that point, the maximum margin in that case is taken into consideration and the number of intermittent superframes set in register 64 is set. WFN = i
The set was done.

On the other hand, in this embodiment, the synchronization window signal WTj and the receiver power ON signal STj having the optimum time width are provided according to how many superframes the intermittent reception has advanced by that point. It is possible. Hereinafter, a specific description will be given. When the intermittent reception designation signal RM = 1 (intermittent reception), the selector 68 selects and outputs the side of the intermittent superframe setting number WFN = i. However, when the intermittent reception designation signal RM = 0 (continuous reception), the superframe count number SFN = j (≦ i) side of the superframe counter 56 at that time is selectively output.

The differentiating circuit 69 detects the falling edge of RM = 0 and generates a pulse signal after a lapse of a predetermined time. As a result, the information of the superframe count number SFN = j at that time is set in the register 64, and the superframe count number SFN from the timing generation unit 55 is set.
= J, the synchronization window signal WTj and the receiver power ON signal STj having the optimum time width are provided.

Then, in this received frame, the synchronization detection SW
Is obtained, the output Q of the register 64 is reset to "0", and the synchronous window signal WT0 and the receiver power ON signal ST0 having the minimum time width are provided in each successive frame thereafter, thus reducing the power consumption. Savings and prevention of false synchronization are achieved. FIG. 6 is an operation timing chart of discontinuous reception control according to another embodiment.
(A) shows a case where intermittent reception is performed every three superframes. This operation is similar to that of FIG.

FIG. 6B shows a case where the mode is switched to the continuous reception mode during the intermittent reception of every 3 superframes. For example, at the timing of ta, the intermittent reception designation signal RM =
When it becomes 0 (continuous reception), the information of the super frame count number SFN = 1 at that time is set in the register 64, and the timing generation unit 55 sets the optimum frame according to the SFN = 1 in the section of the subsequent frame number = 35. Time window synchronization window signal WT1 and receiver power ON signal ST1
Is provided.

When the synchronization detection SW is obtained in this received frame = 35, the output Q of the register 64 is reset to "0", and each successive frame 00 to 3 thereafter.
In FIG. 5, the synchronization window signal WT0 and the receiver power ON signal ST0 of each minimum time width are provided, thus saving power consumption and preventing false synchronization. In the case of such continuous reception, the synchronization window signal WT0 ′ and the reception unit power ON signal ST0 having a narrower time width than the synchronization window signal WT0 and the reception unit power ON signal ST0.
You may make it use '.

Further, in this case, the super frame counter 56 sets the intermittent super frame setting number W from the PIO 43.
Depending on FN = 0 to n, for example, if WFN = 0, then S
When FN = 0, 0, ..., WFN = 1, SFN = 0,
, 1, WFN = 2, SFN = 0,1,
The superframe count number is output in each of the modes 2, 0, 1, 2, .... Then, in this case, the selector 68 of FIG. 5 may be deleted, and the information of the superframe count number SFN = j may be always set in the register 64. Even with this, the same action and effect can be obtained.

In this case, the superframe count number SFN is not in the counting phase as shown in FIG. 6, and when the received frame number set value FRN = 01, for example, the superframe count number SFN is changed to the timing of the frame count number FCTR = 01. With a different count phase. By doing so, the superframe count number SFN always represents a correct elapsed time from the previous synchronization detection to the current synchronization detection.

FIG. 7 is a diagram showing the configuration of the reference counter section according to the embodiment. In the figure, 52 is the reference counter section.
71 is an up counter (CTR), 72 is a subtractor (SU)
B), 73 is a latch circuit (LTH), 74 is a decoder (DEC), 75 is a JK type, 76 is an RS type, 7
7 is each D-type flip-flop (FF), 78, 7
9 is an AND gate circuit (A), and 80 is an OR gate circuit (O).

It should be noted that the reference counter section 52 of FIG.
Although it may be equivalent to the conventional reference counter unit 32 of FIG. 7, the reference counter unit 52 of FIG. 7 is preferably used. Counter 7
1 is clock-loaded with the data of the data input terminal D when the load control terminal L = 1, and otherwise counts up with the reference clock signal CK. The signal from the load control terminal L is supplied to the counter 7 during intermittent reception.
It becomes “1” when the frame pulse FP is generated by the timeout of 1 and when the synchronization detection SW is obtained during intermittent reception. The former is the case where the counter 71 is self-running at the count cycle K, and the latter is the case where the counter 71 is restarted to "0" (phase-synchronized with the synchronization detection SW) by the synchronization detection SW.

However, if the synchronization detection SW cannot be obtained at the timing of a certain synchronization window signal W = 1, FF7
7 is still set, so that the outputs S and M of the subtractor 72 are energized, and the output of the subtractor 72 is preloaded into the counter 71 when the frame pulse FP at that time is generated. . That is, the count phase is corrected.

The subtractor 72 has output terminals of sine S and magnitude M, and when B-A ≧ 0, S =
It outputs 0 (positive) and its positive difference M. Also, B-A <
When 0, S = 1 (negative) and its negative difference M (however, the complement of K) are output. The counter 71 counts up as Q = 0, 1, 2, ... When D = 0 is loaded, for example, and outputs a carry signal CA when Q = K. Also, for example, when D = 10 is loaded, Q = 10, 11, 1
Counted up to 2, ..., carry signal CA when Q = K
Is output. That is, the count phase advances by 10 counts. Further, for example, when D = -10 (that is, K-10) is loaded, Q = K-10, K-9, K-8, ... K-
Counts up as 1, 0, 1, 2, ... And outputs a carry signal CA when Q = K. That is, the count phase is delayed by 10 counts.

When D = -10 is loaded, carry signal CA is generated twice at the count value Q = K-1 → 0 and at the subsequent Q = K. Therefore, in order to ignore the carry signal CA for the first time, the FF 75 is loaded at the load timing of sine S = 1 (negative).
Is set so that the first carry signal CA does not become the frame pulse signal FP. This FF7
5 is reset at the first fall of the carry signal CA, so that the second carry signal CA becomes the frame pulse signal FP.

The latch 73 latches the count output Q of the counter 71 at that time at the timing when the synchronization detection SW is obtained. By the way, since the timing at which the synchronization detection SW is obtained is within the time width of the synchronization window signal W, the count output Q of the counter 71 is (K-
γ) to K and 0 to δ.

In this case, the count output Q is (K-γ)
When the synchronization detection SW is obtained in the section of ~ K, the subtracter 7
The input B of 2 is in the range of (K-γ) to K, so the above subtraction results in B-A = [(K-γ) to K] -K, which gives the actual phase difference (phase lead). An appropriate negative number to represent-γ ~
It becomes 0. On the other hand, when the synchronization detection SW is obtained in the section where the count output Q is 0 to δ, the input B of the subtractor 72 is 0 to 0.
is in the range δ, so the above subtraction is B−A = (0
δ) −K, which cannot be an appropriate positive number representing the actual phase difference (phase delay).

Therefore, if the FF 76 is set in advance by the generation of the frame pulse signal FP and the synchronization detection SW is obtained in the interval of the count output Q of 0 to δ by this, the higher bits than K Bit signal MSB =
1 is latched in the latch circuit 73. For example, K = 1023
Then, the bit signal MSB = 1024. As a result, when the synchronization detection SW is obtained in the section where the count output Q is 0 to δ, the input B of the subtractor 72 is (MSB +
0) to (MSB + δ), so the above subtraction results in B−A = [(MSB + 0) to (MSB + δ)] − K, which is a suitable positive number representing the actual phase difference (phase lag). 1 to (δ + 1).

In this case, the decoder 74 uses the counter 7
An appropriate intermediate value of the count output Q of 1 is decoded, and when the count output Q reaches this intermediate value, the reset signal MP is output and the FF 76 is reset. In addition,
In this example, the latch circuit 73 latches the count output Q of the counter 71 at the time when the reception synchronization SW is obtained, but the correction value of the output of the subtractor 72 may be latched.

FIG. 8 is an operation timing chart of the reference counter section according to the embodiment. FIG. 8A shows the synchronization detection S at a certain timing t0 due to a change in the transmission state or the like.
It shows a case where W has advanced in phase. in this case,
The reference counter unit 52 is restarted earlier by the synchronization detection SW at t0, which advances the phase of synchronization detection by φ1. Since the synchronization detection is not performed in the following two superframe sections, the phase of the synchronization detection is advanced by φ1. That is, since the device itself cannot know the fluctuation of the transmission state, the synchronization detection is advanced assuming that the current detection phase is correct. Then, in the third superframe, the synchronization window signal W (the same applies to the reception unit power ON signal S) is opened earlier by the phase φ1.

However, in this example, since the previous synchronization detection SW was due to a change in the transmission state, synchronization detection cannot be obtained at the next timing of t1. Therefore, this t
At the timing of 1, the reference counter unit 52 times out, and the frame counter FP causes the reference counter unit 52 to time out.
The detected phase of is corrected (delayed) by φ1 previously stored. As a result, the reference counter unit 52 returns to the correct detection phase, and the synchronization detection SW is obtained at the next timing of t2.

At the timing of t1, there is a possibility that the synchronization detection SW can be obtained at that time by correcting the detection phase. However, in this example, since the sync word signal SW happens to be delayed at this point due to a change in the transmission state or the like, sync detection cannot be obtained at the timing of t1. FIG. 8B shows a case where the synchronization detection SW has a phase delay at a certain timing t0 due to a change in the transmission state or the like.

In this case, the reference counter unit 52 is restarted after the synchronization detection at t0, and the phase of the synchronization detection is delayed by φ2. Since the synchronization detection is not performed in the subsequent two superframe sections, the phase of the synchronization detection remains delayed by φ2. Then, in the third superframe, the synchronization window signal W (receiver power ON is delayed by phase φ2).
Signal S is the same).

However, in this example, since the previous synchronization detection SW was due to a change in the transmission state or the like, synchronization detection cannot be obtained at the next timing of t1. Therefore, this t
At the timing of 1, the reference counter unit 52 times out, and the frame counter FP causes the reference counter unit 52 to time out.
The detected phase of is corrected (advanced) by φ2 previously stored. As a result, the reference counter unit 52 returns to the correct detection phase, and the synchronization detection SW is obtained at the next timing of t2.

In the above embodiment, the example of application to the TDMA receiving system used in the current mobile communication system is described, but it goes without saying that the present invention can be applied to various other TDMA receiving systems. There is also no. Further, in the above embodiment, an example of discontinuous reception control in which the number of superframes is used as a unit has been described, but it is clear that the present invention is also applicable to discontinuous reception control in which the number of normal frames is used as a unit.

Although a plurality of preferred embodiments of the present invention have been described above, it will be understood that various changes can be made to the configuration of each part, control, and combinations thereof without departing from the spirit of the present invention. There is no limit.

[0077]

As described above, according to the present invention, the power consumption can be further saved with a simple structure, and stable intermittent reception synchronization can always be obtained. It greatly contributes to improving the quality.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a diagram showing a configuration of a digital mobile phone according to an embodiment.

FIG. 3 is a diagram showing a configuration of a timing generation unit according to the embodiment.

FIG. 4 is an operation timing chart of discontinuous reception control according to the embodiment.

FIG. 5 is a diagram showing a configuration of a timing generation unit according to another embodiment.

FIG. 6 is an operation timing chart of intermittent reception control according to another embodiment.

FIG. 7 is a diagram showing a configuration of a reference counter unit according to the embodiment.

FIG. 8 is an operation timing chart of the reference counter unit according to the embodiment.

FIG. 9 is a diagram (1) illustrating a conventional technique.

FIG. 10 is a diagram (2) illustrating a conventional technique.

FIG. 11 is a diagram (3) illustrating a conventional technique;

[Explanation of symbols]

 10 wireless unit 20 telephone function unit 33 frame counter unit 45 battery 46 switch unit 50 intermittent reception control unit 52 reference counter unit 54 frame selection unit 55 timing generation unit 56 super frame counter unit FRN received frame number set value RF read frame timing signal RM Intermittent reception designation signal S Receiver power ON signal SFN Super frame number SLN Receive slot number setting value SW, SW 'Sync detection signal W Sync window signal WFN Intermittent super frame setting number

Claims (9)

[Claims] 1. A wireless communication device for intermittently receiving a frame signal, comprising: a holding unit that holds a setting value of the number of intermittent frames; and a synchronization with the reception frame signal of the receiving unit in advance, and a setting value of the holding unit. A synchronization control unit that generates a timing signal of the reading frame at a corresponding frame timing, and a receiving unit power ON control unit that generates a receiving unit power ON signal of a time width corresponding to the setting value of the holding unit in the activating section of the reading frame. And a power supply unit that supplies power to the receiving unit in the energized section of the receiving unit power ON signal. 2. A synchronization window control section for energizing the detection of the synchronization signal in the synchronization control section, wherein the synchronization window control section has a time width corresponding to a set value of the holding section in the energizing section of the reading frame. The wireless communication device according to claim 1, wherein the wireless communication device generates a synchronization window signal. 3. The synchronization control unit includes a counting unit that counts the number of intermittent frames according to the set value of the holding unit, and the receiving unit power ON control unit has a receiving unit having a time width corresponding to the count number of the counting unit. The wireless communication device according to claim 1, wherein the wireless communication device generates a power ON signal. 4. The synchronization control unit includes a counting unit that counts the number of intermittent frames according to a setting value of the holding unit, and the synchronization window control unit outputs a synchronization window signal having a time width according to the count number of the counting unit. The wireless communication device according to claim 2, wherein the wireless communication device is generated. 5. The wireless communication device according to claim 1, wherein the number of intermittent frames is a number in units of superframes, which is a set of a predetermined number of frames. 6. The receiver power-on control unit minimizes the set value of the time width of the receiver power-on signal by detecting the synchronization signal in the read frame.
Wireless communication device. 7. The wireless communication device according to claim 2, wherein the synchronization window control unit minimizes the time width of the synchronization window signal by detecting the synchronization signal in the read frame. 8. The synchronization control unit normally counts a nominal period for one frame, and a reference counter unit that initializes its count phase by detecting a synchronization signal, and a count value when the synchronization signal is detected. And a correction means for holding the difference between the nominal cycle and the nominal cycle, and when the detection of the synchronization signal cannot be obtained in the read frame at a certain point, the correction means holds the count phase of the reference counter section at a predetermined timing The wireless communication device according to claim 1, wherein only the difference is restored. 9. The wireless communication device according to claim 1, further comprising: a transmitter / receiver unit using the TDMA system, a telephone function unit connected to the transmitter / receiver unit to realize a call function, and a battery-powered power supply unit. .