JP2963560B2 - Decoder circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a decoder circuit for reproducing received data which is used in a radio paging receiver in data communication.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing an example of a part of a radio paging receiver including a conventional decoder circuit. In the figure, 20 is a decoder circuit, 21 is a data generator, 22
Is a bit synchronization circuit, 23 is a synchronization collation circuit, 24 is a frequency divider, 25 is a CPU (processor unit), 26 is a wireless receiver, 27 is an oscillator that supplies a reference clock to the synchronization circuit,
Reference numeral 28 denotes a clock oscillation unit of the CPU 25. The decoder circuit 20 of the conventional paging receiver includes a radio receiver 26.
A reference clock is converted to a bit synchronization circuit 2 based on the baseband input signal detected in step 2 and the reference clock from the frequency divider 24.
The synchronous clock corrected by performing the phase correction in 2 is output, and the synchronous clock and the reproduced data in bit units are output from the input signal data generation unit 21. The data is collated with the stored collation pattern to output bit-wise synchronization information to the CPU 25. The CPU 25 confirms the accuracy of the synchronization check based on the reproduction data and the synchronization information input in units of bits, and then performs a predetermined decoding process to give a reproduction output to a display unit or an alarm device.

[0003]

However, such a conventional receiving circuit has the following disadvantages. The CPU 25 waits for bit-wise synchronization information from the decoder circuit 20 by a built-in counter in accordance with a clock supplied from the oscillation unit 28. When the synchronization information is input, the CPU 25 receives playback data from that point in time according to the timing. Is started, and when synchronization information is not input, reception of reproduction data is started at an earlier timing. This CPU
In the operation 25, as described above, since the decoding process is performed in units of bits, it is necessary to increase the speed of the clock supplied from the oscillation unit 28, and therefore, there is a problem that the current consumption is significantly increased. This is a practical drawback related to the battery life of the portable wireless device that causes the microprocessor to control the operation. SUMMARY OF THE INVENTION An object of the present invention is to provide a decoder circuit which solves the above-described problems and reduces the current consumption of a microprocessor.

[0004]

According to the present invention, a decoder is provided with a bit synchronization circuit having a function of determining whether or not to correct the phase of a reference clock based on synchronization information in a decoder circuit. This eliminates the need for performing the data processing described above, and the system clock speed of the CPU is reduced to 1/3 of the conventional speed. That is, the decoder circuit of the present invention includes: a bit synchronization circuit A that corrects the phase of a reference clock by using a synchronization signal included in an input signal detected by a wireless reception unit and outputs a synchronization clock A; A data generation unit A that reproduces and outputs the reproduction data A from the input signal in accordance with the synchronization clock A, and compares the reproduction data A of the data generation unit A with the built-in pattern, determines the synchronization, and synchronizes when the patterns match. A synchronization matching circuit that outputs information, a correction storage circuit in which correction information of the phase of the bit synchronization circuit A is stored in advance, and the reference based on synchronization information from the synchronization matching circuit and correction information from the correction storage circuit. A bit synchronization circuit B that corrects the phase of the clock and outputs a synchronization clock B; A data generation unit B for reproducing the reproduction data B, the reproduction data A and the reproduction data B, the synchronization clock A and the synchronization clock B are input, and the reproduction data A and the synchronization clock A or the reproduction data B A selection circuit for selecting and outputting any one of the synchronous clocks B; and a serial-parallel conversion circuit for serial-to-parallel conversion of serial reproduction data of the selection circuit into parallel reproduction data and outputting the parallel reproduction data. .

[0005]

FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, 1 is a data generation unit A, 2 is a bit synchronization circuit A, 3 is a data generation unit B, 4 is a bit synchronization circuit B,
5 is a synchronous collation circuit, 6 is a correction storage circuit, 7 is a selection circuit,
8 is an oscillator, 9 is a serial-parallel converter, 10 is a divider, 11
Denotes an oscillating unit, 12 denotes a CPU (processor unit), 13 denotes a wireless receiving unit, and 14 denotes a decoder circuit showing the configuration of the present invention.

[0006] The data generation unit A (1)
The reproduced data A is output in accordance with the received data input from the bit synchronization circuit A and the synchronization clock A from the bit synchronization circuit A. The bit synchronization circuit A (2) uses the received data, the reference clock from the frequency divider 10, the synchronization information from the synchronization matching circuit 5, and the correction information from the correction storage circuit 6 to set the reference clock to the reference of the base station on the transmission side. It operates so as to match the clock and outputs the synchronous clock A. The data generator B (3) outputs the reproduction data B in accordance with the received data and the synchronization clock B from the bit synchronization circuit B (4). Bit synchronization circuit B (4)
Is calculated based on the reference clock from the frequency divider 10, the synchronization information from the synchronization matching circuit 5, and the phase correction amount generated by the bit synchronization circuit A (2) stored in the correction storage circuit 6.
The phase of the reference clock from the frequency divider 10 is corrected. The synchronization verification circuit 5 collates the reproduced data A from the data generation unit A (1) with the data pattern stored in the synchronization verification circuit 5, and outputs a determination result as synchronization information when they match. The correction storage circuit 6 counts the correction amount of the phase correction information generated by the bit synchronization circuit A (2), and stores the corrected storage amount in the bit synchronization circuit A (2) and the bit synchronization circuit B.
Output to (4). The selecting circuit 7 outputs the data of the data generator A (1) and the data generator B (3) and the bit synchronization circuit A (2) based on the synchronization information from the synchronization matching circuit 5.
And the output of the bit synchronization circuit B (4) is selected. When the synchronization information is present, the outputs of the data generation unit A (1) and the bit synchronization circuit A (2) are selected as outputs. If there is no synchronization information, the data generation unit B (3)
And the output of the bit synchronization circuit B (4). The serial / parallel conversion circuit 9 is a data generation unit A selected by the selection circuit 7.
(1) or converting the reproduced data of the data generation unit B (3) from serial data to parallel data. Divider 1
The reference numeral 0 indicates that the clock oscillated by the crystal oscillator or the like of the oscillating unit 8 is frequency-divided and supplied as a reference clock to each unit of the decoder circuit 14.

That is, the bit synchronization circuit A (2) functions to sample the reference clock with the received data, correct the phase of the reference clock based on the relative difference, and output the synchronization clock A. However, when the synchronization information cannot be obtained from the synchronization matching circuit 5, the state is returned to the state before the correction by applying the reverse correction of the phase correction amount stored in the correction storage circuit 6, and the synchronization clock A is output. . Data generator A
(1) works so as to output the reproduction data A by sampling the reception data by the synchronization clock A from the bit synchronization circuit A (2). The bit synchronization circuit B (4) does not correct the phase of the reference clock until the synchronization information from the synchronization matching circuit 5 is obtained, and corrects the amount of the phase stored in the correction storage circuit 6 when the synchronization information is obtained. To perform the phase correction and output the synchronous clock B. Data generator B
(3) works so as to output the reproduction data B by sampling the reception data by the synchronization clock B from the bit synchronization circuit B (4). That is, the bit synchronizing circuits A and B and the data generators A and B use the synchronizing information from the synchronizing circuit 5 to determine whether the bit synchronizing circuit B has the synchronizing information, ie, correct the phase correction. , And the data generator B synchronizes the output timing with the data generator A. If there is no synchronization information from the synchronization check circuit 5, the bit synchronization circuit A
The data generator A works so as to match the timing of the data generator B. FIG. 2 is a time chart for explaining the operation of the present invention. (A) shows the case where the synchronization information cannot be obtained for the received signal, and (B) shows the case where the synchronization information has been obtained. First, the phase of the synchronous clock A is corrected by the synchronous signal of the received signal. Then synchronization verification signal is collated by the synchronization matching circuit 5, if not met, i.e., no information is available synchronization (a) phase synchronizing clock B of the synchronous clock A at the time of P ₁ in the case of
And the selection circuit 7 selectively outputs the reproduced data B and the synchronous clock B. On the other hand, aligned with the phase of the synchronous clock A synchronous clock B at time P ₂ in the case of synchronization information from the synchronization correlation circuit 5 were obtained (b), the selection circuit 7 is reproduction data A and the synchronous clock A is selectively output. As described above, according to the present invention, by providing two systems of synchronization circuits, data (sound signal and message signal) immediately following the synchronization verification signal can be reproduced, and the CPU 12 can perform a low-speed clock operation. It is assumed that. According to the above operation, the decoder circuit 14 of the present invention performs all the processing of taking in the reproduction data in bit units, so that the CPU 12 does not need to take in data in 1 bit units. What is necessary is just to perform control of taking in data in word units.

[0008]

According to the present invention, since the received data output to the CPU is changed from 1 bit unit to n bit unit, the data control of the CPU may be performed by the clock of the n bit, and the speed of the system clock of the CPU may be reduced. Can be reduced to 1/3 to 1 / m of the conventional one, which has an extremely large effect on reduction of current consumption.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a time chart illustrating the operation of the present invention.

FIG. 3 is a block diagram of a conventional circuit.

[Explanation of symbols]

 Reference Signs List 1 data generation unit A 2 bit synchronization circuit A 3 data generation unit B 4 bit synchronization circuit B 5 synchronization verification circuit 6 correction storage circuit 7 selection circuit 8 oscillation unit 9 serial / parallel conversion circuit 10 frequency division unit 11 oscillation unit 12 CPU 13 wireless Reception unit 14 Decoder circuit 20 Decoder circuit 21 Data generation unit 22 Bit synchronization circuit 23 Synchronization verification circuit 24 Frequency divider 25 CPU 26 Wireless reception unit 27 Oscillator 28 Oscillator

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04L 7/02 H03M 9/00

Claims (1)

(57) [Claims] 1. A bit synchronization circuit A for correcting a phase of a reference clock by a synchronization signal included in an input signal detected by a radio reception unit and outputting a synchronization clock A, and a synchronization clock A from the bit synchronization circuit A And a data generator A for reproducing and outputting the reproduction data A from the input signal, collating the reproduction data A of the data generator A with the built-in pattern, determining the synchronization, and outputting the synchronization information when they match. A synchronization verification circuit; a correction storage circuit in which correction information of the phase of the bit synchronization circuit A is stored in advance; and a synchronization information from the synchronization verification circuit and a correction information from the correction storage circuit. A bit synchronization circuit B for correcting and outputting a synchronization clock B; and reproducing the reproduction data B from the input signal by the synchronization clock B from the bit synchronization circuit B. A data generation unit B, which receives the reproduction data A and the reproduction data B, the synchronization clock A and the synchronization clock B, and outputs the reproduction data A and the synchronization clock A or the reproduction data B and the synchronization clock B A decoder circuit comprising: a selection circuit for selecting and outputting one of them; and a serial-parallel conversion circuit for serial-to-parallel conversion of serial reproduction data of the selection circuit into parallel reproduction data and outputting the parallel reproduction data.