JPH07312549A - Method and device for correcting clock signal - Google Patents

Abstract

PURPOSE:To reduce the power consumption and to correct a clock signal properly by providing a basic clock source generating a reception reproduced clock signal and the correction device for frequency fluctuation of the basic clock signal in the device and selecting through changeover a periodic correction mode operated at a prescribed period or a temperature change tracing correction mode implementing the operation in response to a temperature change. CONSTITUTION:When a control section 4A consisting of a microcomputer or the like rises at application of power, a built-in timer is started to switch on/off of a control signal at a prescribed period interval. Thus, an error signal is obtained at a prescribed period interval and the signal is corrected based on a clock signal of a temperature compensation crystal oscillator TCXO10. When the control section 4A detects expiration of time, the information of a built-in register A is transferred to a register B, a control signal is cleared and the temperature information fetched from a temperature sensor 50 is set to the register A. When the noncoincidence in contents of the registers A, B is detected, the control signal is set. When a temperature drift takes place as a result, a comparator section 40 is operated and the temperature change tracing correction mode is set.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock correction method and its apparatus applied to mobile communication terminals and the like.

[0002]

2. Description of the Related Art Conventionally, as a basic clock source for generating a basic clock of a recovered clock, a mobile communication terminal has a TCXO (T
emerasure Compensated Cr
The ystal oscillator (temperature-compensated crystal oscillator) was used. However, this TCXO
Had the problem of being expensive. Therefore, a mobile communication terminal has been provided in which the TCXO used in the wireless system is used to correct the frequency fluctuation of the basic clock of the reproduced clock. A mobile communication terminal having this configuration is shown in FIG.

The terminal of FIG. 5 is provided with two antennas 1-1 and 1-2 due to the space diversity system. RF captured from antennas 1-1 and 1-2
The (radio frequency) signal is down-converted to an IF (intermediate frequency) signal in the transmission / reception unit 2 and further sent to the orthogonal demodulators 11 and 12 to be demodulated into an I channel signal and a Q channel baseband signal, respectively. It reaches the A / D converters 14 and 15 and is digitized and sent to the signal processing unit 3. The signals arriving at the A / D converters 14 and 15 are subjected to delay detection in a detection (delay) circuit 31, reach a P / S (parallel / serial) conversion circuit 32, are converted into serial data, and are sent to the frame disassembly unit 34. To be The frame decomposition unit 34 includes a UW (unique word) detection unit 36.
Based on the detection result of 1, the frame is disassembled for each frame and sent to the control unit 4 and the error correction unit 35. Error correction unit 3
In 5, the error correction is performed based on the error correction bits included in one frame, and the result is sent to the control unit 4 and the CODEC (coder / decoder) 5. Here, the frame disassembling unit 34 and the error correcting unit 35 have a function of switching the transmission path according to the attribute of the frame. It is the control information frame that is sent to the control unit 4 side and the voice information that is sent to the CODEC 5 side. The original information frame such as. UW detector 3
The detection output of 6 is also sent to the frame counter 37. The frame counter 37 counts the number of frames each time one frame arrives, sends the result to the transmission / reception unit 2, and sends / receives a predetermined number of frames as a unit. There is. COD
The signal arriving at EC5 is decoded (decoded) to D /
D / A conversion of the A / A / D converter 6 is performed to form an analog signal, which is sent from the driver 17 to the speaker 21 and output as sound. On the other hand, the audio signal input from the microphone 22 is amplified by the receiver 18 and the D / A.
It reaches the A / D converter 6, receives A / D conversion, and then C
The signal is sent to the ODEC 5, coded (encoded), sent to the transmission signal processing unit 39, subjected to processing reverse to that of the received signal to be a signal of a predetermined frame, and sent to the D / A converter 16. . The D / A converter 16 performs conversion into an analog signal, sends the analog signal to the quadrature modulator 13 of the transmission / reception unit 2 to undergo quadrature modulation, and then up-converts it to a radio frequency, and then antenna 1 (1-1). Or it is transmitted from 1-2).

By the way, the output of the detection circuit 31 is TANK.
The TANK circuit 33 is also provided to the circuit 33, and is composed of a bandpass filter that extracts a clock component of a predetermined frequency from the received data. The clock extracted by the TANK circuit 33 is given to a DPLL (digital phase lock loop) 38. DPLL38 is T
The ANK circuit 33 operates so that the phase of the received clock relating to the output of the ANK circuit 33 and the clock of the basic clock source 7 are synchronized, and the reproduced clock is sent to each section. However, the accuracy of the oscillation frequency of the basic clock source 7 is not so high and correction is required. Therefore, the TC used in the transceiver unit 2
The DPLL 38 uses the output of the XO 10 for correction.

[0005]

However, according to the above clock correction method, power is consumed for the operation of the circuit for the constant correction, and the terminal consumes a large amount of power.
In particular, in the case of a portable device, the capacity of the battery to be mounted must be increased, which causes a problem that the terminal itself becomes large. On the other hand, it is possible to intermittently perform the operation for correction, but if this is done, the oscillation frequency cannot be stabilized at an appropriate oscillation frequency at the beginning of startup. Further, when the intermittent time interval is shortened, power is consumed and the terminal consumes a large amount of power as described above. Further, the basic clock generated by the basic clock source 7 basically causes frequency fluctuations due to temperature drift as shown in FIG. 6 except when the power is turned on, and this should be solved. There was found.

The present invention has been made in view of the problems of the clock recovery method and its device used in the mobile communication device as described above, and the background of the problem solution. (EN) Provided is a clock correction method and device capable of appropriately correcting a clock while suppressing the clock.

[0007]

Therefore, in the clock correction method according to the invention described in claim 1, there is provided a basic clock source for generating a basic clock of the received reproduction clock, and means for correcting the frequency fluctuation of the basic clock. And a temperature change tracking correction mode in which the means is operated in response to a temperature change, and a clock correction is executed by switching between these two modes. It is characterized by

Further, in the clock correction method according to the invention of claim 2, in the invention of claim 1, the cyclic correction mode is executed for a predetermined time from the start-up, and after this predetermined time has elapsed. Is characterized by shifting to a temperature change tracking correction mode and executing clock correction.

The clock correction method according to the third aspect of the present invention comprises a basic clock source for generating the basic clock of the received reproduction clock, and means for correcting the frequency fluctuation of the basic clock, and continuously. A continuous correction mode for operating the means, and a temperature change tracking correction mode for operating the means in response to a temperature change,
It is characterized in that the correction of the clock is executed by switching between these two modes.

Further, in the clock correction method according to the invention of claim 4, in the invention of claim 3, the continuous correction mode is executed for a predetermined time from the start-up, and after the predetermined time has elapsed, The temperature change tracking correction mode is entered to perform clock correction.

Further, in the clock correction device according to the present invention, a basic clock source for generating a basic clock of the reception / reproduction clock, a clock oscillation source having a higher accuracy than the basic clock source, and the reception / reproduction clock. And a PLL for synchronizing the phase of the basic clock generated by the basic clock source, and error information relating to the frequency fluctuation of the basic clock generated by the basic clock source, based on the clock of the clock oscillation source, and the error It is characterized by comprising a correction means for correcting the frequency of the reproduction clock in the PLL according to the information, and an operation / non-operation control means for switching the operation / non-operation of the correction means according to the temperature fluctuation.

Further, in the clock correction device according to the invention described in claim 6, in the invention described in claim 5, the operation / non-operation control means performs switching control so that the operation is performed at a predetermined cycle at a predetermined time. However, in other cases, the switching control is performed so that the operation is performed when the temperature variation is detected.

[0013]

According to the clock correction method of the first aspect of the present invention, there are provided a cyclic correction mode in which the means is operated in a predetermined cycle and a temperature change tracking correction mode in which the means is operated in response to a temperature change. The two modes are appropriately switched to perform the clock correction.

According to the clock correction method of the second aspect of the present invention, the cyclic correction mode is executed for a predetermined time from the start-up, and after the predetermined time has elapsed, the mode changes to the temperature change tracking correction mode. Then, the clock is corrected, the correction is repeatedly performed when the frequency is unstable at the initial stage of activation, and the convergence is achieved. Further, thereafter, the fluctuation due to the temperature drift is appropriately corrected.

According to the clock correction method of the third aspect of the present invention, there are two modes: a continuous correction mode in which the means is operated continuously and a temperature change tracking correction mode in which the means is operated in response to temperature changes. The modes are appropriately switched and clock correction is executed.

According to the clock correction method of the fourth aspect of the present invention, the continuous correction mode is executed for a predetermined time from the start-up, and after the predetermined time has elapsed, the temperature change tracking correction mode is entered. The clock is corrected by the clock, and the correction is continuously performed when the frequency is unstable at the initial stage of startup to quickly converge, and thereafter, the fluctuation due to the temperature drift is appropriately corrected.

According to the clock correction device of the fifth aspect of the invention, the operation / non-operation of the correction means for correcting the frequency of the reproduction clock in the PLL is switched according to the temperature fluctuation, and the fluctuation due to the temperature drift is appropriate. Is corrected to.

According to the clock correction device of the sixth aspect of the present invention, the correction means for correcting the frequency of the reproduction clock in the PLL operates at a predetermined cycle at a predetermined time and changes in temperature at other times. When the frequency is unstable, such as in the initial stage of starting, the correction is repeatedly performed to converge, and at other times, fluctuations due to temperature drift are appropriately corrected.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A clock correction method and apparatus according to an embodiment of the present invention will be described below with reference to the accompanying drawings. In addition,
In the description of each drawing, the same constituents will be denoted by the same reference symbols and redundant description will be omitted. FIG. 1 shows a clock correction device adopting the clock correction method of the present invention. This clock recovery device is applied to the mobile communication terminal shown in FIG. 5, and as shown in the drawing, the TCXO 10, the basic clock source 7, and the TAN of the mobile communication terminal shown in FIG.
It is configured using the K circuit 33. In addition to the above, the control unit 4
A (corresponding to the control unit 4 in FIG. 5) and DPLL38A (see FIG. 5).
Corresponding to the DPLL 38) and the comparison unit 40.

A temperature sensor 50 is connected to the control unit 4A, and the control unit 4A fetches temperature information and controls ON / OFF of a control signal (CONT) to the comparison unit 40. Further, the control section 40 controls the control signal (CO
NT) is ON, the error information relating to the frequency fluctuation of the basic clock is created by the clock of the TCXO 10 and the clock of the basic clock source 7, and the DPLL3
Give to 8A.

FIG. 2 shows a detailed structure of the comparison section 40. The comparison unit 40 includes a reference pulse generation unit 41,
It is composed of a counter 42, a constant output section 43, and a subtractor 44. The reference pulse generator 41 counts the clock output from the TCXO 5 when the control signal (CONT) given from the controller 4A is ON, and generates a reference pulse having a pulse width corresponding to the monitoring period for correction. To do. In this embodiment, when the clock frequency of the TCXO 10 is 16.2 MHz and the clock frequency of the basic clock source 7 is 21.504 MHz, the reference pulse generator 41 sets the output to H level from "0" to "324000". . As will be described later, the control signal (CONT) is turned on at intervals of 720 mS or when a temperature change is detected. Then, the reference pulse generator 41 turns off the control signal (CONT).
It is reset at, and when it is turned on, counting is started, and its output is from "0" to "32" for the clock of TCXO10.
When the 4000 "pulse arrives, its output is set to the H level. As a result, a pulse having a pulse width of 20 mS is sent to the counter 42. Counter 42 is 2
This is a 0-bit counter, which is enabled by being supplied with a pulse having a pulse width of 20 mS from the reference pulse generator 41, and counts the clock of the basic clock source 7 to 20
The bit output is sent to the subtractor 44. Therefore, if the clock frequency of the basic clock source 7 does not change, 2
An output of 0 mS × 21.504 MHz = 430080 is generated. The same “430080” as the above is output from the constant output unit 43 to the negative terminal of the subtractor 44. Therefore, when the clock frequency of the basic clock source 7 fluctuates and the output of the counter 42 goes up and down from "430080", the difference is output as an error signal, and the DPLL
38A. In this embodiment, the output of the subtractor 44 uses 7 bits from the MSB in order to prevent the correction operation from occurring due to a slight frequency change.

FIG. 3 shows the detailed structure of the DPLL 38A. The basic configuration of this DPLL38A is that the clock of 21.504 MHz output from the basic clock source 7 is divided by 2 by the frequency divider 61, and the clock inserting / extracting unit 66 inserts / extracts pulses to obtain 5.376 MHz, and further divides it. The frequency is reduced to 256 kHz by the frequency divider 67, and the frequency is reduced to 21 KHz, which is then guided to the phase comparator 64.
The 21 KHz component signal output from the zero crossing detector 63 is zero-crossed, pulsed, sent to the phase comparator 64 for phase comparison, and an output corresponding to the phase difference is obtained to detect the counter / rising edge. The output of the counter / rising edge detection circuit 65 is applied to the circuit 65, and the insertion / extraction of pulses in the clock insertion / extraction unit 66 is controlled. In the counter / rising edge detection circuit 65, a cycle for extracting a pulse from the output of the frequency divider 61 is set by loop gain setting, and the U related to the output of the phase comparator 64 is set.
A P or DWON signal changes this cycle. The counter / rising edge detection circuit 65 detects the rising edge of the clock of the frequency divider 51, and at this timing and at each of the changed cycles, a pulse is inserted into or removed from the clock insertion / extraction unit 66. Pulse is applied to obtain the recovered clock.

In the present embodiment, the counter / rising edge detection circuit 65 is further provided with a signal for changing the cycle for extracting a pulse from the output of the frequency divider 61 by the output of the PWM conversion section 62. In other words, the PWM converter converts the pulse width of the error signal output from the comparator 40 into a pulse of H or L level corresponding to the error and outputs the pulse. When it is at the H level, it acts as it is to reduce the pulse dropout cycle, and when it is at the L level, it acts as a signal inverted by the inverter 69 and raises the pulse dropout cycle.

FIG. 4 shows a flowchart for the control section 4A to control ON / OFF of the control signal (CONT). When the control unit 4A including a microcomputer or the like having a program corresponding to this flowchart is started by turning on the power,
For example, a built-in timer that times up at 60S is started (S71), and the control signal (CONT) is switched ON / OFF at predetermined intervals (720mS) in order to execute the correction performed at predetermined intervals (720mS) (S).
72). As a result, the error signal described above has a predetermined period (72
The correction is performed at intervals of 0 mS) and is corrected based on the clock of the TCXO 10. Then, the control unit 4A detects the presence or absence of a time-up (S73), and if the time-up is not detected, the periodic correction mode for executing the correction performed at a predetermined cycle (720 mS) is further continued, and when the time-up is detected, The information in the built-in register A is transferred to the register B (S74), the control signal (CONT) is turned off (S75), and the temperature information fetched from the temperature sensor 50 is set in the register A (S76). Then, it is detected whether the contents of the register A and the register B do not match (S
77), if they match, the operation from step S74 is repeated again. On the other hand, when it is detected in step S77 that the contents of the register A and the register B do not match, the control signal (CONT) is turned ON (S7).
8) Then, the operation from step S74 is repeated again. As a result, when temperature drift occurs, as described above,
The comparison unit 40 operates and an error signal is output. In other words, the temperature change correction mode is executed.

According to the above, when the power is turned on, a stable frequency clock is appropriately set, but after that, the comparison unit 40 does not operate, power consumption is reduced, and a temperature drift occurs. The comparison unit 40 operates again and the correction operation is performed.

In the above embodiments, the correction is periodically performed at the initial stage of power-on, but in other embodiments, the continuous correction mode is substantially performed. That is, for example, the operation of turning on the control signal for 720 mS, setting an instantaneous off period, and turning on the control signal for 720 mS is continued for a predetermined time. According to this other embodiment, a quick stable operation is guaranteed at the initial stage of power-on.

Further, the temperature sensor 50 of this embodiment may be provided for the present invention, but in the mobile communication terminal, the electric field strength detection unit for detecting that the service is out of the service area has an error due to temperature drift. A temperature sensor is provided to prevent detection. Therefore, it is efficient to share this temperature sensor.

Further, in this embodiment, the correction is made when the temperature is different, but in the other embodiments, the correction is made when the change in the temperature is equal to or more than a predetermined value. According to the other embodiment, the power consumption can be further reduced without performing the correction operation with a slight temperature change.

[0029]

As described above, according to the clock correction method according to the invention of claim 1 of the present application, the means for operating the means in response to a temperature change and the periodic correction mode for operating the means in a predetermined cycle. Since the two modes of the temperature change tracking correction mode to be performed are appropriately switched and the clock correction is executed, the quick correction when necessary and the fluctuation due to the temperature drift in the steady state can be accurately executed.

According to the clock correction method of the second aspect of the present invention, the correction is repeatedly performed when the frequency is unstable at the initial stage of the start-up, and the convergence is achieved. To reduce the power consumption.

Further, according to the clock correction method of the invention described in claim 3 of the present application, since there is a continuous correction mode for continuously operating the means, a quick correction when necessary is guaranteed.

Further, according to the clock correction method of the invention described in claim 4 of the present application, the continuous correction mode is executed for a predetermined time from the start-up, and after the predetermined time has elapsed, the temperature change tracking correction is performed. After shifting to the mode, the clock is corrected, and when the frequency is unstable at the initial stage of startup, it is continuously corrected and quickly converged.
The power consumption is reduced by appropriately compensating for fluctuations due to temperature drift.

According to the clock correction device of the fifth aspect of the present invention, the operation / non-operation of the correction means for correcting the frequency of the reproduction clock in the PLL is switched according to the temperature change, and the temperature is changed. Fluctuations due to drift are appropriately corrected to reduce power consumption.

According to the clock correction device of the invention of claim 6, the correction operation is performed at a predetermined cycle at a predetermined time, and at other times when a temperature change is detected. It is repeatedly corrected when the frequency is unstable, such as at the beginning of startup, to achieve convergence.
At other times, the fluctuation due to the temperature drift is appropriately corrected. Thus, appropriate clock correction is performed while reducing power consumption.

[Brief description of drawings]

FIG. 1 is a block diagram of a clock correction device according to an embodiment of the present invention.

FIG. 2 is a detailed block diagram of a main part of the clock correction device according to the embodiment of the present invention.

FIG. 3 is a detailed block diagram of essential parts of the clock correction device according to the embodiment of the present invention.

FIG. 4 is a flowchart for explaining the operation of the clock correction device according to the embodiment of the present invention.

FIG. 5 is a block diagram of a mobile communication terminal equipped with a conventional clock correction device.

FIG. 6 is a diagram showing frequency fluctuations due to temperature drift of a basic clock.

[Explanation of symbols]

10 TCXO 7 Basic clock 4A Control unit 33 TAN
K circuit 38A DPLL 40 Comparison unit 41 Reference pulse generation unit 42 Counter 43 Constant output unit 44 Subtractor 50 Temperature sensor 61 Frequency divider 62 PWM conversion unit 63 Zero cross detection unit 64 Phase comparator 65 Counter / rising edge detection circuit 66 Clock insertion / extraction Circuit 67 frequency divider

Claims (6)

[Claims] 1. A basic clock source for generating a basic clock of a reception / reproduction clock, and means for correcting a frequency fluctuation of the basic clock, a periodic correction mode for operating the means at a predetermined cycle, and a temperature change. And a temperature change tracking correction mode for operating the means in accordance with the above, and the clock correction is performed by switching between these two modes. 2. The periodic correction mode is executed for a predetermined time from the start-up, and after the predetermined time has elapsed, the mode is shifted to the temperature change tracking correction mode and the clock correction is executed. The clock correction method according to claim 1. 3. A basic clock source for generating a basic clock of a reception / reproduction clock, and means for correcting the frequency fluctuation of the basic clock, and a continuous correction mode for continuously operating the means, and a temperature change. And a temperature change tracking correction mode for operating the means in accordance therewith, and the clock correction is performed by switching between these two modes. 4. The continuous correction mode is executed for a predetermined time from the start-up, and after the predetermined time has elapsed, the temperature change tracking correction mode is entered and the clock correction is executed. Item 3. The clock correction method according to Item 3. 5. A basic clock source for generating a basic clock of a reception / reproduction clock, a clock oscillation source having a higher precision than this basic clock source, a phase of the reception / reproduction clock and a basic clock generated by the basic clock source. The PLL to be synchronized and error information relating to the frequency fluctuation of the basic clock generated by the basic clock source are created based on the clock of the clock oscillation source, and the frequency of the reproduction clock in the PLL is corrected according to this error information. A clock correction device comprising: a correction means; and an operation / non-operation control means for switching the operation / non-operation of the correction means according to a temperature change. 6. The operation / non-operation control means performs switching control so as to perform an operation at a predetermined cycle at a predetermined time, and performs switching control so as to perform an operation when a change in temperature is detected at other times. The clock correction device according to claim 5, wherein the clock correction device is a clock correction device.