JP3325434B2 - Reference clock supply device and mobile terminal device using the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reference clock supply device for generating a reference clock used in a terminal device such as a portable telephone terminal device, and more particularly, to a reference clock supply device for reducing power consumption and its use. Mobile terminal device.

[0002]

2. Description of the Related Art In a digital car telephone system, a "digital car telephone system standard" is used.
As described in (RCR STD27 Radio System Development Center), TDM / TDM
The A method is adopted.

According to this standard, a portable telephone terminal device performs a predetermined process when power is turned on, receives a predetermined control channel called a perch channel, and decodes the received data with respect to the received data of this channel. Establish bit synchronization. Thereafter, frame synchronization or superframe synchronization is established by periodically detecting a synchronization word included in a slot to be received. When these synchronizations are established, the mobile phone terminal receives the broadcast channel (BCCH) and shifts to the channel specified by the BCCH.

FIG. 17 shows the structure of a control channel.

[0005] The location of the paging channel (PCH) to be received by the own station is determined based on the control information broadcast on the BCCH of the control channel of the transfer destination, and an intermittent reception operation is performed.
During this intermittent reception operation, a so-called standby state is set.
In this state, the reception operation only needs to perform reception of about 6.7 msec once in a relatively long cycle of several hundred msec. Transmission from the mobile phone terminal device in the standby state includes location registration, call processing, and the like. Is not performed regularly.

However, at the time of intermittent reception, P
In order to determine the position of the CH, frame synchronization and superframe synchronization must be maintained.

During communication, as shown in FIG.
Reception R, idle I, transmission T, and antenna switching diversity level measurement period LM are repeatedly operated.

FIG. 19 is a block diagram showing an example of the configuration of a portable telephone terminal device.

In FIG. 1, a received signal received by an antenna 101 is divided into a demultiplexer 102, a receiver 103, and a demodulator 1.
06, output from the speaker via the channel codec unit 109 and the audio codec unit 110 as audio, and the audio signal input from the microphone 113 is output from the audio codec 11
0, output from the antenna 101 via the channel codec unit 109, the modulation unit 107, the transmission unit 104, and the duplexer 102. Control signals required for communication are exchanged between the channel codec unit 109 and the microprocessor 111.

Here, a reference clock required for performing the entire operation is supplied from a highly stable voltage-controlled temperature-compensated crystal oscillator (VCTCXO) 108.

[0011] In the portable telephone terminal device, the receiving unit 103, the transmitting unit 104, and the demodulating unit 10 are desirably used for a long time.
6. The modulation unit 107 and the like frequently perform power control so as to operate only for a minimum time when necessary for communication, and the microprocessor 111 that performs overall control performs intermittent reception during standby. At the time, only the key operation process is operated, and other processes are shifted to a standby mode to reduce power consumption.

However, VCTC which supplies a reference clock
The XO 108 has been operating at all times to maintain frame synchronization and to return the microprocessor 111 from the standby mode by key operation processing.

[0013]

As described above,
Each part of the mobile phone terminal device performs power control frequently to reduce power consumption, whereas the VCTCXO that generates the reference clock has always been operating. In particular, at the time of intermittent reception, the VCTCXO operates only for maintaining frame synchronization and for key operation processing even though other operations are stopped, which is not enough to reduce power consumption. Did not.

It is an object of the present invention to maintain frame synchronization using an oscillator with very low power consumption and to use a VCTCXO.
Another object of the present invention is to provide a reference clock supply device which is stopped at the time of intermittent reception during standby except when necessary to reduce power consumption and a mobile terminal device using the same.

[0015]

According to a first aspect of the present invention, there is provided a control unit for controlling and calculating the entire operation, and a first unit for generating a clock having a first frequency.
Clock generating means, a second clock generating means for generating a clock of a second frequency, a power supply means for stopping or starting power supply to or operation of the first clock generating means, A gate means for closing or opening the output clock of the clock generation means and outputting it as a reference clock; and, when activated, closing the gate means after a preset time and generating the first clock by the power supply means. Closing time adjusting means for stopping power supply or operation to the means; and opening time for opening the gate means after the output clock of the second clock generating means has been counted by a preset value when activated. Adjusting means;
A frequency dividing means for dividing the reference clock having passed through the gate means to a desired frequency; and i (where i is an integer) stages, and an output clock of the frequency dividing means is inputted and j (where,
(j is an integer that satisfies i ≧ j)) A symbol clock is output from the stage, a binary counter capable of reading and writing the count value by the control unit, a stop means for stopping or canceling the operation of the binary counter, Counting means for counting the number of output clocks of the clock generating means, start value setting means for setting the count value of the counting means at the time when the stop processing of the symbol clock is started, and the start value A value obtained by adding a value obtained by subtracting a count value preset in the open time adjusting means from the number of output clocks of the second clock generating means until the return time of the symbol clock to a set value of the setting means, As the return value, the return value setting means set by the control unit, and the set value of the start value setting means and the count value of the counting means are compared, and it is detected that they match. The stopping means stops the operation of the binary counter and activates the closing time adjusting means, and compares the return value of the return value setting means with the count value of the counting means. When it is detected that they match, the stopping means releases the stop of the operation of the binary counter, and the power supply means stops the first counter.
And a second comparing means for starting power supply or operation to the clock generating means and activating the open time adjusting means.

According to a second aspect of the present invention, there is provided the control section, the first clock generating section, the second clock generating section, the power supply section, the gate section, and the closing time adjusting section. Means, the open time adjusting means, the frequency dividing means, the binary counter, the stopping means,
The counting means, a latch means for holding the value of the counting means in response to a control signal from the control section, and the second clock generation until the symbol clock returns to the value held in the latch means. A return value setting unit that sets a value obtained by adding a value obtained by subtracting a count value preset in the open time adjustment unit from the number of output clocks of the unit as a return value, the return value setting unit being set by the control unit; Comparing means.

Further, the third aspect of the present invention relates to the first and second aspects.
In the invention of the above, external input detecting means for detecting an external input, starting means for outputting a start signal when an input is detected by the external input detecting means, the starting means and the second comparing means And an OR gate which receives the output signal of the above and outputs it to the open time adjusting means and the power supply means.

Further, the fourth aspect of the present invention is directed to the first to third aspects.
And a changeover switch for selecting one of a reference clock output from said gate means and an output clock of said second clock generation means and supplying the selected clock to said control section.

Further, the fifth invention is characterized in that the control unit comprises:
The first clock generation means, the second clock generation means, the power supply means, and, when activated, the first power generation means causes the power supply means to execute the first clock generation after a preset time.
Stopping time adjusting means for stopping power supply or operation of the clock generating means, the frequency dividing means, the binary counter, and the stopping means.
Releasing time adjusting means for counting the output clock of the clock generating means by a preset value, and then canceling the stop of the binary counter by the stopping means; the counting means; the start value setting means; Value setting means, comparing the set value of the start value setting means and the count value of the counting means, when it is detected that they match,
The stop means stops the operation of the binary counter and activates the stop time adjusting means. The first comparison means compares the return value of the return value setting means with the count value of the counting means. When it detects a match,
A second comparing means for starting the power supply or operation to the first clock generating means by the power supply means and activating the release time adjusting means.

Further, in a sixth aspect of the present invention, the control section includes:
The first clock generation unit, the second clock generation unit, the power supply unit, the stop time adjustment unit, the frequency division unit, the binary counter, the stop unit, and the release time Adjusting means, the counting means,
The apparatus includes the latch unit, the return value setting unit, and the comparison unit.

According to a seventh aspect of the present invention, in the fifth and sixth aspects, the output signals of the external input detecting means, the activating means, the activating means, the external input detecting means and the comparing means are inputted. And an OR gate for outputting to the power supply means.

In an eighth aspect based on the fifth to seventh aspects, one of the reference clock output from the first clock generation means and the output clock of the second clock generation means is provided. And a changeover switch for selecting and supplying the control unit to the control unit.

[0023]

In the first aspect of the invention, when the first comparison means detects the coincidence, the control unit stops the phase difference between the output clock of the second clock generation means and the symbol clock. The symbol after the time obtained by adding the time when the second comparing means detects the coincidence and the time when the counting by the open time adjusting means ends is detected from the value of the j-th stage or less of the binary counter. The phase of the clock is calculated, and this is set in the binary counter. When the time set in advance by the closing time adjusting means has elapsed, the gate means is closed, and the first clock is supplied by the power supply means. When the power supply or operation to the generation means is stopped, the supply of the reference clock to the binary counter is stopped, and the second comparison means detects the above-mentioned coincidence, the power supply is stopped. When the power supply means starts the power supply or operation of the first clock generation means and counts the output clock of the second clock generation means by the open time adjustment means by a preset value in advance, the gate means is opened. The reference clock is supplied to the binary counter, and the output of the symbol clock starts at the phase set in the binary counter.

According to the second aspect of the present invention, when a control signal is transmitted from the control unit, the closing time adjusting means is activated, and the stopping means sets an edge of an output clock of the second clock generating means. The binary counter is stopped, and the phase difference between the output clock of the second clock generating means and the symbol clock is detected from the value of the j-th stage or lower of the stopped binary counter, and the second comparing means detects the phase difference. , And the phase of the symbol clock after a time obtained by adding the time when the counting by the opening time adjusting means is completed is calculated, and the calculated phase is set in the binary counter. At the end, the gate means is closed, the power supply means stops supplying power to the first clock generation means, and the binary When the supply of the reference clock to the counter is stopped and the above-mentioned coincidence is detected by the second comparison means, the power supply to the first clock generation means is started by the power supply means, When the counting by the opening time adjusting means is completed, the gate means is opened, the reference clock is supplied to the binary counter, and the output of the symbol clock is started at the phase set in the binary counter.

In the third aspect of the present invention, when the power supply means stops the first clock generation means and the external input detection section detects an external input, the activation means sets the activation means. The opening time adjusting means is started, and power supply or operation to the first clock generating means is started by the power supply means. When the counting of the opening time adjusting means is completed, the gate means is opened and the gate means is opened. Supply of the reference clock to the binary counter resumes,
Thereafter, the control unit resets a value obtained by adding a value set in advance to the open time adjustment unit to a value set in the return value setting unit as a return value in the return value setting unit, When the second comparing means detects that the return value matches the count value of the counting means, the stopping means releases the stoppage of the operation of the binary counter, the binary counter starts operating, and the symbol The clock returns.

According to the fourth aspect of the present invention, when the gate means is closed, the changeover switch is set to the second state.
And when the gate means is open, the changeover switch selects the reference clock from the gate means and supplies it to the control unit.

[0027] In the fifth aspect of the present invention, when the first comparison means detects the coincidence, the control unit:
The time when the phase difference between the output clock of the second clock generation means and the symbol clock is detected from the value of the jth stage or less of the stopped binary counter and the coincidence is detected by the second comparison means. Calculate the phase of the symbol clock after a time obtained by adding the time when the counting of the release time adjusting means is completed, and set the phase of the symbol clock in the binary counter, and set the time preset in the stop time adjusting means. After the elapse, the first power supply means causes the first
When the power supply or operation to the clock generation means is stopped, the supply of the reference clock to the binary counter is stopped, and the coincidence is detected by the second comparison means, the power supply means is stopped. As a result, the power supply or operation to the first clock generating means is started, and the second clock is incremented by the count value preset in the release time adjusting means.
When the output clock of the clock generation means is counted, the stop of the binary counter is stopped by the stop means, and the output of the symbol clock is started at the phase set in the binary counter.

In the sixth aspect of the present invention, when a control signal is sent from the control section, the stop time adjusting means is activated, and the stop means controls the edge of the output clock of the second clock generating means. And the phase difference between the output clock of the second clock generation means and the symbol clock is detected from the value of the j-th stage or lower of the stopped binary counter, and the second comparison means Calculate the phase of the symbol clock after a time obtained by adding the time for detecting the coincidence and the time when the counting of the release time adjusting means is completed, set the calculated phase in the binary counter, and set the phase in the stop time adjusting means in advance. After the lapse of time, the power supply means stops the power supply or operation to the first clock generation means, and When the supply of the reference clock to the counter is stopped and the coincidence is detected by the second comparison means, the power supply means starts power supply or operation to the first clock generation means. When the output clock of the second clock generation means is counted by a value set in advance by the release time adjustment means, the stop of the binary counter is canceled by the stop means, and the phase is set at the phase set in the binary counter. The output of the symbol clock starts.

In the seventh aspect of the present invention, when the power supply means stops the first clock generation means and the external input detection section detects an input from outside, the start-up means activates the start-up means. The power is supplied to the first clock generation means by the power supply means or the operation is started by the power supply means, and the supply of the reference clock to the binary counter is resumed. When the above-mentioned coincidence is detected, the release time adjusting means is activated. When the release time adjusting means finishes counting the output clock of the second clock generating means, the stop means operates the binary counter. The suspension was released,
The output of the symbol clock is started at the phase set in the binary counter.

According to the eighth aspect of the present invention, when the first clock generation means is stopped, the changeover switch selects the output clock of the second clock generation means, and selects the output clock of the second clock generation means. Is operating, the changeover switch selects the output clock of the first clock generation means and supplies it to the control unit.

[0031]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of a reference clock supply device according to the present invention, wherein 1 is a control unit, 2 is a VCTCXO (clock generation unit), 3 is a clock generation unit for a clock, Is a power supply means, 5 is a gate means, 6 is a closing time adjusting means, 7 is an opening time adjusting means, 8
Is a frequency dividing means, 9 is a binary counter, 10 is a stopping means,
11 is a counting means, 12 is a start value setting means, 13 is a return value setting means, and 14 and 15 are comparison means.

In FIG. 1, a control unit 1 is constituted by a microprocessor or the like, controls the operation of the entire apparatus, and
Perform the operation. Here, the clock generation means 2 is composed of a highly stable VCTCXO. The clock generator 3 is a low-power-consumption clock generator that generates a clock used for a clock for time measurement.

The power supply means 4 is for stopping or starting the supply of power to the VCTCXO2, and when turned on, the gate means 5 passes the output clock of the VCTCXO2 and outputs it as a reference clock. Reference numeral 6 denotes a closing time adjusting means. When activated, the gate means 5 is turned off after a preset time, and the VCTCXO 2 is stopped by the power supply means 4. The value (integer value) of C3 is set in the opening time adjusting means 7 in advance. This C3 is V
The open time adjusting means 7 indicates the number of clocks generated by the clock clock generating means 3 during the time from the start of activation of the CTCXO 2 to the stabilization of its output.
When O2 is started, the output clock of the clock generating means 3 is counted. When the counted value becomes equal to the set value c3, the gate means 5 is turned on, and the output clock of the VCTCXO2 is divided by the frequency dividing means 8. The supply to the binary counter 9 is started. The frequency dividing means 8 is supplied with a reference clock from the gate means 5, divides the frequency of the reference clock to a desired frequency, and supplies the frequency to the binary counter 9.

The binary counter 9 is an i-th stage (i is an integer) counter, and outputs an output signal of a j-th stage (an integer satisfying i ≧ j) as a symbol clock. Is possible.

FIG. 2 is a timing chart showing an example of the operation of the binary counter 9.

In this example, j = 3, and the symbol clock is output from the third stage of the binary counter 9. The 3-bit value of the signal of the third and lower stages represents the symbol clock phase in a binary number with eight stages of accuracy, and the control unit 1 can arbitrarily rewrite the third and lower stages of the symbol clock to obtain the symbol clock. The phase can be set to any of eight stages. In addition, the (i-
1) The bit output represents the count value of the symbol clock in a binary number.

Returning to FIG. 1, the stopping means 10 stops and restarts the operation of the binary counter 9. For example, the stopping means 10 stops the output clock of the frequency dividing means 8 supplied to the binary counter 9. It can be realized by canceling or canceling. The counting means 11 counts the output clock of the clock generating means 3. The start value setting means 12 is set by the control unit 1 with a value indicating the timing at which the stop processing of the symbol clock is started. The return value setting means 13 is set by the control unit 1 to a value representing the return timing of the symbol clock, and the set value returns to the value set in the start value setting means 12 after the symbol clock is stopped. It is a value obtained by adding a value obtained by subtracting the set value c3 of the opening time adjusting means 7 from the number of output clocks of the clock clock generating means 3 during the period.

The comparing means 14 compares the set value of the starting value setting means 12 with the count value of the counting means 11 and, when detecting that they match, operates the stopping means 10 to stop the binary counter 9. Then, the closing time adjusting means 6 is activated. The comparing means 15 compares the set value of the return value setting means 13 with the count value of the counting means 11, and when it is detected that they match, operates the stopping means 10 to release the operation stop of the binary counter 9. At the same time, the supply of power to the VCTCXO 2 is started by the power supply means 4 and the opening time adjustment means 7 is started.

Next, the operation of the first embodiment will be described with reference to the flowchart shown in FIG.

When the portable telephone terminal is in the standby state and the intermittent reception is started and the receiving operation is no longer necessary, the processing operation of this embodiment starts (step 200).

That is, first, the control section 1 reads the count value of the counting means 11 and sets the count value m of the counting means 11 at the time when the stop processing of the symbol clock is started to the start value setting means 1.
2 (step 201). Then, in order to perform the next reception, the number of output clocks of the clock clock generating means 3 at the time when the symbol clock returns is calculated. Is set as the return value V (step 202). This return value V is calculated as follows.

Now, the period of the symbol clock is T1, the period of the output clock of the clock generation means 3 is T2,
The value set in the start value setting means 12 and indicating the time point at which the binary counter 9 is stopped is m, the clock number of the symbol clock in the time from the start of the processing operation until the next symbol clock recovery time is c1, and Time adjustment means 7
The number of output clocks of the clock clock generating means 3 during the time from the start of the VCTCXO2 to the stabilization is c3, and the symbol clock is used to perform reception after the symbol clock is stopped. Assuming that the value obtained by subtracting the set value c3 of the opening time adjusting means 7 from the number of output clocks of the clock clock generating means 3 at the time T1 × c1 until the return is c2, the following relational expression (1) holds.

T2 × (c2 + c3) = T1 × (c1-1) + θ2 (1) Here, θ2 is 0 when the initial phase difference between the symbol clock at the start of processing and the output clock of the clock generator 3 is 0.
Is the time T2 × (c2 + c) from the initial point in time.
3) The phase difference between these clocks after elapse, and T2 ×
It is given by the value after the decimal point of (c2 + c3) / (T1 × (c1-1)).

From the above equation (1), c2 is obtained by the following equation.

C2 = int (T1 / T2 × (c1-1)) − c3 (2) where int (X) represents the largest integer not exceeding X.

Accordingly, the return value V set in the return value setting means 13 is given by the following equation (3).

V = m + int (T1 / T2 × (c1-1)) − c3 (3) Here, the phase of the symbol clock is 8 in binary by the 3-bit output signal of the third stage or lower of the binary counter 9.
When θ2 is expressed as a value tb of the third or lower stage of the binary counter 9, this is represented by the number of stages (eight stages from 0 to 7 in decimal number). Represents the phase of the symbol clock,
It looks like this:

Tb = int (8 × θ2) (4) For example, when θ2 = 0.7, tb = 5.
The output bits of the values represented by the base numbers are the first stage of the binary counter 9, the second stage = 0, and the third stage = 1.
In addition, a value after the decimal point of 8 × θ2 is an error.

The calculations of the above equations (1) to (4) may be performed after the processing is started. However, if the value c1 is known in advance as a fixed value, the V, V is stored in a storage element such as a ROM in advance.
The value of tb may be held.

In FIG. 3, next, the comparing means 14 judges whether or not the count value of the counting means 11 and the set value m of the start value setting means 12 match (step 203). By operating the means 10, the operation of the binary counter 9 is stopped to stop the generation of the symbol clock, and the closing time adjusting means 6 is activated (step 204).

The counting timing of the counting means 11 is as follows.
The rising edge of the output clock of the clock generator 3 is set to the rising edge, and the timing of the comparison operation of the comparator 14 is set to the falling edge of the output clock of the clock generator 3.

Here, the value m set by the control unit 1 in the start value setting means 12 in step 201 is sufficient for the count value read by the control unit 1 from the counting means 11 in step 201 to reach this set value m. Are values at which the processing of step 202 can be performed.

Next, the control unit 1 reads the value of the third or lower stage of the binary counter 9 stopped at the timing of the first rising edge of the output clock of the clock clock generating means 3, thereby reading the clock clock generating means. The initial phase ta of the symbol clock for the output clock No. 3 is detected (step 205). The initial phase ta represents the initial phase of the symbol clock in eight stages in a binary number, similarly to the above-described phase tb. Then, the controller 1 sets the phase tb
Is added to the phase ta, and the added value (this is the time T2 ×
(This represents the phase difference between the symbol clock after (c2 + c3) and the output clock of the clock generating means 3)
To the third stage or lower of the binary counter 9 and the value n obtained by adding (c1-1) to the value n of the fourth stage or higher of the stopped binary counter 9 (this is the clock of the symbol clock at time T2 × (c2 + c3)). (Representing a number) is set (step 206).

Thereafter, the control unit 1 performs a standby process so that the supplied reference clock may be stopped (step 207). When the standby process is completed (step 208), the control unit 1 stops. .

Thereafter, when a preset time elapses in the closing time adjusting means 6, the closing time adjusting time 6 turns off the gate means 5 to cut off the output clock of the VCTCXO2, and the power supply means 4 supplies power to the VCTCXO2. The supply is stopped (step 209).

The comparing means 15 determines whether or not the counted value of the counting means 11 and the set value V of the return value setting means 13 match (step 210). Activate the means 7 and start the power supply to the VCTCXO2 by the power supply means 4;
The stopping of the operation of the stopped binary counter 9 is canceled by the stopping means 10 (step 211).

Thereafter, the opening time adjusting means 7 sets the count value of the output clock of the clock generating means 3 to the set value c3.
, The gate means 5 is turned on, and the VCTCX is again turned on.
The reference clock passing through the gate means 5 from O2 is divided by the frequency dividing means 8
And supply to the binary counter 9 is started (step 212). Then, when the supply of the output clock of the frequency dividing means 8 is restarted, the operation of the control unit 1 is restored, and while the binary counter 9 is stopped, the phase indicated by the added value set in the third or lower stage is changed. The symbol clock is output, and the symbol clock returns with the continuity maintained (step 213), and the process ends (step 21).
4).

According to the above operation, even if the binary counter 9 stops, when the operation resumes next time, the symbol clock is output at the same phase as that during the stop period. Therefore, since the bit synchronization and the frame synchronization are maintained, the mobile phone terminal can perform a normal receiving operation.

Next, the above operation will be described with reference to the timing chart shown in FIG. 2A shows the output clock of the clock generating means 3 and FIG.
1, (c) is a symbol clock when the binary counter 9 operates continuously, and (d) is a count value at the fourth or higher stage (symbol clock of the binary clock 9) when the binary counter 9 operates continuously. (E) is the value of the third stage or lower (symbol clock phase) when the binary counter 9 operates continuously, (f) is the stop period of the binary counter 9, and (g) is ) Indicates the operation of the VCTCXO2, FIG. 11H shows the operation of the control unit 1, FIG. 11I shows the symbol clock stop period, and FIG. 3 (k) shows the values of the third and subsequent stages during the stop period of the binary counter 9, respectively.

In FIG. 4, when the processing operation is started, the control section 1 reads the count value of the counting means 11 and sets the count value m of the counting means 11 at a time t2 when the stop processing of the symbol clock is started. Set in the means 12.

In this case, as described above, the counting means 11 outputs the output clock of the clock generating means 3 (FIG. 4).
It counts up at the rising edge of (a)), and the comparing means 14 and 15 perform the comparing operation at the falling edge of the output clock.

Then, the control unit 1 determines the number of clocks c1 of the symbol clock within the time until the reception is restored (time t6), the set value c3 of the release time adjusting means 7, and the symbol clock cycle T1. The above-mentioned c2 is calculated from the output clock cycle T2 of the clock clock means 3, and m + c2 is set as the return value V in the return value setting means 13.

The counting means 11 is used as the clock generating means 3
Is counted by the comparing means 14 and the counting means 11
Is detected (time t2), the comparison means 14 determines that the count value of
The stopping means 10 is operated to stop the operation of the binary counter 9 and the closing time adjusting means 6 is started.

Then, the control section 1 reads the count value of the stopped binary counter 9 and reads the value of the third stage or lower (FIG. 4).
From (k)), the initial phase ta of the symbol clock when the binary counter 9 is stopped (here, the number of output clocks of the frequency dividing means 8 between times t1 and t2, and time t1 is the symbol clock immediately before time t2) Of the symbol clock is detected from the values of the fourth and higher stages (FIG. 4 (j)), and the value of n + c1-1 is calculated in the fourth and higher stages of the binary counter 9. Tb + in the third stage and below
Write the value of ta respectively.

Here, in FIG. 4E, tb =
7, ta = 3, and the phase is an octal number from tb + ta, so that 12 is written in the third and subsequent stages in a binary-coded decimal number. If the result of tb + ta exceeds 8, there is a carry, and the value to be set in the fourth or higher stage of the binary counter 9 is n + c1-1 + 1 = n + c1, and the value of 2 is written in the third or lower stage. .

The value of 2 written in the third and lower stages is
As shown in FIGS. 4D and 4E, the binary counter 9
When the c1 symbol clocks are continuously generated from the value n (time t2) at the fourth stage or more, the c1st (time t5) symbol clock with respect to the output clock of the clock generator 3 The phase is shown.

The above operation is performed by reading the count value of the counting means 11 and the count value of the binary counter 9 at time t2. Thereafter, the control unit 1 performs a process of shifting to the standby state and enters the standby state. .

In the closing time adjusting means 6, a time sufficient for the control unit 1 to perform the above calculation and the standby process is set in advance, and when the set time elapses, the closing time adjusting means 6 sets the gate time. 5 is turned off, and the power supply to the VCTCXO2 is stopped by the power supply means 4 (time t3).

Thereafter, the comparing means 15 causes the counting means 1
When it is detected that the count value of 1 has become m + c2 (time t4), the comparing means 15 sends the VCT
The power supply to the XCO 2 is started, the opening time adjusting means 7 is started, and the stopping means 10 is operated to release the operation stop of the binary counter 9. The count value c3 of the clock generation means 3 set in advance in the opening time adjustment means 7 is set as a time when the oscillation state is sufficiently stabilized after the power supply of the VCTCXO2 is supplied.

When the opening time adjusting means 7 is started, it starts counting the output clock of the clock clock 3, and when the counted value reaches the above set value c3 (time t6), the gate means 5 is turned on and the binary clock is turned on. The output clock of the frequency dividing means 8 is supplied to the counter 9. As a result, the symbol clock returns from the binary counter 9 with the phase of the value 2 set in the third and lower stages.

As described above, in this embodiment, even when the binary counter 9 is stopped, the symbol clock returns at the same phase as when the symbol clock is continuously generated when the binary counter 9 is restored. Therefore, in the standby state, the power supply to the VCTCXO2 can be stopped while maintaining the continuity of the symbol clock and maintaining the bit synchronization and the frame synchronization, and the power consumption of the mobile phone terminal can be reduced.

FIG. 5 is a block diagram showing a second embodiment of the reference clock supply device according to the present invention, wherein 16 is a latch means, 17 is an AND gate, and portions corresponding to those in FIG. A duplicate description will be omitted.

In the figure, the latch means 16 holds the count value of the counting means 11 according to the control signal of the control unit 1.
The AND gate 17 controls the stop unit 10 based on the reverse edge of the output clock of the clock generation unit 3 when the count value is held by the latch unit 16 and the control signal of the control unit 1.
To stop the binary counter 9.

Next, the operation of the second embodiment will be described with reference to the flowchart shown in FIG.

In the figure, when the portable telephone terminal is in a standby state and the intermittent reception is started and the reception operation becomes unnecessary, the processing operation starts (step 200). The control unit 1 outputs a control signal and causes the latch unit 16 to hold the count value m of the counting unit 11 at this time. Further, the stopping means 10 operates and the binary counter 9 is stopped by the reverse edge of the clock input to the counting means 11 when the latch means 16 is held and the output signal of the AND gate 17 which is the logical product of the control signal. Then, the symbol clock stops. Further, the closing time adjusting means 6 is activated by the control signal from the control unit 1 holding the latch means 16 (step 215).

After that, the control section 1 reads the value m held in the latch means 16 (step 216). Then, from the value of m, the same processing as step 202 in the flowchart of FIG. 3 showing the operation of the first embodiment is performed, and the return value V is set in the return value setting means 13. Then, similarly to the first embodiment, a series of processing of steps 205 to 214 is performed.

In this way, this embodiment has exactly the same effects as the first embodiment.

FIG. 7 is a block diagram showing a third embodiment of the reference clock supply device according to the present invention. In FIG. 7, reference numeral 18 denotes an external input detecting means, reference numeral 19 denotes a starting means, and reference numeral 20 denotes an OR gate. The same reference numerals are given to the portions, and the duplicate description will be omitted.

In the figure, the external input detecting means 18
It detects the presence or absence of a key operation of the mobile phone terminal.
The activation unit 19 activates the opening time adjustment unit 7 via the OR gate 20 when the external input detection unit 18 detects an external key operation.
The power supply to the CTCXO2 is started, and the control unit 1
To the effect that the power supply to the VCTCXO2 has been started by an external input. The OR gate 20 is connected to the comparing means 15
And the output of the activating means 19, and the open time adjusting means 7 is activated by the output, and the power supply means 4 starts the power supply to the VCTCXO2.

In this embodiment, a processing operation is also performed by an external key operation. This operation will be described with reference to a flowchart shown in FIG.

In the figure, the processing of steps 201 to 210 is exactly the same as in the first embodiment.

The count value of the counting means 11 and the return value setting means 1
If no match of the return value V set to 3 is detected by the comparing means 15 (step 210), it is determined whether an external input has been detected (step 217). At this time,
If no external input is detected, the process returns to step 210.

In the loop processing of steps 210 and 217, an external input is detected by the time the comparator 15 detects a match between the count value of the counting means 11 and the return value V of the return value setting means 13 (step 210). If not performed (step 217), step 2 similar to the first embodiment is performed.
A series of operations from 11 to 214 is performed.

If an external input is detected (step 217) before the comparison means 15 detects a match between the count value of the counting means 11 and the return value V of the return value setting means 13 (step 210), the activation means 19 activates the opening time adjusting means 7 and causes the power supply means 4 to start supplying power to the VCTCXO 2 and reports this to the control unit 1 (step 218).

When the count value of the output clock of the clock generator 3 reaches the set value c3, the open time adjusting means 7 turns on the gate means 5 and the binary counter 9 supplies the reference clock. Is supplied (step 219). When the reference clock is supplied, the operation of the control unit 1 returns (step 220). When the report signal is input from the activation unit 19 at the time of the return, the control unit 1 sends the return value setting unit 13 Then, an added value of the return value V set there and the set value c3 of the opening time adjusting means 7 is reset (step 221).

Next, the comparing means 15 compares the count value of the counting means 11 with the value set in the return value setting means 13 (step 222).
By operating 0, the stop of the binary counter 9 is released, the symbol clock is restored (step 223), and the process ends (step 214), and the mobile phone terminal performs a receiving operation.

Here, during the period from the start of the opening time adjusting means 7 (step 218) to the return processing of the control section 1 (step 220), the comparing means 15 causes the counting means 1 to operate.
When a match between the count value of 1 and the set value of the return value setting means 13 is detected, a report signal is output from the comparing means 15 to the control unit 1. As described above, when the report signal is input from the comparison unit 15, even when the report signal is input from the activation unit 19, steps 221 and 222 are performed.
Is not performed, and the operation of step 223 is performed.

By performing the above processing, V
Even if CTCXO2 detects an external input while stopped,
VCTCXO2 can be restored.

FIG. 9 is a block diagram showing a fourth embodiment of the reference clock supply device according to the present invention. Reference numeral 21 denotes a changeover switch, and portions corresponding to those in FIG. Is omitted.

In the figure, a changeover switch 21 switches between the reference clock output from the gate means 5 and the output clock from the clock generation means 3 and supplies the same to the control unit 1.

In this embodiment, when the gate means 5 is turned off and the reference clock is stopped, the changeover switch 21 is switched to the clock generation means 3 side, the gate means 5 is turned on, and the reference clock is turned off. If supplied, the changeover switch 21 switches to the gate means 5 side and supplies this reference clock to the control unit 1.

In this embodiment, since the clock supplied to the control unit 1 does not stop, the control unit 1 can perform processing even when the VCTCXO 2 is stopped.

FIG. 10 is a block diagram showing a fifth embodiment of the reference clock supply device according to the present invention. Reference numeral 22 denotes stop time adjusting means, reference numeral 23 denotes release time adjusting means.
The same reference numerals are given to the portions corresponding to and the duplicate description will be omitted.

In the figure, the stop time adjusting means 22 comprises:
When activated by the comparing means 14, the power supply means 4 stops supplying power to the VCTCXO2 after a preset time has elapsed. When activated by the comparing means 15, the release time adjusting means 23 counts the output clock of the clock generating means 3 by a preset value c3, and then controls the stopping means 10 to stop the operation of the binary counter 9. Release.

Next, the operation of the fifth embodiment will be described with reference to the flowchart shown in FIG.

When the portable telephone terminal is in the standby state and the intermittent reception is started and the reception operation becomes unnecessary, a series of processing of steps 200 to 203 is performed as in the first embodiment.

The counting value of the counting means 11 and the starting value setting means 1
When the comparison unit 14 detects a match with the set value of 2 (step 203), the comparison unit 14 operates the stop unit 10 to stop the binary counter 9, stops the symbol clock, and sets the stop time adjustment unit. 22 is started (step 224). Then, a series of processing in steps 205 to 208 is performed in the same manner as in the first embodiment.

Thereafter, when a preset time elapses in the stop time adjusting means 22, the stop time adjusting means 22 stops the power supply to the VCTCXO2 by the power supply means 4 to stop the generation of the reference clock (step 22).
5) After that, when the comparison unit 15 detects a match between the count value of the counting unit 11 and the return value of the return value setting unit 13 (step 210), the comparison unit 15 activates the release time adjustment unit 23. , VCTCXO by the power supply means 4
2 and the supply of the reference clock to the binary counter 9 is started (step 226).

Then, the control unit 1 returns (step 22).
7), when the release time adjusting means 23 counts the output clock of the clock clock generating means 3 by the set value c3, the release time adjusting means 23 operates the stopping means 10 to cancel the stop of the operation of the binary counter 9; The symbol clock is restored with the same phase as when the symbol clock is supplied continuously (step 228).

As described above, also in this embodiment, effects similar to those of the first embodiment can be obtained.

FIG. 12 is a block diagram showing a sixth embodiment of the reference clock supply device according to the present invention, and portions corresponding to FIGS. 5 and 10 are denoted by the same reference numerals.

In this embodiment, a stop time adjusting means 22 and a release time adjusting means 23 as shown in FIG. 10 are provided in the second embodiment shown in FIG.

Next, the operation of the sixth embodiment will be described with reference to the flowchart shown in FIG.

When the processing operation is started (step 20)
0), the process of step 229 is performed. This step 229 is the same as step 215 in FIG. 10 showing the operation of the second embodiment, except that the part for activating the closing time adjusting means 6 is activated to activate the stopping time adjusting means 22. is there. Then, as in the second embodiment,
Step 216, Step 202, Step 205-2
08 is performed.

Next, when a predetermined time elapses in the stop time adjusting means 22, the stop time adjusting means 22 stops the power supply to the VCTCXO2 by the power supply means 4 and stops the generation of the reference clock (step 225). ). Then, similarly to the fifth embodiment, a series of processes of Step 210 and Steps 226 to 228 is performed, and the process ends (Step 214).

As described above, this embodiment has the same effects as the second embodiment.

FIG. 14 is a block diagram showing a seventh embodiment of the reference clock supply device according to the present invention, and portions corresponding to FIGS. 7 and 10 are denoted by the same reference numerals.

This embodiment uses the stop time adjusting means 22 and the release time adjusting means 23 as shown in FIG. 10 in the third embodiment shown in FIG.

Next, the operation of the seventh embodiment will be described with reference to the flowchart shown in FIG.

When the processing operation is started (step 20)
0), steps 201 to 20 as in the fifth embodiment.
Steps 210, 224, 205 to 208, and 225 are performed to perform a series of steps 210.

The count value of the counting means 11 and the return value setting means 1
If the return value V of No. 3 is not detected by the comparing means 15 (step 210), it is determined whether an external input has been detected (step 217). If no external input has been detected, the process returns to step 210. This step 210, 21
7, the coincidence between the count value of the counting means 11 and the return value V of the return value setting means 13 is determined by the comparing means 15.
If there is no external input detection by the time (step 210), the series of processing of steps 226 to 228 and step 214 is performed as in the fifth embodiment.

If an external input is detected (step 217) before the comparison means 15 detects a match between the count value of the counting means 11 and the return value V of the return value setting means 13 (step 210), The starting unit 19 causes the power supply unit 4 to start supplying power to the VCTCXO2, starts supplying a reference clock to the binary counter 9 (step 230), and returns the control unit 1 (step 220).

The comparing means 15 compares the count value of the counting means 11 with the return value V of the return value setting means 13 (step 222).
Starts the release time adjusting means 23 (step 23).
1). Thereafter, when the count value of the output clock of the clock generating means 3 reaches the set value c3 by the release time adjusting means 23, as in the fifth embodiment, step 228 is performed and the process is terminated (step 214). ).

As described above, also in this embodiment, the third
The same effect as that of the embodiment can be obtained.

FIG. 16 is a block diagram showing an eighth embodiment of the reference clock supply device according to the present invention. Parts corresponding to those in FIGS. 9 and 10 are denoted by the same reference numerals, and redundant description is omitted.

In this embodiment, the stop time adjusting means 22 and the release time adjusting means 23 as shown in FIG. 10 are provided in the fourth embodiment shown in FIG.

In this embodiment, when the VCTCXO2 is stopped by the power supply means 3 and the generation of the reference clock is stopped, the changeover switch 21 is switched to the clock generation means 3 side, and the VCTCXO2 operates. If there is, switch to the VCTCXO2 side and supply the clock to the control unit 1.

This embodiment has the same effects as the fourth embodiment.

In the embodiment described above, the power supply means 3 stops the power supply of the VCTCXO2. However, the power supply means 3 may stop the oscillation operation of the VCTCXO2. Can be.

[0121]

As described above, according to the present invention,
Bit management and frame synchronization can be performed by controlling the time using the second clock generating means having very low power consumption and controlling the phase of the symbol clock formed based on the output clock of the first clock generating means. , The first clock generation means constituted by the VCTCXO can be stopped, so that power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a reference clock supply device according to the present invention.

FIG. 2 is a timing chart showing an operation example of a binary counter.

FIG. 3 is a flowchart showing an operation of the first embodiment shown in FIG. 1;

FIG. 4 is a timing chart showing an operation of the first embodiment shown in FIG. 1;

FIG. 5 is a block diagram showing a second embodiment of the reference clock supply device according to the present invention.

FIG. 6 is a flowchart showing the operation of the second embodiment shown in FIG.

FIG. 7 is a block diagram showing a third embodiment of the reference clock supply device according to the present invention.

8 is a flowchart showing the operation of the third embodiment shown in FIG.

FIG. 9 is a block diagram showing a fourth embodiment of the reference clock supply device according to the present invention.

FIG. 10 is a block diagram showing a fifth embodiment of the reference clock supply device according to the present invention.

FIG. 11 is a flowchart showing the operation of the fifth embodiment shown in FIG.

FIG. 12 is a block diagram showing a sixth embodiment of the reference clock supply device according to the present invention;

FIG. 13 is a flowchart showing the operation of the sixth embodiment shown in FIG.

FIG. 14 is a block diagram showing a seventh embodiment of the reference clock supply device according to the present invention.

FIG. 15 is a flowchart showing the operation of the seventh embodiment shown in FIG.

FIG. 16 is a block diagram showing an eighth embodiment of the reference clock supply device according to the present invention.

FIG. 17 is a configuration diagram of a control channel.

FIG. 18 is a diagram illustrating an operation of the mobile phone terminal during communication.

FIG. 19 is a block diagram illustrating a configuration example of a digital mobile phone terminal.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Control part 2 Clock generating means (VCTCXO) 3 Clock generating means 4 Clock supply means 5 Gate means 6 Closing time adjusting means 7 Opening time adjusting means 8 Dividing means 9 Binary counter 10 Stopping means 11 Counting means 12 Start value setting Means 13 Return value setting means 14, 15 Comparison means 16 Latch means 18 External input detection means 19 Starting means 21 Changeover switch 22 Stop time adjusting means 23 Release time adjusting means

────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yasuaki Takahara 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Hitachi, Ltd. Multimedia System Development Division (56) References JP-A-7-20964 (JP, A) JP-A-60-251418 (JP, A) JP-A-7-281782 (JP, A) JP-A-9-18405 (JP, A) JP-A-8-307304 (JP, A) JP-A-6-350509 (JP, A) JP-A-6-6255 (JP, A) Table 8-8-504075 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 1/04 H03K 3 / 02 H04B 7/26

Claims (9)

(57) [Claims] 1. A reference clock supply device for generating a reference clock used in a portable telephone terminal device or the like, comprising: a control unit including a microprocessor for controlling and calculating the entire operation; First clock generation means for generating a clock, second clock generation means for generating a clock of a second frequency, power supply to the first clock generation means, or power supply for stopping and starting the operation Means for closing or opening the output clock of the first clock generating means and outputting the clock as a reference clock; and when activated, the gate means is closed after a preset time and the power supply Means for supplying power to the first clock generating means or stopping the operation by means of the first clock generating means; Opening time adjusting means for opening the gate means after counting the output clock of the lock generating means by a preset value, frequency dividing means for dividing the reference clock from the gate means to a desired frequency, i (where i is an integer) stages, the output clock of the frequency dividing means is supplied, and a symbol clock is output from the jth (where j is an integer that satisfies i ≧ j) stage. A binary counter capable of reading and writing a count value, stopping means for stopping or canceling the operation of the binary counter, counting means for counting the number of output clocks of the second clock generating means, and stopping processing of the symbol clock. A start value setting unit that sets the count value of the counting unit at a start time to the set value of the start value setting unit; A return value setting means sets a value obtained by adding a value obtained by subtracting a count value preset in the open time adjusting means from the number of output clocks of the second clock generation means as a return value. And comparing the set value of the start value setting means with the count value of the counting means, and when it is detected that they match, the stopping means stops the operation of the binary counter, and the closing time First comparing means for activating the adjusting means; comparing the return value of the return value setting means with the count value of the counting means; Release the operation stop of the binary counter,
A second comparing means for starting power supply or operation to the first clock generating means by the power supply means and activating the open time adjusting means; and setting the start value by the first comparing means. When the coincidence between the set value of the means and the count value of the counting means is detected, the control unit controls the binary counter which stops the phase difference between the output clock of the second clock generation means and the symbol clock. the time from the j-th stage or lower to the time when the second comparison means detects that the set value of the return value setting means matches the count value of the counting means, The phase of the symbol clock after a time obtained by adding the time when the counting is completed is calculated and set in the binary counter. When a time set in the closing time adjusting means elapses, the gate means is closed. And the power supply The power supply means stops the power supply or operation to the first clock generation means, stops the supply of the reference clock, and the second comparison means compares the return value of the return value setting means with the count. When the coincidence with the count value of the means is detected, the power supply means starts power supply or operation to the first clock generation means, and the second clock signal is supplied to the second clock by a value preset in the open time adjustment means. When the output clock of the clock generation means is counted, the gate means is opened to supply the reference clock to the binary counter, and to start outputting the symbol clock at the phase set in the binary counter. Reference clock supply. 2. A reference clock supply device for generating a reference clock used in a portable telephone terminal device or the like, comprising: a control unit including a microprocessor for controlling the entire operation and performing an operation; First clock generating means for generating a clock of a second frequency; second clock generating means for generating a clock of a second frequency; and power supply for stopping or starting the operation of the first clock generating means. Means for closing or opening the output clock of the first clock generating means and outputting the clock as a reference clock; and when activated, the gate means is closed after a preset time and the power supply Closing time adjusting means for stopping power supply or operation to the first clock generating means by the means; Opening time adjusting means for opening the gate means after counting the output clock of the clock generating means by a preset value, and frequency dividing means for dividing the reference clock from the gate means to a desired frequency. , I (where i is an integer) stages, the output clock of the frequency dividing means is supplied, and a symbol clock is output from the jth (where j is an integer satisfying i ≧ j) stage, and the control unit A counter capable of reading and writing a count value, a stop unit for stopping or canceling the operation of the binary counter, a counting unit for counting the number of output clocks of the second clock generation unit, and a control from the control unit. Latch means for holding the count value of the counting means by a signal, and a value held by the latch means;
A value obtained by adding a value obtained by subtracting a count value preset in the open time adjusting means from the number of output clocks of the second clock generating means until the return time of the symbol clock,
As the return value, the return value setting means set by the control unit, and the return value of the return value setting means and the count value of the counting means are compared. The stopping means releases the operation stop of the binary counter,
A second comparing means for starting the supply or operation of the first clock generating means by the power supply means and activating the open time adjusting means, wherein a control signal is sent from the control unit; , The closing time adjusting means is activated, the stopping means stops the binary counter at an edge of the output clock of the second clock generating means, and outputs the output clock of the second clock generating means and the symbol clock. The time when the phase difference is detected from the value of the j-th stage or less of the binary counter that has stopped, and the second comparison means detects that the return value of the return value setting means matches the count value of the counting means. The phase of the symbol clock after a time obtained by adding the time when the counting by the open time adjusting means is completed is calculated and set in the binary counter, and the phase is set in the closed time adjusting means in advance. After a period of time, the gate means is closed and the power supply means
The power supply or operation to the first clock generation means is stopped, the supply of the reference clock is stopped, the return value of the return value setting means and the count value of the counting means are returned by the second comparison means. When a match is detected, power supply or operation to the first clock generation means is started by the power supply means, and the second clock is supplied by a count value preset in the open time adjustment means. When the output clock of the generating means is counted, the gate means is opened to supply a reference clock to the binary counter, and to start outputting the symbol clock at the phase set in the binary counter. Clock supply. 3. An external input detecting means according to claim 1, wherein said external input detecting means detects an input from the outside, an activation means for outputting an activation signal when an input is detected by said external input detecting means, and said activation means. And an OR gate for receiving an output signal of the second comparison means and outputting to the open time adjustment means and the power supply means, wherein the power supply means stops the first clock generation means. In this case, when an external input is detected by the external input detection unit, the activation unit reports to the control unit, activates the open time adjustment unit, and activates the first power supply unit by the power supply unit. The power supply or operation to the clock generating means is started, and when the count of the open time adjusting means is completed, the gate means is opened to supply the reference clock to the binary counter. After that, the control unit receives a report from the activation unit, and the second comparison unit detects that the return value of the return value setting unit matches the count value of the counting unit. If not, reset the return value setting means to a value obtained by adding a count value preset to the open time adjusting means to the return value, and return the return value setting means by the second comparing means When the coincidence between the return value and the count value of the counting means is detected, the stop means cancels the stop of the operation of the binary counter and returns the symbol clock. 4. The control unit according to claim 1, 2 or 3, wherein one of the reference clock output from the gate unit and the output clock of the second clock generation unit is selected and supplied to the control unit. A changeover switch, wherein the switch selects the output clock of the second clock generation means when the gate means is closed, and the changeover switch when the gate means is open. Selects the reference clock output from the gate means. 5. A reference clock supply device for generating a reference clock used in a portable telephone terminal device or the like, comprising: a control unit including a microprocessor for controlling and calculating the entire operation; First clock generation means for generating a clock, second clock generation means for generating a clock of a second frequency, power supply to the first clock generation means, or power supply for stopping and starting the operation Means for stopping power supply to the first clock generating means or stopping the operation by the power supply means after a preset time when activated, and the first clock generating means And i (where i is an integer) stages. The output clock of the frequency dividing means is supplied, (Where j is an integer that satisfies i ≧ j) A symbol counter is output from the stage, a binary counter capable of reading and writing the count value by the control unit, a stop means for stopping or canceling the operation of the binary counter, When activated, a release time adjusting means for counting the output clock of the second clock generating means by a preset value and then releasing the stop of the binary counter by the stopping means; Counting means for counting the number of output clocks of the means; start value setting means for setting the count value of the counting means at the time when the stop processing of the symbol clock is started; The set value is calculated from the number of output clocks of the second clock generation means up to the return time of the symbol clock and a count value preset in the release time adjustment means. A value obtained by adding the subtracted value is used as a return value. The return value setting means set by the control unit, the set value of the start value setting means and the count value of the counting means are compared, and both values are matched. When detecting, the stop means stops the operation of the binary counter, activates the stop time adjusting means, a first comparing means, a return value of the return value setting means, and a count value of the counting means. And comparing the two with each other, when it is detected that the two coincide with each other, the power supply means starts power supply or operation to the first clock generation means and starts the release time adjustment means. When the first comparison means detects a match between the set value of the start value setting means and the count value of the counting means, the control unit:
The phase difference between the output clock of the second clock generation means and the symbol clock is detected from the value of the j-th stage or less of the stopped binary counter, and the second comparison means detects the return value of the return value setting means. Calculates the phase of the symbol clock after adding the time until the coincidence with the count value of the counting means is detected and the time when the counting of the release time adjusting means ends, and outputs the phase of the symbol clock to the binary counter. After the time set in the stop time adjusting means elapses, the power supply means stops power supply or operation to the first clock generation means and stops supply of the reference clock. When the second comparison means detects that the return value of the return value setting means matches the count value of the counting means, the power supply means supplies power to the first clock generation means or Behavior When the output clock of the second clock generation means is counted by a value preset in the release time adjustment means, the stop of the binary counter is released by the stop means, and the output of the binary counter is set. A reference clock supply device, which starts outputting the symbol clock at the phase. 6. A reference clock supply device for generating a reference clock used in a portable telephone terminal device or the like, comprising: a control unit including a microprocessor for controlling and calculating the entire operation; First clock generation means for generating a clock, second clock generation means for generating a clock of a second frequency, power supply to the first clock generation means, or power supply for stopping and starting the operation A stop time adjusting means for stopping power supply or operation of the first clock generating means by the power supply means after a preset time when activated, and a stop time adjusting means of the first clock generating means. A frequency dividing means for dividing the output clock to a desired frequency; and i (where i is an integer) stages, wherein the output clock of the frequency dividing means is supplied and j (Where j is an integer that satisfies i ≧ j)) A symbol counter is output from the stage, a binary counter capable of reading and writing the count value by the control unit, a stop unit for stopping or canceling the operation of the binary counter, Then, after counting the output clock of the second clock generation means by a preset value, the release time adjustment means for releasing the stop of the binary counter by the stop means, and the second clock generation means Counting means for counting the number of output clocks, latch means for holding a count value of the counting means by a control signal from the control unit, and a value held by the latch means until the return time of the symbol clock. A value obtained by adding a value obtained by subtracting a value preset in the release time adjusting means from the number of output clocks of the second clock generating means, as a return value, The return value setting means set by the control unit is compared with the return value of the return value setting means and the count value of the counting means. And a comparing means for starting power supply or operation to the first clock generating means and activating the release time adjusting means. When a control signal is sent from the control section, the stop time adjusting means is activated. The stopping means stops the binary counter at the edge of the output clock of the second clock generating means, and stops the phase difference between the output clock of the second clock generating means and the symbol clock. Detecting from the values below the stage, the comparison unit detects the coincidence between the return value of the return value setting unit and the count value of the counting unit, and the counting of the release time adjustment unit ends. The phase of the symbol clock after a time obtained by adding the time is calculated and set in the binary counter. When the time preset in the stop time adjusting means elapses, the first power supply means sets When the power supply or operation to the clock generation means is stopped, the supply of the reference clock is stopped, and the comparison means detects that the return value of the return value setting means matches the count value of the counting means. When power supply or operation to the first clock generation means is started by the power supply means and the output clock of the second clock generation means is counted by a count value preset in the release time adjustment means, The stopping means releases the stop of the operation of the binary counter, and starts outputting the symbol clock at the phase set in the binary counter. Clock supply. 7. An external input detecting means according to claim 5, wherein said external input detecting means detects an input from outside, said starting means outputting a start signal when said external input detecting means detects an input, and said starting means. And an OR gate for receiving an output signal of the second comparison means and outputting the signal to the power supply means, wherein the external input is provided when the first clock generation means is stopped by the power supply means. When the detection unit detects an external input, the start unit reports the input to the control unit and starts power supply or operation to the first clock generation unit by the power supply unit. When the supply of the reference clock to the counter is restarted, and the second comparison means detects that the return value of the return value setting means matches the count value of the counting means, When the adjusting means is activated and the counting of the output clock of the second clock generating means by the release time adjusting means is completed, the stopping of the binary counter is canceled by the stopping means, and the setting of the binary counter is performed. A reference clock supply device, wherein output of the symbol clock is started at the above phase. 8. The method according to claim 5, wherein one of a reference clock output from said first clock generating means and an output clock of said second clock generating means is selected. A switching switch for supplying to the control unit, wherein when the first clock generation unit is stopped,
When the changeover switch selects the output clock of the second clock generation means, and when the first clock generation means is operating,
The reference clock supply device, wherein the changeover switch selects the reference clock output from the first clock generation means. 9. A mobile terminal device comprising the reference clock supply device according to claim 1. Description: