JPH0962396A - Reference clock supply device and traveling object terminal equipment using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain low power consumption by stopping a VCTCXO as keeping bit synchronization and frame synchronization when no receiving operation is required in a reception awaiting state. SOLUTION: When the reception awaiting state is set, the value of a start value setting means 12 and that of a return value setting means 13 are set, and when the count value of a counter means 11 matches the set value of the start value setting means 12, a binary counter 9 is stopped, and a symbol clock is stopped. The phase of the symbol clock at return time is found from the value in the binary counter 9 and it is written in the binary counter a. After the lape of a set time of a close time adjusting means 6, a gate means 5 is turned off, and power supply to the VCTCXO 2 is stopped. When the count value of the counter means 11 matches the set value of the return value setting means 13, the stoppage of the binary counter 9 is relased, and the power source is supplied to the VCTCXO 2, and after the lapse of a set time of a release time adjusting means 7, the gate means 5 is turned on, and the symbol clock is returned with a set phase by a reference clock.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reference clock supply device for generating a reference clock used in a terminal device such as a mobile phone terminal device, and more particularly to a reference clock supply device for reducing power consumption and the reference clock supply device. The mobile terminal device.

[0002]

2. Description of the Related Art In digital car telephone systems, "digital car telephone system standard"
As described in (RCR STD27 Radio System Development Center), TDM / TDM is used as a communication method.
The A method is adopted.

According to this standard, the portable telephone terminal device performs a predetermined process when the power is turned on, receives a predetermined control channel called a perch channel, and decodes the received data from the received data of this channel. Establishes bit synchronization. After that, frame synchronization and superframe synchronization are established by periodically detecting the synchronization word included in the slot to be received. When these synchronizations are established, the mobile phone terminal receives the broadcast channel (BCCH) and shifts to the channel designated by this BCCH.

FIG. 17 shows the structure of the control channel.

The position of the paging channel (PCH) to be received by the own station is determined by the control information broadcasted on the BCCH of the transfer destination control channel, and the intermittent reception operation is performed.
This intermittent reception operation is a so-called standby state.
In this state, the receiving operation may be performed for several 6.7 msec once in a relatively long cycle of several hundred msec, and the transmission from the mobile phone terminal device in the standby state may include location registration and call origination processing. However, it is not performed regularly.

However, at the time of intermittent reception, P should be received by the own station.
Frame synchronization and superframe synchronization must be maintained in order to determine the CH position.

During communication, as shown in FIG.
The reception R, idle I, transmission T, and antenna switching diversity level measurement period LM are repeatedly operated.

FIG. 19 is a block diagram showing an example of the configuration of a mobile phone terminal device.

In FIG. 1, the received signal received by the antenna 101 is the demultiplexer 102, the receiving section 103, and the demodulating section 1.
The audio signal output from the speaker via the 06, the channel codec unit 109, and the audio codec unit 110 and input from the microphone 113 is the audio codec 11
0, the channel codec unit 109, the modulation unit 107, the transmission unit 104, and the demultiplexer 102 to output from the antenna 101. Further, control signals necessary for communication are exchanged between the channel codec unit 109 and the microprocessor 111.

The reference clock required for the entire operation is supplied from a highly stable voltage controlled temperature compensated crystal oscillator (VCTCXO) 108.

Since it is desired to use the portable telephone terminal device for a long time, the receiving unit 103, the transmitting unit 104 and the demodulating unit 10 are required.
6. The modulation unit 107 and the like diligently perform power supply control so that it operates only for a minimum time when necessary for communication, and the microprocessor 111, which performs overall control, performs intermittent reception during standby. At this time, only the key operation processing is operated and other processing is shifted to the standby mode to reduce the power consumption.

However, the VCTC which supplies the reference clock
The XO 108 was always operating in order to maintain frame synchronization and return from the standby mode of the microprocessor 111 by key operation processing.

[0013]

As described above,
While each unit constituting the mobile phone terminal device frequently controls the power source to reduce the power consumption, the VCTCXO which generates the reference clock always operates. In particular, at the time of intermittent reception, the VCTCXO is operating only for maintaining the frame synchronization and handling the key operation even though other operations are stopped, which is not sufficient for reducing power consumption. There wasn't.

It is an object of the present invention to maintain frame synchronization using an oscillator with very low power consumption and to provide a VCTCXO.
Another object of the present invention is to provide a reference clock supply device and a mobile terminal device using the reference clock supply device, which are configured to stop at times other than necessary at the time of intermittent reception during standby to reduce power consumption.

[0015]

In order to achieve the above-mentioned object, the first aspect of the present invention is a control section for controlling and operating the entire operation, and a first frequency generating clock of a first frequency.
Clock generating means, second clock generating means for generating a clock of a second frequency, power supply means for stopping or starting the power supply or operation of the first clock generating means, and the first clock generating means. Gate means for closing or opening the output clock of the clock generating means and outputting it as a reference clock; and, when activated, closing the gate means after a preset time and generating the first clock by the power supply means. Closing time adjusting means for stopping power supply to the means or operation, and opening time for opening the gate means after counting the output clock of the second clock generating means by a preset value when activated Adjusting means,
The reference clock that has passed through the gate means is divided into a desired frequency and frequency dividing means and i (where i is an integer) stages, and the output clock of the frequency dividing means is input to j (however,
(j is an integer that satisfies i ≧ j), a symbol clock is output from the (third) stage, a binary counter capable of reading and writing a count value by the control unit, a stop unit that stops or cancels the operation of the binary counter, and the second counter Counting means for counting the number of output clocks of the clock generating means, the start value setting means for setting the count value of the counting means at the time when the stop processing of the symbol clock is started, and the start value. A value obtained by adding a value obtained by subtracting a count value preset in the open time adjusting means from the number of output clocks of the second clock generating means up to the return time of the symbol clock to the set value of the setting means, As the return value, the return value setting means set by the control unit is compared with the set value of the start value setting means and the count value of the counting means, and it is detected that both match. And comparing the return value of the return value setting means and the count value of the counting means with the first comparing means for stopping the operation of the binary counter by the stop means and activating the closing time adjusting means. However, when it is detected that the two coincide with each other, the stop means releases the operation stop of the binary counter, and the power supply means releases the first counter.
Second comparing means for starting power supply or operation to the clock generating means and activating the opening time adjusting means.

The second aspect of the present invention is the control section, the first clock generating means, the second clock generating means, the power supply means, the gate means, and the closing time adjustment. Means, the opening time adjusting means, the frequency dividing means, the binary counter, the stopping means,
The counting means, the latch means for holding the value of the counting means by the control signal from the control section, and the second clock generation until the symbol clock recovery time is set to the value held in the latch means. A value obtained by adding a value obtained by subtracting the count value preset in the opening time adjusting means from the number of output clocks of the means is used as a return value, the return value setting means set by the control unit, and the second And comparison means.

Furthermore, a third aspect of the present invention provides the above first and second aspects.
The external input detecting means for detecting an input from the outside, the starting means for outputting a starting signal when the input is detected by the external input detecting means, the starting means and the second comparing means. And an OR gate which outputs the output signal to the opening time adjusting means and the power supply means.

Furthermore, a fourth aspect of the present invention is the above-mentioned first to third aspects.
In the invention, there is provided a changeover switch for selecting one of the reference clock output from the gate means and the output clock of the second clock generating means and supplying the selected clock to the control unit.

Furthermore, a fifth aspect of the present invention includes the control section,
The first clock generation means, the second clock generation means, the power supply means, and when activated, the first power generation means causes the power supply means to perform a first preset time.
Stop time adjusting means for stopping the power supply or operation of the clock generating means, the frequency dividing means, the binary counter, the stopping means, and the second
After counting the output clock of the clock generating means by a preset value, release time adjusting means for releasing the stop of the binary counter by the stopping means, the counting means, the start value setting means, and the return When comparing the set value of the value setting means and the set value of the start value setting means and the count value of the counting means, and detecting that both match,
The stop means stops the operation of the binary counter and activates the stop time adjusting means, and the return value of the return value setting means and the count value of the counting means are compared. When it finds a match,
The power supply means starts power supply or operation to the first clock generation means, and the second comparison means activates the release time adjustment means.

Furthermore, a sixth aspect of the present invention includes the control section,
The first clock generating means, the second clock generating means, the power supply means, the stop time adjusting means, the frequency dividing means, the binary counter, the stop means, and the release time. Adjusting means, the counting means,
The latch means, the return value setting means, and the comparing means are provided.

Further, in a seventh aspect of the present invention based on the fifth and sixth aspects, the output signals of the external input detection means, the activation means, the activation means, the external input detection means and the comparison means are input. And an OR gate for outputting to the power supply means.

Further, in an eighth aspect of the present invention, in any one of the fifth to seventh aspects, one of a reference clock output from the first clock generating means and an output clock of the second clock generating means. And a changeover switch for selecting and supplying to the control unit.

[0023]

In the first aspect of the invention, when the first comparing means detects the coincidence, the control section stops the phase difference between the output clock of the second clock generating means and the symbol clock. The symbol after the time obtained by adding the time at which the second comparing means detects the coincidence and the time at which the counting by the opening time adjusting means ends by detecting from the value of the jth stage or less of the binary counter When the phase of the clock is calculated, this is set in the binary counter, and the time preset by the closing time adjusting means elapses, the gate means is closed, and the power supply means causes the first clock to be closed. When the power supply or the operation to the generating means is stopped, the supply of the reference clock to the binary counter is stopped, and the coincidence is detected by the second comparing means, the power supply When the power supply means starts the power supply or operation of the first clock generation means and the opening time adjustment means counts the output clock of the second clock generation means by a preset value, the gate means is opened. The reference clock is supplied to the binary counter, and the output of the symbol clock starts at the phase set in the binary counter.

In the second aspect of the present invention, when the control signal is sent from the control section, the closing time adjusting means is activated, and the stopping means causes an edge of the output clock of the second clock generating means. The binary counter is stopped, and the phase difference between the output clock of the second clock generating means and the symbol clock is detected from the value of the jth stage or less of the stopped binary counter, and the second comparing means is matched. Is calculated and the phase of the symbol clock after the time when the counting of the opening time adjusting means ends is added, the calculated phase is set in the binary counter, and the counting of the closing time adjusting means is performed. At the end, the gate means is closed and the power supply means stops the power supply to the first clock generation means to cause the binary When the supply of the reference clock to the counter is stopped and the second comparison means detects the coincidence, the power supply means starts the power supply to the first clock generation means, When the counting of the opening time adjusting means is completed, the gate means is opened, the reference clock is supplied to the binary counter, and the symbol clock is started to be output at the phase set in the binary counter.

In the third aspect of the present invention, when the first clock generating means is stopped by the power supply means and the external input detecting section detects an external input, the starting means is activated. The opening time adjusting means is activated, the power supply means starts power supply or operation to the first clock generating means, and when the counting of the opening time adjusting means ends, the gate means is opened and the opening means is opened. Supply of the above reference clock to the binary counter is restarted,
Thereafter, the control unit resets a value obtained by adding a value preset in the opening time adjusting unit to the value set in the reset value setting unit as a return value in the reset value setting unit, When the second comparing means detects that the return value and the counting value of the counting means match, the stop means releases the operation stop of the binary counter, the binary counter starts operation, and the symbol The clock recovers.

In the fourth aspect of the present invention, when the gate means is closed, the changeover switch is the second switch.
If the output clock of the clock generating means is selected and the gate means is opened, the changeover switch selects the reference clock from the gate means and supplies it to the control section.

In the fifth aspect of the present invention, when the first comparing means detects the coincidence, the control section is
Time at which the phase difference between the output clock of the second clock generating means and the symbol clock is detected from the value of the jth stage or less of the binary counter that has been stopped, and the coincidence is detected by the second comparing means. And the phase at which the symbol clock is counted after the addition of the time when the counting by the release time adjusting means is finished, set this in the binary counter, and the time preset in the stop time adjusting means. When the time elapses, the first power supply means causes the first
If the power supply or operation to the clock generating means is stopped, the supply of the reference clock to the binary counter is stopped, and the coincidence is detected by the second comparing means, the power supplying means is By this, power supply or operation to the first clock generation means is started, and the count value preset in the release time adjustment means is used for the second clock.
When the output clock of the clock generating means is counted, the stop means releases the operation stop of the binary counter, and the output of the symbol clock is started at the phase set in the binary counter.

In the sixth aspect of the present invention, when the control signal is sent from the control section, the stop time adjusting means is activated, and the stop means outputs the edge of the output clock of the second clock generating means. Then, the binary counter is stopped, and the phase difference between the output clock of the second clock generating means and the symbol clock is detected from the value of the jth stage or less of the stopped binary counter, and the second comparing means detects it. The phase of the symbol clock is calculated after adding the time for detecting the coincidence and the time when the counting by the release time adjusting means is finished, and setting this in the binary counter and preset in the stop time adjusting means. After a lapse of a predetermined time, the power supply means stops the power supply or operation to the first clock generating means, When the supply of the reference clock to the counter is stopped and the coincidence is detected by the second comparison means, the power supply means starts the power supply or operation to the first clock generation means. When the output clock of the second clock generating means is counted by a value preset in the release time adjusting means, the stop of the operation of the binary counter is released by the stop means, and the phase is set in the binary counter. The symbol clock starts outputting.

In the seventh aspect of the present invention, when the external input detecting section detects an external input when the first clock generating means is stopped by the power supply means, the starting means is activated. Report to the control unit, the power supply means starts power supply or operation to the first clock generation means, the supply of the reference clock to the binary counter is restarted, and the second comparison means. When the above coincidence is detected, the release time adjusting means is activated, and when the release time adjusting means finishes counting the output clock of the second clock generating means, the stop means operates the binary counter. Has been stopped,
The output of the symbol clock is started at the phase set in the binary counter.

In the eighth aspect of the present invention, when the first clock generating means is stopped, the changeover switch selects the output clock of the second clock generating means, and the first clock generating means. Is operating, the changeover switch selects the output clock of the first clock generating means and supplies it to the control section.

[0031]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of a reference clock supply device according to the present invention, in which 1 is a control unit, 2 is a VCTCXO (clock generation means), 3 is a clock clock generation means, and 4 is a clock clock generation means. Is a power supply means, 5 is a gate means, 6 is a closing time adjusting means, 7 is an opening time adjusting means, 8
Is a frequency dividing means, 9 is a binary counter, 10 is a stopping means,
11 is a counting means, 12 is a start value setting means, 13 is a return value setting means, and 14 and 15 are comparing means.

In the figure, the control unit 1 is composed of a microprocessor or the like, controls the operation of the entire apparatus, and
Calculate. The clock generation means 2 is composed of a highly stable VCTCXO here. The clock generation means 3 for a clock is here a low power consumption clock generation means for generating a clock used for a clock for time measurement.

The power supply means 4 stops or starts the power supply to the VCTCXO2, and when the gate means 5 is turned on, it passes the output clock of the VCTCXO2 and outputs it as a reference clock. 6 is a closing time adjusting means, which, when activated, turns off the gate means 5 after a preset time and stops the VCTCXO 2 by the power supply means 4. The opening time adjusting means 7 is preset with a value of C3 (integer value). This C3 is V
This represents the number of clocks generated by the clock clock generation means 3 during the time from the start of the activation of the CTCXO2 until its output is stabilized, and the open time adjustment means 7 is the VCTCX.
When O2 is started, the output clock of the clock clock generating means 3 is counted, and when the count value becomes equal to the set value c3, the gate means 5 is turned on and the output clock frequency dividing means 8 of the VCTCXO2 is used. The supply to the binary counter 9 is started. The dividing means 8 is supplied with the reference clock from the gate means 5, divides the reference clock to a desired frequency, and supplies it to the binary counter 9.

The binary counter 9 is an i-stage (i is an integer) counter, and outputs an output signal of the j-th stage (an integer satisfying i ≧ j) as a symbol clock, and reads / writes from the control unit 1. Is possible.

FIG. 2 is a timing chart showing an example of the operation of the binary counter 9.

In this example, j = 3, and the symbol clock is output from the third stage of the binary counter 9. Further, a 3-bit value consisting of the signal of the third stage and below represents the phase of the symbol clock with a binary number with 8-step precision, and the control unit 1 arbitrarily rewrites the third stage and below to obtain the symbol clock phase. The phase can be set to any of eight stages. Furthermore, (i-
1) The bit output represents the symbol clock count value in binary.

Returning to FIG. 1, the stopping means 10 stops and restarts the operation of the binary counter 9. This means, for example, stopping the output clock of the frequency dividing means 8 supplied to the binary counter 9. It can be realized by turning on or off. The counting means 11 counts the output clock of the clock clock generating means 3. In the start value setting means 12, the control unit 1 sets a value representing the timing at which the stop processing of the symbol clock is started. The return value setting means 13 is set by the controller 1 to a value indicating the return timing of the symbol clock, and this set value is returned to the value set in the start value setting means 12 after the symbol clock is stopped. Is a value obtained by adding a value obtained by subtracting the set value c3 of the opening time adjusting means 7 from the number of output clocks of the clock clock generating means 3 up to.

The comparison means 14 compares the set value of the start value setting means 12 with the count value of the counting means 11 and, when detecting that they match, stops the binary counter 9 by operating the stop means 10. Then, at the same time, the closing time adjusting means 6 is activated. The comparing means 15 compares the set value of the return value setting means 13 with the count value of the counting means 11, and when detecting that they match, the stop means 10 is operated to release the operation stop of the binary counter 9. At the same time, the power supply means 4 starts the supply of power to the VCTCXO 2 and also activates the opening time adjustment means 7.

Next, the operation of the first embodiment will be described with reference to the flow chart shown in FIG.

When the portable telephone terminal enters the standby state and the intermittent reception is started and the receiving operation is not necessary, the processing operation of this embodiment is started (step 200).

That is, first, the control section 1 reads the count value of the counting means 11 and sets the count value m of the counting means 11 at the time when the stop processing of the symbol clock is started to the start value setting means 1
2 is set (step 201), and then the number of output clocks of the clock clock generation means 3 at the time when the symbol clock is restored is calculated for the next reception, and the calculated value is returned to the restoration value setting means 13. Is set as the return value V (step 202). This return value V is calculated as follows.

Now, the period of the symbol clock is T1, the period of the output clock of the clock clock generating means 3 is T2,
A value that is set in the start value setting means 12 and represents the time when the binary counter 9 is stopped is m, and the number of clocks of the symbol clock in the time from the start of the processing operation to the next restoration time of the symbol clock is c1 and is released. Time adjustment means 7
Is set in advance, and the number of output clocks of the clock clock generation means 3 in the time from the startup of the VCTCXO2 to its stabilization is set to c3, and the symbol clock for receiving after the symbol clock is stopped is When the value obtained by subtracting the setting value c3 of the opening time adjusting means 7 from the number of output clocks of the clock clock generating means 3 at the time T1 × c1 until the restoration is c2, the following relational expression (1) is established.

T2 × (c2 + c3) = T1 × (c1-1) + θ2 (1) Here, θ2 is the initial phase difference between the symbol clock at the start of processing and the output clock of the clock clock generation means 3 is 0.
Time T2 × (c2 + c
3) Phase difference from these clocks after the passage of time, T2 ×
It is given by the value after the decimal point of (c2 + c3) / (T1 × (c1-1)).

From the above equation (1), c2 is obtained by the following equation.

C2 = int (T1 / T2 × (c1-1)) − c3 (2) where int (X) represents the maximum integer not exceeding X.

Therefore, the return value V set in the return value setting means 13 is given by the following equation (3).

V = m + int (T1 / T2 × (c1-1))-c3 (3) Here, the phase of the symbol clock is 8 in binary according to the 3-bit output signal of the third stage and below of the binary counter 9.
Expressed in stages (8 stages of 0 to 7 in decimal), when θ2 is represented as a value tb equal to or lower than the third stage of the binary counter 9, this corresponds to the output clock of the clock clock generation means 3. Represents the phase of the symbol clock,
It looks like this:

Tb = int (8 × θ2) (4) For example, when θ2 = 0.7, tb = 5, which is 2
The respective output bits of the value represented by a decimal number are the first stage = 1, the second stage = 0, and the third stage = 1 of the binary counter 9.
A value below the decimal point of 8 × θ2 is an error.

The calculation of the above equations (1) to (4) may be performed after the processing is started, but if the value c1 is known as a fixed value in advance, the above V,
The value of tb may be held.

In FIG. 3, next, the comparing means 14 judges whether or not the count value of the counting means 11 and the set value m of the start value setting means 12 match (step 203). By operating the means 10, the operation of the binary counter 9 is stopped, the generation of the symbol clock is stopped, and the closing time adjusting means 6 is activated (step 204).

The counting timing of the counting means 11 is as follows.
The rising edge of the output clock of the clock clock generating means 3 is used, and the timing of the comparison operation of the comparator 14 is the falling edge of the output clock of the clock clock generating means 3.

Here, the value m set by the control unit 1 in the starting value setting means 12 in step 201 is sufficient for the count value read from the counting means 11 by the control unit 1 in step 201 to reach the set value m. Is a value with which the processing of step 202 can be performed.

Next, the control section 1 reads the value of the third or lower stage of the binary counter 9 stopped at the timing of the first rising edge of the output clock of the clock clock generating means 3 to generate the clock clock generating means. The initial phase ta of the symbol clock with respect to the output clock of 3 is detected (step 205). The initial phase ta represents the initial phase of the symbol clock in eight stages in binary, like the above-described phase tb. The control unit 1 then controls the phase tb.
Is added to the phase ta, and the added value (this is the time T2 ×
(It represents the phase difference between the symbol clock after (c2 + c3) and the output clock of the clock clock generation means 3).
Is a value obtained by adding (c1-1) to the value n of the fourth stage or more of the stopped binary counter 9 below the third stage of the binary counter 9 (this is the clock of the symbol clock at time T2 × (c2 + c3)). (Representing a number) is set (step 206).

Thereafter, the control unit 1 performs a standby process so that the supplied reference clock may be stopped (step 207). When the standby process is completed (step 208), the control unit 1 stops. .

After that, when the time preset in the closing time adjusting means 6 has elapsed, the closing time adjusting time 6 turns off the gate means 5 to shut off the output clock of the VCTCXO2, and the power supply means 4 supplies power to the VCTCXO2. The supply is stopped (step 209).

Then, the comparing means 15 judges whether or not the count value of the counting means 11 and the set value V of the return value setting means 13 match (step 210). The means 7 is started, and the power supply means 4 starts the power supply to the VCTCXO2,
The stopping operation of the stopped binary counter 9 is released by the stopping means 10 (step 211).

After that, the open time adjusting means 7 determines that the count value of the output clock of the clock clock generating means 3 is the set value c3.
When it reaches, the gate means 5 is turned on and VCTCX is turned on again.
The reference clock passing from O2 through the gate means 5 is divided by the frequency dividing means 8
The frequency is divided by and the supply to the binary counter 9 is started (step 212). Then, when the supply of the output clock of the frequency dividing means 8 is restarted, the operation of the control section 1 is restored, and while the binary counter 9 is stopped, the phase indicated by the above-mentioned added value set in the third stage and below is stopped. The symbol clock is output, the symbol clock is restored with the continuity maintained (step 213), and the process is terminated (step 21).
4).

By the above operation, even if the binary counter 9 is stopped, when it restarts the operation next time, the symbol clock is output in the same phase as it was operating during the stop period. Therefore, since the bit synchronization and the frame synchronization are maintained, the mobile phone terminal can perform a normal receiving operation.

Next, the above operation will be described with reference to the timing chart shown in FIG. 1A shows an output clock of the clock clock generating means 3, and FIG. 1B shows a counting means 1.
1 is a count value, FIG. 7C is a symbol clock when the binary counter 9 continuously operates, and FIG. 7D is a count value of the fourth stage and above when the binary counter 9 continuously operates (of the symbol clock (Count value), (e) of the figure is a value of the third stage and below when the binary counter 9 operates continuously (phase of the symbol clock), (f) of FIG. ) Is the operation of the VCTCXO2, (h) is the operation of the control unit 1, (i) is the symbol clock stop period, and (j) is the fourth stage and above of the binary counter 9 during the stop period. The values (k) in the figure respectively show the values of the third stage and below during the stop period of the binary counter 9.

In FIG. 4, when the processing operation is started, the control section 1 reads the count value of the counting means 11 and sets the count value m of the counting means 11 at the time t2 when the stop processing of the symbol clock is started. It is set in the means 12.

Here, as described above, the counting means 11 outputs the output clock of the clock clock generating means 3 (see FIG. 4).
It is assumed that the rising edge of (a) is counted up, and the comparing means 14 and 15 perform the comparing operation at the falling edge of this output clock.

Then, the control unit 1 sets the number of clocks c1 of the symbol clock within the time until the reception is restored (time t6), the set value c3 of the opening time adjusting means 7, and the period T1 of the symbol clock. , C2 is calculated from the cycle T2 of the output clock of the clock clock means 3, and m + c2 is set as the return value V in the return value setting means 13.

The counting means 11 is the clock generation means 3 for the clock.
The output clocks of the
When it is detected that the count value of is equal to the set value m of the start value setting means 12 (time t2), the comparing means 14
The stop means 10 is operated to stop the operation of the binary counter 9, and the closing time adjustment means 6 is activated.

Then, the control unit 1 reads the count value of the stopped binary counter 9 and reads the count value of the third stage and below (see FIG. 4).
(K)) to the initial phase ta of the symbol clock when the binary counter 9 is stopped (here, the number of output clocks of the frequency dividing means 8 between times t1 and t2, where time t1 is the symbol clock immediately before time t2). Of the symbol clock count value n from the value at the fourth stage or higher (FIG. 4 (j)), and the value of n + c1-1 at the fourth stage or higher of the binary counter 9, Tb + below the 3rd stage
Write the value of ta, respectively.

Here, in FIG. 4 (e), tb =
7, ta = 3, and the phase is an octal number from tb + ta, so 12 in binary-coded decimal number is written in the third or lower stage. If the result of tb + ta exceeds 8, there is a carry, and the value to be set in the fourth or higher stage of the binary counter 9 is n + c1-1 + 1 = n + c1, and the value of 2 is written in the third or lower stage. .

The value of 2 written in the third and subsequent stages is
As shown in FIGS. 4D and 4E, the binary counter 9
When c1 symbol clocks are continuously generated from the value n (time t2) of the fourth stage or more of the above, the c1th symbol clock (time t5) of the symbol clock with respect to the output clock of the clock clock generating means 3 is generated. Shows the phase.

The above operation is performed by reading the count value of the counting means 11 and the count value of the binary counter 9 at time t2. Thereafter, the control unit 1 performs the process of shifting to the standby state and becomes the standby state. .

The closing time adjusting means 6 is preset with a time sufficient for the control section 1 to perform the above-described calculation and standby processing. After the set time has elapsed, the closing time adjusting means 6 is changed to the gate means. 5 is turned off, and the power supply means 4 stops the power supply to the VCTCXO 2 (time t3).

Thereafter, the comparing means 15 causes the counting means 1 to operate.
When it is detected that the count value of 1 becomes m + c2 (time t4), the comparison means 15 causes the power supply means 4 to VCT.
The power supply to the XCO 2 is started, the opening time adjusting means 7 is activated, and the stopping means 10 is operated to release the operation stop of the binary counter 9. The count value c3 of the clock clock generating means 3 preset in the opening time adjusting means 7 is set as the time during which the oscillation state is sufficiently stabilized after the power supply of the VCTCXO2.

When the opening time adjusting means 7 is activated, it starts counting the output clock of the clock clock 3, and when the counted value reaches the above-mentioned set value c3 (time t6), the gate means 5 is turned on and the binary clock is turned on. The counter 9 is supplied with the output clock of the frequency dividing means 8. As a result, the symbol clock is recovered from the binary counter 9 at the phase of the value 2 set in the third stage and below.

As described above, in this embodiment, even if the binary counter 9 is stopped, the symbol clock is restored in the same phase as when the symbol clock is continuously generated when the binary counter 9 is restored. Therefore, in the standby state, the continuity of the symbol clock can be maintained and the power supply to the VCTCXO 2 can be stopped while maintaining the bit synchronization and the frame synchronization, and the power consumption of the mobile phone terminal can be reduced.

FIG. 5 is a block diagram showing a second embodiment of the reference clock supply device according to the present invention, in which 16 is a latch means and 17 is an AND gate, and the portions corresponding to those in FIG. A duplicate description will be omitted.

In the figure, the latch means 16 holds the count value of the counting means 11 according to the control signal of the control section 1.
The AND gate 17 uses the opposite edge of the output clock of the clock clock generating means 3 when the count value is held by the latch means 16 and the control signal of the control section 1 to cause the stopping means 10 to operate.
Is operated to stop the binary counter 9.

Next, the operation of the second embodiment will be described with reference to the flowchart shown in FIG.

In the figure, when the portable telephone terminal enters the standby state and the intermittent reception is started and the receiving operation becomes unnecessary, the processing operation starts (step 200). The control unit 1 outputs a control signal and causes the latch unit 16 to hold the count value m of the counting unit 11 at this time. Further, the stop means 10 operates and the binary counter 9 stops by the reverse edge of the clock input to the counting means 11 when the latch means 16 is held and the output signal of the AND gate 17 which is the logical product of this control signal. Then, the symbol clock stops. Further, the closing time adjusting means 6 is activated by the control signal from the control section 1 which holds the latch means 16 (step 215).

After that, the control section 1 reads the value m held in the latch means 16 (step 216). Then, from the value of m, the same processing as step 202 in the flowchart of FIG. 3 showing the operation of the first embodiment is performed, and the return value V is set in the return value setting means 13. Then, as in the first embodiment, a series of processing from step 205 to step 214 is performed.

In this way, this embodiment can obtain the same effect as that of the first embodiment.

FIG. 7 is a block diagram showing a third embodiment of the reference clock supply device according to the present invention, in which 18 is an external input detecting means, 19 is a starting means, and 20 is an OR gate, which corresponds to FIG. The same reference numerals are given to the parts, and the duplicated description will be omitted.

In the figure, the external input detecting means 18 is
The presence / absence of key operation of the mobile phone terminal is detected.
When the external input detection means 18 detects an external key operation, the activation means 19 activates the opening time adjustment means 7 via the OR gate 20, and the power supply means 4 activates V.
The power supply to CTCXO2 is started, and the control unit 1
To the effect that the power supply to the VCTCXO2 has been started by the external input. The OR gate 20 is a comparison means 15.
Is combined with the output of the activation means 19, and the open time adjustment means 7 is activated by the output, and the power supply means 4 starts the power supply to the VCTCXO 2.

In this embodiment, the processing operation is also performed by the operation of an external key, and this operation will be described with reference to the flow chart shown in FIG.

In the figure, the processing of steps 201 to 210 is exactly the same as that of the first embodiment.

Count value of counting means 11 and return value setting means 1
When the comparison means 15 does not detect the coincidence of the return value V set to 3 (step 210), the presence / absence of external input detection is determined (step 217). At this time,
If no external input is detected, the process returns to step 210.

In the loop processing of steps 210 and 217, the external input is detected by the comparison means 15 until the coincidence between the count value of the counting means 11 and the return value V of the return value setting means 13 is detected (step 210). If not (step 217), the same step 2 as in the first embodiment is performed.
A series of operations from 11 to step 214 is performed.

If an external input is detected (step 217) before the comparison means 15 detects the coincidence between the count value of the counting means 11 and the return value V of the return value setting means 13 (step 210), the starting means. 19 activates the opening time adjusting means 7, causes the power supply means 4 to start supplying power to the VCTCXO 2, and also reports this to the control unit 1 (step 218).

Then, when the count value of the output clock of the clock clock generating means 3 reaches the set value c3 by the opening time adjusting means 7, the opening time adjusting means 7 turns on the gate means 5 and causes the binary counter 9 to turn on the reference clock. Are supplied (step 219). When this reference clock is supplied, the operation of the control unit 1 is restored (step 220), and when the report signal is input from the starting unit 19 when the control unit 1 is restored, the return value setting unit 13 is sent. , And the reset value V set there and the addition value of the set value c3 of the opening time adjusting means 7 are reset (step 221).

Next, the comparing means 15 compares the count value of the counting means 11 with the value set in the return value setting means 13 (step 222). If they match, the stopping means 1
0 is released to cancel the stop of the binary counter 9, the symbol clock is restored (step 223), the process is finished (step 214), and the mobile phone terminal performs the receiving operation.

Here, during the period from the activation of the opening time adjusting means 7 (step 218) to the return processing of the control section 1 (step 220), the comparing means 15 causes the counting means 1 to operate.
When a match between the count value of 1 and the set value of the return value setting means 13 is detected, the comparing means 15 outputs a report signal to the control unit 1. As described above, when the report signal is input from the comparison unit 15, even when the report signal is input from the activation unit 19, steps 221 and 222 are performed.
The operation of step 223 is performed without performing the operation of.

By performing the above processing, V
Even if an external input is detected while CTCXO2 is stopped,
The VCTCXO2 can be restored.

FIG. 9 is a block diagram showing a fourth embodiment of the reference clock supply device according to the present invention, in which reference numeral 21 is a changeover switch, and portions corresponding to those in FIG. Is omitted.

In the figure, the changeover switch 21 switches between the reference clock output from the gate means 5 and the output clock of the clock clock generation means 3 and supplies it to the control section 1.

In this embodiment, when the gate means 5 is turned off and the reference clock is stopped, the changeover switch 21 is switched to the timepiece clock generating means 3 side, the gate means 5 is turned on, and the reference clock is turned on. When supplied, the changeover switch 21 switches to the gate means 5 side and supplies this reference clock to the control unit 1.

In this embodiment, since the clock supplied to the control unit 1 does not stop, the control unit 1 can perform the processing even when the VCTCXO 2 is stopped.

FIG. 10 is a block diagram showing a fifth embodiment of the reference clock supply device according to the present invention, in which 22 is a stop time adjusting means and 23 is a release time adjusting means.
The same reference numerals are given to the portions corresponding to and the duplicate description will be omitted.

In the figure, the stop time adjusting means 22 is
When activated by the comparison means 14, the supply of power to the VCTCXO 2 by the power supply means 4 is stopped after a preset time has elapsed. The release time adjusting means 23, when activated by the comparing means 15, counts the output clock of the clock clock generating means 3 by a preset value c3 and then controls the stopping means 10 to stop the operation of the binary counter 9. To release.

Next, the operation of the fifth embodiment will be described with reference to the flow chart shown in FIG.

When the portable telephone terminal enters the standby state and the intermittent reception is started and the receiving operation is no longer required, a series of processing from step 200 to step 203 is performed as in the first embodiment.

Count value of counting means 11 and start value setting means 1
When the comparison means 14 detects a match with the set value of 2 (step 203), the comparison means 14 operates the stop means 10 to stop the binary counter 9 to stop the symbol clock and stop time adjusting means. 22 is activated (step 224). Then, a series of processing from step 205 to step 208 is performed as in the first embodiment.

After that, when the time preset in the stop time adjusting means 22 has elapsed, the stop time adjusting means 22 stops the power supply to the VCTCXO 2 by the power supply means 4 to stop the generation of the reference clock (step 22).
5) After that, when the comparison unit 15 detects that the count value of the counting unit 11 and the return value of the return value setting unit 13 match (step 210), the comparison unit 15 activates the release time adjusting unit 23. , VCTCXO by power supply means 4
2 is started, and the supply of the reference clock to the binary counter 9 is started (step 226).

Then, the control unit 1 is restored (step 22).
7) When the release time adjusting means 23 counts the output clock of the clock clock generating means 3 by the set value c3, the release time adjusting means 23 operates the stopping means 10 to release the stop of the operation of the binary counter 9, It is restored in the same phase as when the symbol clock is continuously supplied (step 228).

As described above, also in this embodiment, the same effect as that of the first embodiment can be obtained.

FIG. 12 is a block diagram showing a sixth embodiment of the reference clock supply device according to the present invention, in which parts corresponding to those in FIGS. 5 and 10 are designated by the same reference numerals.

In this embodiment, the stop time adjusting means 22 and the release time adjusting means 23 as shown in FIG. 10 are provided in the second embodiment shown in FIG.

Next, the operation of the sixth embodiment will be described with reference to the flow chart shown in FIG.

When the processing operation is started (step 20)
0), the process of step 229 is performed. This step 229 is similar to step 215 in FIG. 10 showing the operation of the second embodiment, but the part that activates the closing time adjusting means 6 is changed to activate the stop time adjusting means 22. is there. Then, as in the second embodiment,
Step 216, Step 202, Steps 205-2
A series of processing of 08 is performed.

Next, when the time preset in the stop time adjusting means 22 has elapsed, the stop time adjusting means 22 stops the power supply to the VCTCXO 2 by the power supply means 4 to stop the generation of the reference clock (step 225). ). Then, similarly to the fifth embodiment, a series of processes of step 210 and steps 226 to 228 is performed and the process is finished (step 214).

As described above, this embodiment can obtain the same effect as that of the second embodiment.

FIG. 14 is a block diagram showing a seventh embodiment of the reference clock supply device according to the present invention, in which parts corresponding to those in FIGS. 7 and 10 are designated by the same reference numerals.

This embodiment uses the stop time adjusting means 22 and the release time adjusting means 23 as shown in FIG. 10 in addition to the third embodiment shown in FIG.

Next, the operation of the seventh embodiment will be described with reference to the flow chart shown in FIG.

When the processing operation is started (step 20)
0) and steps 201 to 20 as in the fifth embodiment.
3, a series of processing of step 210 is performed through step 224, steps 205 to 208, and step 225.

Count value of counting means 11 and return value setting means 1
When the comparison means 15 does not detect the match of the return value V of 3 (step 210), the presence / absence of external input detection is determined (step 217). When the external input is not detected, the processing returns to step 210. This step 210, 21
In the loop processing by 7, the coincidence between the count value of the counting means 11 and the return value V of the return value setting means 13 is the comparing means 15
When there is no external input detection by the time detected by (step 210) (step 217), a series of processing of steps 226 to 228 and step 214 is performed as in the fifth embodiment.

If an external input is detected (step 217) before the comparison means 15 detects a match between the count value of the counting means 11 and the return value V of the return value setting means 13 (step 210), The starting means 19 starts the power supply to the VCTCXO 2 by the power supply means 4, starts the supply of the reference clock to the binary counter 9 (step 230), and the control unit 1 returns (step 220).

Then, the comparing means 15 compares the count value of the counting means 11 with the return value V of the return value setting means 13 (step 222). If they match, the comparing means 15
Activates the release time adjusting means 23 (step 23)
1). Thereafter, when the count value of the output clock of the clock clock generating means 3 reaches the set value c3 by the release time adjusting means 23, step 228 is carried out and the processing is terminated as in the fifth embodiment (step 214). ).

As described above, also in this embodiment, the third
The same effect as that of the embodiment can be obtained.

FIG. 16 is a block diagram showing an eighth embodiment of the reference clock supply device according to the present invention. The parts corresponding to those of FIGS. 9 and 10 are designated by the same reference numerals and their duplicate description will be omitted.

In this embodiment, the stop time adjusting means 22 and the release time adjusting means 23 as shown in FIG. 10 are provided in the fourth embodiment shown in FIG.

In this embodiment, when the VCTCXO2 is stopped by the power supply means 3 and the generation of the reference clock is stopped, the changeover switch 21 is switched to the clock generation means 3 for clock and the VCTCXO2 operates. If so, it switches to the VCTCXO2 side and supplies a clock to the control unit 1.

This embodiment has the same effects as the fourth embodiment.

In the embodiment described above, the power supply means 3 stops the power supply of the VCTCXO2. However, it is also possible to stop the oscillation operation of the VCTCXO2, and similarly reduce the power consumption. You can

[0121]

As described above, according to the present invention,
Bit synchronization or frame synchronization is achieved by controlling the time of the second clock generating means with very low power consumption and controlling the phase of the symbol clock formed based on the output clock of the first clock generating means. It is possible to stop the first clock generating means composed of the VCTCXO without removing the above, so that the power consumption can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of a reference clock supply device according to the present invention.

FIG. 2 is a timing chart showing an operation example of a binary counter.

FIG. 3 is a flowchart showing an operation of the first embodiment shown in FIG.

FIG. 4 is a timing chart showing the operation of the first embodiment shown in FIG.

FIG. 5 is a block diagram showing a second embodiment of the reference clock supply device according to the present invention.

6 is a flowchart showing the operation of the second embodiment shown in FIG.

FIG. 7 is a block diagram showing a third embodiment of the reference clock supply device according to the present invention.

8 is a flowchart showing the operation of the third embodiment shown in FIG.

FIG. 9 is a block diagram showing a fourth embodiment of the reference clock supply device according to the present invention.

FIG. 10 is a block diagram showing a fifth embodiment of the reference clock supply device according to the present invention.

11 is a flowchart showing the operation of the fifth embodiment shown in FIG.

FIG. 12 is a block diagram showing a sixth embodiment of the reference clock supply device according to the present invention.

13 is a flowchart showing the operation of the sixth embodiment shown in FIG.

FIG. 14 is a block diagram showing a seventh embodiment of the reference clock supply device according to the present invention.

FIG. 15 is a flowchart showing an operation of the seventh embodiment shown in FIG.

FIG. 16 is a block diagram showing an eighth embodiment of the reference clock supply device according to the present invention.

FIG. 17 is a configuration diagram of a control channel.

FIG. 18 is a diagram showing an operation of a mobile phone terminal during communication.

FIG. 19 is a block diagram showing a configuration example of a digital mobile phone terminal.

[Explanation of symbols]

 1 Control Unit 2 Clock Generating Means (VCTCXO) 3 Clock Clock Generating Means 4 Power Supply Means 5 Gate Means 6 Closing Time Adjusting Means 7 Opening Time Adjusting Means 8 Frequency Dividing Means 9 Binary Counters 10 Stopping Means 11 Counting Means 12 Start Value Setting Means 13 Return value setting means 14, 15 Comparison means 16 Latch means 18 External input detecting means 19 Starting means 21 Changeover switch 22 Stop time adjusting means 23 Release time adjusting means

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Satoshi Kawai, 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Stock company Hitachi Image Information Systems (72) Inventor Yasuaki Takahara 292, Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Ceremony company Hitachi Ltd. multimedia system development headquarters

Claims (9)

[Claims] 1. A reference clock supply device for generating a reference clock, which is used in a mobile phone terminal or the like, comprising: a control unit including a microprocessor for controlling and calculating the entire operation; First clock generating means for generating a clock, second clock generating means for generating a clock of a second frequency, and power supply to the first clock generating means, or power supply for stopping / starting the operation Means and gate means for closing or opening the output clock of the first clock generating means and outputting it as a reference clock; and, when activated, closing the gate means after a preset time and supplying the power. Means for supplying power to the first clock generating means or closing time adjusting means for stopping the operation of the first clock generating means; An open time adjusting means for opening the gate means after counting the output clock of the lock generating means by a preset value, and a frequency dividing means for dividing the reference clock from the gate means to a desired frequency, i (where i is an integer) stages, the output clock of the frequency dividing means is supplied, and the symbol clock is output from the j-th stage (where j is an integer satisfying i ≧ j), and the control section A binary counter capable of reading and writing a count value, a stopping means for stopping or canceling the operation of the binary counter, a counting means for counting the number of output clocks of the second clock generating means, and a stop processing for the symbol clock. The count value of the counting means at the start time is set to the start value setting means set by the control unit, and the set value of the start value setting means is set to the reset time of the symbol clock. A return value setting means set by the control unit using a value obtained by adding a value obtained by subtracting a count value preset in the open time adjusting means from the number of output clocks of the second clock generating means as a return value. And comparing the set value of the start value setting means with the count value of the counting means, and when it is detected that the two match, the stopping means stops the operation of the binary counter and the closing time. The first comparing means for activating the adjusting means compares the return value of the return value setting means with the count value of the counting means. Release the operation stop of the binary counter,
And a second comparison means for starting power supply or operation to the first clock generation means by the power supply means and activating the open time adjustment means, and the start value setting by the first comparison means. When a match between the set value of the means and the count value of the counting means is detected, the control section causes the binary counter that has stopped the phase difference between the output clock of the second clock generating means and the symbol clock. The time from the j-th stage or lower to detect the coincidence between the set value of the return value setting means and the count value of the counting means by the second comparing means, and the opening time adjusting means. The phase of the symbol clock after the time when the counting ends is added and set in the binary counter, and when the time preset in the closing time adjusting means elapses, the gate means is closed. And the power supply The power supply means stops the power supply or operation to the first clock generation means to stop the supply of the reference clock, and the second comparison means causes the return value of the return value setting means and the count value to be counted. When the coincidence with the count value of the means is detected, the power supply means starts power supply or operation to the first clock generation means, and the second time is set to the open time adjusting means by a value set in advance. When the output clock of the clock generating means is counted, the gate means is opened to supply the reference clock to the binary counter, and the symbol clock is started to be output at the phase set in the binary counter. Reference clock supply device. 2. A reference clock supply device for generating a reference clock used in a mobile telephone terminal device, etc., and a control section comprising a microprocessor or the like for controlling and operating the entire operation, and a first frequency. Clock generating means for generating the clock, second clock generating means for generating the clock of the second frequency, and power supply for the first clock generating means, or power supply for stopping and starting the operation. Means and gate means for closing or opening the output clock of the first clock generating means and outputting it as a reference clock; and, when activated, closing the gate means after a preset time and supplying the power. Closing time adjusting means for stopping power supply or operation to the first clock generating means by means, and the second clock when activated. An open time adjusting means for opening the gate means after counting the output clock of the clock generating means by a preset value, and a dividing means for dividing the reference clock from the gate means to a desired frequency. , I (where i is an integer) stages, the output clock of the frequency dividing means is supplied, and the symbol clock is output from the j-th stage (where j is an integer satisfying i ≧ j), and the control unit A binary counter capable of reading and writing a count value by means of a counter, a stopping means for stopping or canceling the operation of the binary counter, a counting means for counting the number of output clocks of the second clock generating means, and a control from the control section. Latch means for holding the count value of the counting means by a signal, and the number of output clocks of the second clock generating means by the value held in the latch means until the symbol clock recovery time. A value obtained by adding a value obtained by subtracting a count value preset in the opening time adjusting means from the return value setting means set by the control unit, and the return value of the return value setting means. And the count value of the counting means are compared, and when it is detected that they match each other, the stop means releases the operation stop of the binary counter,
When a control signal is sent from the control unit, the power supply means supplies power to the first clock generation means or starts operation of the first clock generation means, and second comparison means for activating the opening time adjustment means. , The closing time adjusting means is activated, the stopping means stops the binary counter at the edge of the output clock of the second clock generating means, and the output clock of the second clock generating means and the symbol clock The time when the phase difference is detected from the value of the jth stage or less of the binary counter, and the second comparing means detects the coincidence between the return value of the return value setting means and the count value of the counting means. And the time at which the counting of the opening time adjusting means ends is added, the phase of the symbol clock after a time is calculated and set in the binary counter, and is preset in the closing time adjusting means. After a certain period of time, the gate means is closed and the power supply means
The power supply to the first clock generating means or the operation is stopped, the supply of the reference clock is stopped, and the return value of the return value setting means and the count value of the counting means by the second comparing means. Is detected, the power supply means starts the power supply or operation to the first clock generation means, and the open time adjusting means operates the second clock by the preset count value. When counting the output clock of the generating means, the gate means is opened to supply the reference clock to the binary counter, and the symbol clock is started to be output at the phase set in the binary counter. Clock supply device. 3. The external input detecting means for detecting an input from the outside, the starting means for outputting a starting signal when the input is detected by the external input detecting means, and the starting means. And an output signal from the second comparing means, the opening time adjusting means and an OR gate for outputting to the power supply means are provided, and the first clock generating means is stopped by the power supply means. In this case, when the external input detection unit detects an external input, the activation unit reports to the control unit, activates the open time adjustment unit, and causes the power supply unit to supply the first signal. When power supply or operation to the clock generation means is started, and when the counting of the opening time adjusting means is finished, the gate means is opened to supply the reference clock to the binary counter. Then, the control section receives a report from the starting means, and the second comparing means detects the coincidence between the return value of the return value setting means and the count value of the counting means. If not, the return value setting means resets a value obtained by adding the count value preset in the open time adjusting means to the return value, and the return value setting means in the second comparing means. When the coincidence between the return value and the count value of the counting means is detected, the stopping means releases the operation stop of the binary counter and restores the symbol clock. 4. The method according to claim 1, 2 or 3, wherein one of the reference clock output from the gate means and the output clock of the second clock generating means is selected and supplied to the control section. A changeover switch, wherein the changeover switch selects the output clock of the second clock generating means when the gate means is closed, and the changeover switch when the gate means is open Selects the reference clock output from the gate means. 5. A reference clock supply device for generating a reference clock used in a mobile phone terminal device and the like, comprising: a control unit composed of a microprocessor or the like for controlling and operating the entire operation; First clock generating means for generating a clock, second clock generating means for generating a clock of a second frequency, and power supply to the first clock generating means, or power supply for stopping / starting the operation Means for stopping power supply to the first clock generating means or stopping operation by the power supply means after a preset time when activated, and the first clock generating means Frequency dividing means for dividing the output clock of (1) to a desired frequency, and i (where i is an integer) stages, and the output clock of the frequency dividing means is supplied, (However, j is an integer that satisfies i ≧ j) A binary clock from which the symbol clock is output from the stage and the count value can be read and written by the control unit, and a stop unit that stops or cancels the operation of the binary counter, When activated, the output clock of the second clock generating means is counted by a preset value, and then the stop time adjusting means releases the stop of the binary counter, and the second clock generating means. Counting means for counting the number of output clocks of the means, start value setting means for setting the count value of the counting means at the time when the stop processing of the symbol clock is started by the control portion, and the start value setting means The set value is the count value preset in the release time adjusting means from the number of output clocks of the second clock generating means until the symbol clock recovery time. The value obtained by adding the subtracted values is used as the return value, and the return value setting means set by the control unit is compared with the set value of the start value setting means and the count value of the counting means, and the two values match. When detecting the, the stop means stops the operation of the binary counter and activates the stop time adjusting means, the first comparing means, the return value of the return value setting means and the count value of the counting means. When a comparison is made and it is detected that the two coincide with each other, the power supply means starts power supply or operation to the first clock generation means, and the second comparison means starts the release time adjustment means. When the first comparison means detects a match between the set value of the start value setting means and the count value of the counting means, the control section
The phase difference between the output clock of the second clock generating means and the symbol clock is detected from the value of the jth stage or less of the stopped binary counter, and the return value of the return value setting means is detected by the second comparing means. And the count value of the counting means is detected, and the time when the counting of the release time adjusting means is finished is added to calculate the phase of the symbol clock and the binary counter is calculated. When the preset time is set in the stop time adjusting means, the power supply means stops the power supply or the operation to the first clock generating means, and the supply of the reference clock is stopped. When the second comparing means detects a match between the return value of the return value setting means and the count value of the counting means, the power supply means supplies power to the first clock generating means or Motion When the output clock of the second clock generating means is started and counted by a value preset in the release time adjusting means, the stop of the operation of the binary counter is released and the binary counter is set. A reference clock supply device characterized by starting output of the symbol clock at the above-mentioned phase. 6. A reference clock supply device for generating a reference clock used in a mobile phone terminal device and the like, comprising: a control unit including a microprocessor for controlling and calculating the entire operation; First clock generating means for generating a clock, second clock generating means for generating a clock of a second frequency, and power supply to the first clock generating means, or power supply for stopping / starting the operation Means for stopping power supply or operation of the first clock generation means by the power supply means after a preset time when activated, and a stop time adjustment means of the first clock generation means. An output clock of the frequency dividing means is supplied from the frequency dividing means for dividing the output clock to a desired frequency and i (where i is an integer) stages, and j (Where j is an integer that satisfies i ≧ j), the symbol clock is output from the (third) stage, a binary counter capable of reading and writing the count value by the control unit, a stop unit for stopping or canceling the operation of the binary counter, and a starter Then, after the output clock of the second clock generating means is counted by a preset value, a canceling time adjusting means for canceling the stop of the binary counter by the stopping means, and the second clock generating means. Counting means for counting the number of output clocks, latch means for holding the count value of the counting means in response to a control signal from the control part, and the value held in the latch means for the return time of the symbol clock. A value obtained by adding a value obtained by subtracting a value preset in the release time adjusting means from the number of output clocks of the second clock generating means is used as a return value, The return value setting means set by the control unit is compared with the return value of the return value setting means and the count value of the counting means, and when it is detected that they match each other, the power supply means supplies the first value. And a comparison means for starting power supply or operation to the clock generation means of No. 1 and activating the release time adjusting means, and when the control signal is sent from the control unit, the stop time adjusting means is activated, The stopping means stops the binary counter at the edge of the output clock of the second clock generating means, and stops the phase difference between the output clock of the second clock generating means and the symbol clock. Detecting from the value below the stage, the time when the comparison means detects the coincidence between the return value of the return value setting means and the count value of the counting means, and the counting of the release time adjusting means ends. The phase of the symbol clock after a time obtained by adding the time is calculated and set in the binary counter, and when the time preset in the stop time adjusting means elapses, the power supply means causes the first When the power supply or operation to the clock generation means is stopped, the supply of the reference clock is stopped, and the comparison means detects a match between the return value of the return value setting means and the count value of the counting means. When the power supply means starts power supply or operation to the first clock generation means, and the output clock of the second clock generation means is counted by a count value preset in the release time adjustment means, A reference characterized in that the stop of the operation of the binary counter is released by the stop means, and the output of the symbol clock is started at the phase set in the binary counter. Clock supply device. 7. The external input detecting means according to claim 5 or 6, for detecting an input from the outside, the starting means for outputting a starting signal when the input is detected by the external input detecting means, and the starting means. And an output signal from the second comparison means are input and output to the power supply means, and the external input is provided when the first clock generation means is stopped by the power supply means. When the detection unit detects an input from the outside, the activation unit reports to the control unit, and at the same time, the power supply unit starts power supply or operation to the first clock generation unit, and the binary When the supply of the reference clock to the counter is restarted and the second comparison means detects a match between the return value of the return value setting means and the count value of the counting means, the release time is released. When the adjusting means is activated and the counting of the output clock of the second clock generating means by the releasing time adjusting means is completed, the stop of the operation of the binary counter is released by the stopping means, and the binary counter is set. A reference clock supply device, wherein output of the symbol clock is started in the above phase. 8. The method according to claim 5, wherein one of a reference clock output from the first clock generating means and an output clock of the second clock generating means is selected. A changeover switch for supplying to the control unit is provided, and when the first clock generation means is stopped,
When the changeover switch selects the output clock of the second clock generating means and the first clock generating means is operating,
The reference clock supply device, wherein the changeover switch selects the reference clock output from the first clock generating means. 9. A mobile terminal device comprising the reference clock supply device according to any one of claims 1 to 8.