JPH0252465B2 - - Google Patents

Info

Publication number
JPH0252465B2
JPH0252465B2 JP59124678A JP12467884A JPH0252465B2 JP H0252465 B2 JPH0252465 B2 JP H0252465B2 JP 59124678 A JP59124678 A JP 59124678A JP 12467884 A JP12467884 A JP 12467884A JP H0252465 B2 JPH0252465 B2 JP H0252465B2
Authority
JP
Japan
Prior art keywords
frequency
pll
oscillator
phase
reception
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59124678A
Other languages
Japanese (ja)
Other versions
JPS613538A (en
Inventor
Masanobu Hasegawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yaesu Musen Co Ltd
Original Assignee
Yaesu Musen Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yaesu Musen Co Ltd filed Critical Yaesu Musen Co Ltd
Priority to JP59124678A priority Critical patent/JPS613538A/en
Publication of JPS613538A publication Critical patent/JPS613538A/en
Publication of JPH0252465B2 publication Critical patent/JPH0252465B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04WWIRELESS COMMUNICATION NETWORKS
    • H04W52/00Power management, e.g. TPC [Transmission Power Control], power saving or power classes
    • H04W52/02Power saving arrangements
    • H04W52/0209Power saving arrangements in terminal devices
    • H04W52/0261Power saving arrangements in terminal devices managing power supply demand, e.g. depending on battery level
    • H04W52/0274Power saving arrangements in terminal devices managing power supply demand, e.g. depending on battery level by switching on or off the equipment or parts thereof
    • H04W52/028Power saving arrangements in terminal devices managing power supply demand, e.g. depending on battery level by switching on or off the equipment or parts thereof switching on or off only a part of the equipment circuit blocks
    • H04W52/0283Power saving arrangements in terminal devices managing power supply demand, e.g. depending on battery level by switching on or off the equipment or parts thereof switching on or off only a part of the equipment circuit blocks with sequential power up or power down of successive circuit blocks, e.g. switching on the local oscillator before RF or mixer stages
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00Reducing energy consumption in communication networks
    • Y02D30/70Reducing energy consumption in communication networks in wireless communication networks

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Superheterodyne Receivers (AREA)

Abstract

PURPOSE:To stop the supply for unnecessary circuits such as a voice circuit and to reduce the current consumption of power by stopping a PLL control oscillating circuit requiring comparatively much power supply current comsumption at the standby reception where reception state is continued for a long time. CONSTITUTION:While a PLL oscillating circuit is in operation, an output frequency fO of a VCO11 is frequency-divided by a prescaler 12, variable frequency division is applied further by a programmable frequency divider 13, the phase is compared with a reference frequency fr at a phase comparator 14 and its phase difference output locks the oscillating frequency of the VCO11 as a control DC voltage. The operation of the PLL circuit 1 is stopped at the standby reception state, an output fR of a fixed frequency oscillator 15 exclusive use of standby reception is used directly or used while being multiplied at a multiplier 18, the frequency fR of the oscillator 15 is frequency-divided by a frequency divider 17 at the operation of PLL as the use of the reference frequency fr. The power supply is switched by a PLL power switch S2 in interlocking with fO and fO'.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は電燈電源の利用できない、携帯用・車
載用および辺地における、多目的受信機であつ
て、使用時以外は連絡用・非常呼出用等の待受信
用に常時受信待期状態を保持する必要のある受信
機に適用して電源電池の消耗を軽減するにある。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention is a multi-purpose receiver for portable, vehicle-mounted, and remote areas where electric light power is not available, and is used for communication, emergency calls, etc. when not in use. The purpose of this invention is to reduce the consumption of the power supply battery by applying it to a receiver that must always maintain a reception standby state for reception and reception.

〔従来技術と問題点〕[Conventional technology and problems]

電燈電源の利用できない移動用や辺地で使用す
る受信機では電源として乾電池を用いることが多
く、運用可能時間は電池の寿命により左右される
が、特に携帯用では重量と体積の点からなるべく
小形の電池の使用が望まれるので、消費電流(す
なわち消費電力)を極力小さく設計する必要があ
るが、受信機の性能維持に必要な電流は確保しな
ければならないので、連絡用や非常呼出を待期す
る待受信時には例えばスケルチ制御電圧を利用し
て、受信波検出段以後の音声増幅回路の動作を停
止して消費電流を節減する手段は従来から実行さ
れている。しかしながら、最も電流を消費する音
声出力段は通常B級動作であるため無入力時にお
ける消費電流は小さいので、音声出力段の動作を
停止したことによる節減効果は必ずしも十分とは
いえない実情であつた。
Receivers for mobile use or for use in remote areas where electric light power is not available often use dry batteries as a power source, and the operating time depends on the battery life, but especially for portable use, it is recommended to use a small size as much as possible in terms of weight and volume. Since the use of batteries is desired, the current consumption (i.e. power consumption) must be designed to be as small as possible, but the current required to maintain the performance of the receiver must be secured, so it is not possible to use batteries for communication or emergency calls. Conventionally, means have been implemented to reduce current consumption by stopping the operation of the audio amplification circuit after the received wave detection stage by using, for example, a squelch control voltage during standby and reception. However, since the audio output stage that consumes the most current is normally in Class B operation, the current consumption is small when there is no input, so the savings effect of stopping the operation of the audio output stage is not necessarily sufficient. Ta.

これを改善した方式としては、先に本出願人の
出願に係わる特願昭和59年第90444号「待受信時
の消費電流低減方式」がある。該発明の概要は(1)
フエーズロツクドループ制御の局部発振器にて受
信周波数を設定する形式の無線受信機において、
特定周波数の電波の待受信状態においてはフエー
ズロツクドループ回路の動作を停止し、代りに待
受信専用の固定周波数発振器を使用するよう構成
したことを特徴とする待受信時の消費電流低減方
式であり、かつ実施に際しては(2)フエーズロツク
ドループ制御の局部発振器出力と水晶制御局部発
振器出力とを並列接続し、「通常受信」時には水
晶制御発振器の電源を切り、「待受信」時にはフ
エーズロツクドループ発振器の電源を切る構成
と、(3)フエーズロツクドループ制御の局部発振器
回路内の局部発振器を構成する水晶制御発振器の
出力を「待受信」時にはフエーズロツクドループ
制御の局部発振器出力と切換えて受信回路のミク
サに注入し、かつ、該水晶制御発振器を除くフエ
ーズロツクドループ制御の局部発振回路の電源を
切る構成と、があるが、前記(2)においては待受信
用の水晶制御発振器を別に設ける必要があり、(3)
においては周波数構成の都合で必ずしも成立しな
い場合があり、いま一歩の進歩が望ましかつた。
As a system that improves this, there is a Japanese Patent Application No. 90444 filed in 1982, ``Method for reducing current consumption during standby'', which was previously filed by the present applicant. The outline of the invention is (1)
In a wireless receiver that sets the reception frequency using a phase-locked loop controlled local oscillator,
A method for reducing current consumption during standby, characterized by a configuration in which the operation of the phase-locked loop circuit is stopped during standby for reception of radio waves of a specific frequency, and a fixed frequency oscillator exclusively for standby and reception is used instead. (2) Connect the phase-locked loop control local oscillator output and the crystal-controlled local oscillator output in parallel, turn off the power to the crystal-controlled oscillator during "normal reception", and turn off the phase-locked oscillator during "standby reception". (3) The output of the crystal controlled oscillator that constitutes the local oscillator in the phase-locked loop control local oscillator circuit is configured to turn off the power to the locked loop oscillator. There is a configuration in which the power is switched to the mixer of the receiving circuit, and the power is turned off to the local oscillation circuit under phase-locked loop control except for the crystal-controlled oscillator. However, in (2) above, the crystal control for standby reception is It is necessary to provide a separate oscillator, (3)
In some cases, this may not necessarily be true due to the frequency configuration, so it would be desirable to make further progress.

〔発明の目的〕[Purpose of the invention]

この発明は待受信時における、従来技術による
消費電流(消費電力)の節減効果をさらに拡大す
ると共に、そのための受信性能低下を伴わない消
費電力低減方式を得るにある。
The present invention aims to further expand the effect of reducing current consumption (power consumption) achieved by the prior art during standby reception, and to obtain a power consumption reduction method that does not involve deterioration of reception performance.

〔発明の概要〕[Summary of the invention]

この発明は第1図に例示するように、フエーズ
ロツクドループ(以下にはPLLと略記する)制
御の局部発振器にて受信周波数を設定する形式の
無線受信機において、特定周波数の電波の待受信
状態においてはPLL回路の動作を停止し、代り
に待受信専用の固定周波数発振器を直接または逓
倍して使用すると共に、PLLの動作時には該固
定周波数発振器の周波数を分周して基準周波数と
して用いる構成としたことを特徴とする待受信時
の消費電力低減方式である。
As illustrated in FIG. 1, the present invention is a wireless receiver in which the reception frequency is set by a local oscillator controlled by phase-locked loop (hereinafter abbreviated as PLL), in which the reception and reception of radio waves of a specific frequency is performed. In this state, the operation of the PLL circuit is stopped and a fixed frequency oscillator for standby reception is used directly or multiplied instead, and when the PLL is operating, the frequency of the fixed frequency oscillator is divided and used as the reference frequency. This is a method for reducing power consumption during standby and reception.

一般に受信機に局部発振器として使用される
PLL回路には「ミクサ方式」と「プリスケーラ」
方式とがあり、前記特願昭和59年第90444号の場
合はミクサ方式であつた。ミクサ方式は発振周波
数設定の自由度が大きいため、ゼネラルカバレー
ジ受信機等に多く用いられるが、複雑なスプリア
ス周波数が発生し易い問題点がある。他方のプリ
スケーラ方式はループ周波数をプリスケーラによ
り単に分周するだけであつて高周波を考慮するだ
けで良く、プリスケーラ用ICの進歩により高い
動作周波数のものが安く入手できるようになつた
ので、ステツプ周波数で運用されるFM受信機等
ではこのプリスケーラ方式が主流となつている。
プリスケーラ方式PLLの基本回路は第2図に
示すように、VCO(電圧制御発振器)21の発振
周波数0をプリスケーラ(分周器)22で分周し
て、プログラマブル分周器23で可変分周して、
位相比較器24で基準発振器25の周波数rと位
相比較を行い、その位相差に相当するパルス出力
をLPF26を通して制御直流電圧としてVCO2
1の発振周波数をロツクする構成である。その結
果としてVCO21の発振周波数0は基準周波数r
の整数倍となるが、通信チヤンネルの周波数間隔
は数10kHzないし数100kHzであり、水晶発振器に
は低過ぎるので、実際はもつと高い周波数Rで発
振し、これを適宜分周して所要のrを得るように
している。
Commonly used as a local oscillator in receivers
PLL circuit uses "mixer method" and "prescaler"
In the case of the above-mentioned patent application No. 90444 of 1982, it was a mixer method. The mixer method has a large degree of freedom in setting the oscillation frequency, so it is often used in general coverage receivers and the like, but it has the problem that complex spurious frequencies are likely to occur. The other prescaler method simply divides the loop frequency using a prescaler and only needs to take high frequencies into consideration.As prescaler ICs have advanced, high operating frequencies have become available at low prices, so step frequencies can be This prescaler method is the mainstream in FM receivers and the like.
As shown in Figure 2, the basic circuit 1 of the prescaler type PLL divides the oscillation frequency 0 of a VCO (voltage controlled oscillator) 21 with a prescaler (frequency divider) 22, and then performs variable frequency division with a programmable frequency divider 23. do,
The phase comparator 24 compares the phase with the frequency r of the reference oscillator 25, and the pulse output corresponding to the phase difference is sent to the VCO 2 as a control DC voltage through the LPF 26.
This configuration locks the oscillation frequency of 1. As a result, the oscillation frequency 0 of VCO21 is the reference frequency r
However, the frequency interval of communication channels is several 10 kHz to several 100 kHz, which is too low for a crystal oscillator, so in reality it oscillates at a high frequency R , which is divided appropriately to obtain the required r . I'm trying to get it.

本発明はPLL発振回路の出力0rの倍数であ
ることに着目し、第1図のVCO11の出力周波
0をプリスケーラ12で分周して、プログラマ
ブル分周器13で可変分周して、位相比較器14
で基準周波数rと位相比較を行い、その位相差に
相当するパルス出力をLPF46を通して制御直
流電圧としてVCO11の発振周波数をロツクす
るPLL発振回路において、待受信状態において
はPLL回路の動作を停止し、代りに待受信専
用の固定周波数発振器15の出力Rを直接または
逓倍器18にて逓倍して使用すると共に、PLL
の動作時には該発振器15の周波数Rを分周器1
7にて分周して基準周波数rとして用いる構成と
したものである。ここで待受信用として基準周波
rを逓倍して用いれば全受信チヤンネルの任意
チヤンネルで待受信ができるが、分周前のRでは
特定チヤンネルに限定されるものである。しかし
ながら、分周や逓倍の段数はなるべく少ないこと
が望ましいので、特定周波数のみの待受信に対し
ては分周を要しないRを設定することが望まし
い。
The present invention focuses on the fact that the output 0 of the PLL oscillation circuit is a multiple of r , and divides the output frequency 0 of the VCO 11 shown in FIG. Phase comparator 14
In the PLL oscillator circuit, which performs a phase comparison with the reference frequency r and uses the pulse output corresponding to the phase difference as a control DC voltage through the LPF 46 to lock the oscillation frequency of the VCO 11, the operation of the PLL circuit 1 is stopped in the standby state. , instead, the output R of the fixed frequency oscillator 15 exclusively for standby reception is used directly or multiplied by the multiplier 18, and the PLL
When the oscillator 15 operates, the frequency R of the oscillator 15 is divided by the frequency divider 1.
The frequency is divided by 7 and used as the reference frequency r . If the reference frequency r is multiplied and used for standby reception, standby reception can be performed on any channel of all reception channels, but R before frequency division is limited to a specific channel. However, since it is desirable that the number of stages of frequency division and multiplication be as small as possible, it is desirable to set R that does not require frequency division for standby and reception of only a specific frequency.

〔発明の実施例〕[Embodiments of the invention]

次に本発明の好適な実施例としてパーソナル無
線通信機への適用につき述べる。
Next, as a preferred embodiment of the present invention, application to a personal wireless communication device will be described.

パーソナル無線のチヤンネル周波数は903.0125
〜904.9875MHz間を25kHz間隔で80のチヤンネル
が設定され、そのうちの903.0125MHzを制御チヤ
ンネル、その他の79チヤンネルを通話チヤンネル
とし、呼出しは必ず制御チヤンネルにより行い、
通話は79チヤンネル中の空チヤンネルに自動移行
して行うものである。従つて、待受信周波数′0
は903.0125MHzのみでよく、スプリアスを考慮し
て第1中間周波数を58.1125MHzとすると、上側
局部発振周波数は961.125MHzとなるから、仮に
これを15分周すると64.075MHzとなり、さらに
2563分周すると25kHzとなるから、第1図におい
て固定発振器15の発振周波数Rを64.075MHzと
し、逓倍器18にて15逓倍して′0=961.125MHz
を得、また64.075MHzを2563分周してPLLの基準
周波数r=25kHzを得ることができるものである。
これによりPLL発振器出力周波数0は25kHzステ
ツプで得られるから、プログラマブル分周器13
の設定次第で25kHz間隔のチヤンネル受信が可能
であり、待受信時には′0に切替えて制御チヤン
ネルを受信することが出来るものである。なお0
と′0を切替えるスイツチ(電子スイツチ回路で
もよい)S1と連動してPLL電源スイツチS2によ
りPLL回路の電源VBを切断して電力消費を低
減し得るものである。
Personal radio channel frequency is 903.0125
80 channels are set at 25kHz intervals between ~904.9875MHz, of which 903.0125MHz is the control channel and the other 79 channels are call channels, and calls are always made through the control channel.
Calls are automatically transferred to an empty channel among 79 channels. Therefore, the standby reception frequency′ 0
needs to be only 903.0125MHz, and if the first intermediate frequency is set to 58.1125MHz considering spurious, the upper local oscillation frequency will be 961.125MHz, so if this is divided by 15, it will be 64.075MHz, and
Dividing the frequency by 2563 gives 25kHz, so in Figure 1, the oscillation frequency R of the fixed oscillator 15 is set to 64.075MHz, and the multiplier 18 multiplies it by 15 to get ' 0 = 961.125MHz.
By dividing 64.075MHz by 2563, the PLL reference frequency r = 25kHz can be obtained.
As a result, the PLL oscillator output frequency 0 can be obtained in 25kHz steps, so the programmable frequency divider 13
Depending on the settings, it is possible to receive channels at 25 kHz intervals, and when in standby mode, it is possible to switch to '0' and receive control channels. Furthermore, 0
The power consumption can be reduced by cutting off the power supply VB of the PLL circuit 1 by means of the PLL power switch S2 in conjunction with the switch S1 (which may be an electronic switch circuit) that switches between the two states.

〔発明の効果〕〔Effect of the invention〕

この発明は発明の概要と実施例の項で詳記した
ように、長時間受信状態を継続する待受信時に比
較的電源電流消費の多いPLL制御発振回路を停
止することにより、前記の音声回路等の不要回路
の停止と相加して電源電流消費(従つて電源電力
消費)を通常受信時の半分以下に低減し得て、特
に乾電池使用の携帯形受信機に適用して効果が大
きいものである。
As described in detail in the Summary of the Invention and Embodiments, this invention enables the above-mentioned audio circuit, In addition to stopping unnecessary circuits, the power supply current consumption (and therefore power supply power consumption) can be reduced to less than half of normal reception, and is particularly effective when applied to portable receivers that use dry batteries. be.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明およびその実施例の構成図、第
2図はPLL回路基本構成図である。 ……PLL回路、11,21……VCO、
12,22……プリスケーラ、13,23……プ
ログラマブル分周器、14,24……位相比較
器、15,25……固定発振器、16,26……
LPF、17……分周器、18……逓倍器、S1
S2……切替スイツチ。
FIG. 1 is a block diagram of the present invention and its embodiments, and FIG. 2 is a basic block diagram of a PLL circuit. 1 , 2 ...PLL circuit, 11, 21...VCO,
12, 22... Prescaler, 13, 23... Programmable frequency divider, 14, 24... Phase comparator, 15, 25... Fixed oscillator, 16, 26...
LPF, 17... Frequency divider, 18... Multiplier, S 1 ,
S 2 ...Switch.

Claims (1)

【特許請求の範囲】[Claims] 1 フエーズロツクドループ制御の局部発振器に
て受信周波数を設定する形式の無線受信機におい
て、特定周波数の電波の待受信状態においてはフ
エーズロツクドループ回路の動作を停止し、代り
に待受信専用の固定周波数発振器を直接または逓
倍して使用すると共に、フエーズロツクドループ
の動作時には該固定周波数発振器の周波数を分周
して基準周波数として用いる構成としたことを特
徴とする待受信時の消費電力低減方式。
1. In a wireless receiver of the type in which the reception frequency is set by a local oscillator controlled by a phase-locked loop, when in the standby state of radio waves of a specific frequency, the operation of the phase-locked loop circuit is stopped, and instead, the operation of the phase-locked loop circuit is stopped, and instead Reducing power consumption during standby reception, characterized by using a fixed frequency oscillator directly or by multiplying it, and at the same time dividing the frequency of the fixed frequency oscillator and using it as a reference frequency during phase-locked loop operation. method.
JP59124678A 1984-06-18 1984-06-18 Power consumption reducing system at standby reception Granted JPS613538A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59124678A JPS613538A (en) 1984-06-18 1984-06-18 Power consumption reducing system at standby reception

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59124678A JPS613538A (en) 1984-06-18 1984-06-18 Power consumption reducing system at standby reception

Publications (2)

Publication Number Publication Date
JPS613538A JPS613538A (en) 1986-01-09
JPH0252465B2 true JPH0252465B2 (en) 1990-11-13

Family

ID=14891358

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59124678A Granted JPS613538A (en) 1984-06-18 1984-06-18 Power consumption reducing system at standby reception

Country Status (1)

Country Link
JP (1) JPS613538A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0731569A2 (en) * 1993-03-10 1996-09-11 National Semiconductor Corporation Radio frequency telecommunications transceiver

Also Published As

Publication number Publication date
JPS613538A (en) 1986-01-09

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