JPH0555950A - Local oscillation circuit employing direct digital synthesizer - Google Patents

Abstract

PURPOSE:To reduce power consumption in the standby state of a mobile communication terminal equipment employing a DDS (direct digital synthesizer) for the local oscillation circuit. CONSTITUTION:In the local oscillation circuit of PLL configuration using an output of the DDS for a reference frequency of a phase comparator, a 1st variable frequency divider 7 is interposed to a pre-stage of the phase comparator 4, a 2nd variable frequency divider 9 is interposed between the DDS 8 and a reference oscillator 10, and the circuit is provided with a control section 11 controlling the frequency division ratio of the 1st and 2nd variable frequency dividers 7, 9. The 2nd variable frequency divider 9 is used to reduce the input frequency of the DDS 8 in the standby state of a communication terminal equipment to reduce the current consumption of the DDS and the frequency division ratio of the 1st variable frequency divider 7 is controlled simultaneously to allow the phase comparator to compare the phases.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mobile communication terminal used in a TDMA system, and more particularly to a local oscillator circuit using DDS.

[0002]

2. Description of the Related Art A TDMA type mobile communication terminal is shown in FIG.
As shown in (4), in the communication channel (channel), the frequency is switched for about 6 ms during the idle period 23 after the reception slot 21 and the transmission slot 22 to monitor the adjacent cell, but this frequency is switched. Conventionally, a high-speed frequency switching synthesizer using DDS has been proposed. FIG. 2 is a block diagram of a local oscillation circuit using this DDS, which includes a VCO (voltage control oscillator) 1, a buffer amplifier 2, a fixed frequency divider 3, a phase comparator 4, a CP (charge pump) 5, and an LPF. (Low-pass filter)
6 forms a PLL loop. In DDS8, CH
The reference frequency corresponding to the carrier frequency is digitally created based on the fixed clock frequency from the reference oscillator 10, and is input to the phase comparator 4 of the PLL loop.

In this configuration, the output of the VCO 1 is frequency-divided by the fixed frequency divider 3 and input to the phase comparator 4, and the DDS 8
The phase frequency is compared with the reference frequency from 1 to drive CP5 and control the voltage value of VCO1 through LPF6 to generate the carrier frequency. Since it can also be set high comparison frequency of the phase comparator 4 in the channel switching of 25KH _Z interval by changing the reference frequency in accordance with the carrier frequency, thereby enabling high-speed frequency switching.

[0004]

DISCLOSURE OF THE INVENTION The conventional DDS described above
In the local oscillation circuit using the, the high frequency reference frequency is generated digitally, but in general, the consumption current of the digital circuit that constitutes the DDS increases in proportion to the frequency of the reference signal input, so that the high frequency clock input DD
The current consumption in S becomes large. Therefore, there is a problem that the power consumption of the entire terminal increases when the mobile communication terminal is actually used and the power consumption also increases when the terminal stands by. An object of the present invention is to provide a local oscillation circuit that reduces power consumption at least when the terminal is on standby.

[0005]

In the local oscillator circuit of the present invention, a first variable frequency divider is inserted in front of a phase comparator of a PLL loop, and a second variable frequency divider is provided between a DDS and its reference oscillator. A control unit is provided which inserts a frequency divider and controls the frequency division ratios of the first and second variable frequency dividers. Here, the frequency division ratio of each of the first and second variable frequency dividers is controlled so that the output frequency becomes low when the mobile communication terminal is on standby.

[0006]

According to the present invention, when the communication terminal is on standby, the control unit controls the frequency division ratio of the second variable frequency divider to reduce the frequency of the reference signal input of the DDS, thereby reducing the current consumption of the DDS. At the same time, the frequency division ratio of the first variable frequency divider is controlled to enable the phase comparison in the phase comparator of the PLL loop.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention. In the figure, 1 is a VCO, 2 is a buffer amplifier, 3 is a fixed frequency divider, 4 is a phase comparator, 5 is CP, and 6 is an LPF.
Although the PLL loop is configured as in the conventional case, the first variable frequency divider 7 is interposed between the fixed frequency divider 3 and the phase comparator 4 here. Further, the DDS 8 is configured to output the created reference frequency to the phase comparator 4 and perform phase comparison in the PLL loop.
The second variable frequency divider 9 is inserted between the reference oscillator 8 and the reference oscillator 10. Then, the first and second variable frequency dividers 7,
The division ratio of 9 can be controlled simultaneously by the control unit 11.

According to this configuration, in frequency synchronization on the call CH, the control unit 11 causes the frequency division ratio designating signals 14, 13 to be generated.
Then, the frequency division ratios of the first and second variable frequency dividers 7 and 9 are set to 1/1. Therefore, the signal of the reference oscillator 10 is directly input to the DDS 8, and the reference frequency corresponding to the carrier frequency of the designated CH 12 is input from the DDS 8 to the phase comparator 4 of the PLL loop. On the other hand, the output of the VCO 1 is frequency-divided by the fixed frequency divider 3, passes through the first variable frequency divider 7 as it is, is phase-compared with the reference frequency in the phase comparison 4, drives CP 5, and passes LPF 6 to the VCO 1 The carrier frequency is generated by controlling the voltage value.

However, when the call CH is closed, the control unit 11 controls the first and second variable frequency dividers 7, 7.
The predetermined frequency division ratio is set so that the output signal of 9 has a low frequency. Therefore, the signal of the reference oscillator 10 divided by the second variable frequency divider 9 is input to the DDS 8, and a low frequency signal is output from the DDS 8 based on this input signal, and the phase comparator of the PLL loop is output. Input to 4. on the other hand,
Also in the PLL loop, the signal whose frequency is lowered by the frequency dividing operation of the first variable frequency divider 7 is input to the phase comparator 4. Therefore, the phase comparator 4 can perform the phase comparison as in the actual use to obtain the frequency synchronization of the control CH. At this time, the DDS 8 reduces the signal frequency to reduce the current consumption, thereby reducing the entire terminal. Power consumption is reduced.

[0010]

As described above, according to the present invention, the input frequency of the DDS is lowered when the communication terminal is on standby, and the frequency of the PLL loop is lowered at the same time.
It is possible to reduce the current consumption in the DS and obtain a local oscillation circuit in which the power consumption of the entire communication terminal is suppressed.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a local oscillator circuit of the present invention.

FIG. 2 is a block diagram of an example of a conventional local oscillation circuit.

FIG. 3 is a slot arrangement diagram in the TDMA system.

[Explanation of symbols]

 1 VCO (voltage controlled oscillator) 3 fixed frequency divider 4 phase comparator 5 CP (charge pump) 6 LPF (low-pass filter) 7 first variable frequency divider 8 DSS (direct digital synthesizer) 9 second Variable frequency divider 10 Reference oscillator 11 Controller

Claims (2)

[Claims] 1. A local oscillator circuit in which an oscillation frequency signal from a DDS (Direct Digital Synthesizer) is used as a reference frequency of a phase comparator in a PLL loop, and an output signal of this PLL loop is used as a local oscillation signal of a mobile communication terminal. The first variable frequency divider is inserted before the phase comparator, the second variable frequency divider is inserted between the DDS and its reference oscillator, and the first variable frequency divider is inserted between the DDS and the reference oscillator. A local oscillating circuit using a direct digital synthesizer having a control unit for controlling a frequency division ratio. 2. The direct digital synthesizer according to claim 1, wherein the frequency division ratios of the first and second variable frequency dividers are controlled so that the output frequency becomes low when the mobile communication terminal is on standby. Local oscillator circuit.