JPH0469459B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a battery saving circuit for a wireless device using a synthesizer circuit.

〔overview〕

In the battery saving circuit of a wireless device equipped with a synthesizer circuit using a phase-locked loop circuit, power is supplied intermittently to the phase comparator, which consumes a lot of power, and the output of the phase comparator is disabled while the phase comparator is not operating. By opening the capacitor of the low-pass filter and discharging the charge accumulated in the capacitor, the oscillation frequency of the voltage-controlled oscillator is maintained, which improves the saving efficiency and allows the reception of call control signals with short data lengths even during battery saving. This is how it was done.

[Conventional technology]

Phase-controlled loop (PLL) including voltage-controlled oscillator
Wireless devices that use synthesizer circuits take a long time to lock the synthesizer circuit, and it is difficult to implement battery saving when the call control signal from the other station is a single call and the data length of the control signal is short. It was hot.

[Problem that the invention seeks to solve]

In such wireless devices, it is not possible to reduce the current during standby. In particular, in the case of portable wireless devices, it is generally not possible to increase the battery capacity, so there is a drawback that the usage time until battery replacement is shortened.

The present invention aims to eliminate such drawbacks and provides a battery saving circuit that can be applied to a wireless device having a synthesizer circuit.

[Means for solving problems]

The present invention includes a voltage controlled oscillator, a phase comparator,
and a receiver controlled by the phase-locked loop circuit, and supplies power to the receiver for a first predetermined time (Ta). , followed by a second predetermined time (Td) is a battery saving circuit equipped with means for cutting off the power supply to the receiver, and as a means for solving the above-mentioned problem,
Circuit means for continuously supplying power to the voltage controlled oscillator and the phase locked loop circuit excluding the voltage controlled oscillator are supplied with power for a first predetermined time (Ta) and for a second predetermined time (Td). A first control means for cutting off the power supply, keeping the phase comparator and the voltage controlled oscillator connected for the first predetermined time (Ta), and controlling the phase comparator for the second predetermined time (Td). a second control means for keeping the comparator and the voltage controlled oscillator in a disconnected state;
extremely short period of time (Tb) that continues intermittently within
The present invention is characterized by comprising a third control means for supplying power for as long as possible.

[Effect]

If power is intermittently supplied to the phase comparator of the synthesizer circuit, the output frequency of the voltage controlled oscillator will change significantly when the phase comparator is not operating. For this purpose, an on/off switch is inserted between the output of the phase comparator and the low-pass filter, and when the phase comparator is not operating, the output is kept open, and during this time, the capacitor used in the low-pass filter accumulates. The oscillation frequency of the voltage controlled oscillator is maintained by the generated charge.

Therefore, even during periods when the phase comparator is not operating, the receiver can be operated intermittently for short periods of time.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS A device according to an embodiment of the present invention will be explained below based on the drawings.

FIG. 1 is a block configuration diagram showing the configuration of an apparatus according to an embodiment of the present invention. FIG. 2 is a waveform diagram of control signals from the control section 10, in which the control signal A controls the switch 5, and the control signal B controls the switches 6 and 7. Further, when the control signal is at H level, the switch is closed, and when the control signal is at L level, the switch is disconnected.

First, the configuration of this embodiment device will be explained based on FIG. This embodiment device includes an antenna 1,
A receiver 2 that demodulates the desired wave signal from the antenna 1, a phase-locked loop circuit 3 that includes a voltage-controlled oscillator 31, a phase comparator 32, and a low-pass filter 33, and a squelch circuit that determines that the desired wave signal has been input. A switch 5 is inserted between the circuit 4, a switch 5 connected to the power input of the receiver 2, a switch 6 connected to the power input of the phase comparator 32, and the output of the phase comparator 32 and the low-pass filter 33. Switch 7
and a control unit 8 connected to the control input of the switch 5, the control input of the switch 6, the control input of the switch 7, the control output of the squelch circuit 4, and the control input of the phase comparator 32, and the power input of the switch 5, Power input of switch 6, voltage controlled oscillator 31
and a power terminal 15 connected to the power input of the control unit 8 and the power input of the control unit 8, respectively.

Next, the power saving operation of the device according to the embodiment of the present invention will be explained with reference to FIGS. 1 and 2.

When the power switch of the wireless device is turned on, a voltage is applied to the power terminal 15, and the control section 8 starts a battery saving operation. This time point is the time t=0 shown in FIG. First, switches 5, 6, and 7 are brought into contact for a time Ta by control signals A and B, as shown in FIG. , brings the phase-locked loop circuit 3 including the voltage controlled oscillator 31 into a stable state.
After this stable state is established, the receiver 2 is turned off for a time Tc by the control signal A shown in FIG. 2, and powered on for a time Tb, which is repeated for a time Td. It will be done. Next, as shown in FIG. 2, the phase-locked loop circuit 3 is stabilized again by control signals A and B at time t ₁ =Ta+Td, and then the intermittent operation described above is performed again. This operation is repeated until the squelch circuit 4 detects that the desired wave is input from the antenna 1.

When the squelch circuit 4 determines that the desired wave signal has been input, the control unit 8 stops the intermittent operation of the switch 5, and the switch 5 is brought into a constantly connected state.
On the other hand, the demodulated signal from the receiver 2 is given to the control unit 8, and it is determined whether or not there is a signal calling the local station.If it is determined that there is a signal calling the local station, the intermittent operation of the switches 6 and 7 is stopped. Battery saving operation stops. If it is determined that there is no signal calling the local station, the battery saving operation is started again. During battery saving, the phase comparator circuit 32, which consumes a lot of current, is
Do not apply power for Td and receiver 2
Power consumption can be reduced because the power supply is intermittently switched on and off.

Here, the time Ta is set to be longer than the time required for the phase comparator circuit 32 to stabilize, and the time Td is set to be shorter than the time required for the free run frequency of the voltage controlled oscillator 31 to deviate from the specified frequency. For example, the time Ta is 100 milliseconds and the time Td is 1 second to several seconds.
Note that since the time Tb is determined by specifying the rising edge of the squelch circuit 4, it can generally be set to a short time of several tens of milliseconds or less.

Next, we will explain why, according to the present device, reception is possible during battery saving even when the call control signal between wireless devices is a single call control signal and the data length of the call control signal is short.

The time Ta after the wireless device is powered on is the time required for the phase comparator circuit 32 to lock, so reception is impossible; however, once locked, the low-pass filter 33 Since the oscillation frequency of the voltage controlled oscillator 31 is held by the charge stored in the capacitor used in the oscillation, the time Tb can be set short.

Furthermore, since the oscillation frequency of the voltage controlled oscillator 31 is extremely close to the specified frequency, the time required for locking after the first time Ta+Td has elapsed can be extremely shortened compared to the initial time Ta. We are using.

〔Effect of the invention〕

As explained above, the present invention has the effect of enabling battery saving even in a wireless device using a synthesizer, thereby reducing power consumption during standby.

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram showing the configuration of an apparatus according to an embodiment of the present invention. FIG. 2 is a waveform diagram showing timing during battery saving. 1... Antenna, 2... Receiver, 3... Phase locked loop circuit, 4... Squelch circuit, 5, 6, 7
...Switch, 8...Control unit, 31...Voltage controlled oscillator, 32...Phase comparator, 33...Low pass filter.

Claims (1)

[Claims] 1. Added to a wireless device comprising a phase-locked loop circuit including a voltage-controlled oscillator, a phase comparator, and a low-pass filter, and a receiver controlled by the phase-locked loop circuit, In a battery saving circuit equipped with a means for supplying power to the receiver during a first predetermined time (Ta) and cutting off power supply to the receiver during a second predetermined time (Td), the voltage controlled oscillator and a phase-locked loop circuit other than the voltage controlled oscillator, the power is supplied for a first predetermined time (Ta) and the power supply is cut off for a second predetermined time (Td). a first control means for maintaining the phase comparator and the voltage controlled oscillator in a connected state for the first predetermined time (Ta), and controlling the phase comparator and the voltage controlled oscillator for the second predetermined time (Td); a second control means for keeping the voltage controlled oscillator in a disconnected state; and a third control means for supplying power to the receiver only for an extremely short time (Tb) that continues intermittently within the second predetermined time (Td). A battery saving circuit characterized by comprising a control means.