JPH08307256A - Pll circuit - Google Patents

Abstract

PURPOSE: To reduce the power consumption by holding a count of a programmable frequency divider in a lock state for a prescribed time after the PLL circuit is locked and inhibiting input of an output of a phase comparator circuit to an LPF. CONSTITUTION: A control circuit 10 decides in advance by a time possible for consecutive reception according to a holding voltage in an LPF 8 and gives an H level signal to an AND circuit 3 and a switch 9 to close a loop of the PLL circuit. Here, the holding voltage of the LPF8 has more voltage change than that in the lock state, so the unlock state is detected and a phase comparator circuit 7 makes phase comparison. When the circuit 7 outputs a lock detection signal, the circuit 10 provides an output of an L level signal to the AND circuit 3 and the switch 9 and then provides an output of an H level signal attended with the lapse of a prescribed time. The prescribed time is set to nearly one second and an input of a programmable frequency divider 2 is interrupted and the counting is stopped to reduce the power consumption very much.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL circuit which constitutes a local oscillation circuit of a communication device or the like.

[0002]

2. Description of the Related Art Conventionally, a local oscillation circuit such as a communication device is used as a PLL.
A circuit configuration is well known, for example, from Japanese Utility Model Publication No. 2-8438.

By the way, the PLL circuit, for example, in the case of a communication device, holds a locked state, and therefore is always in an operating state even while receiving a specific frequency.

[0004]

However, in recent years, many communication devices such as radio receivers, cordless phones, and mobile phones are operated by a battery, and the PLL always operates as described above. In the state, the power consumption becomes a problem.

[0005] Since the counter constituting the PLL circuit are usually manufactured CMOS, and is proportional to the square or third power of the frequency of the counter used power consumption of the CMOS counter frequency hundreds MH _Z In the radio receiver and the like used, the problem of power consumption is particularly remarkable.

[0006]

The PLL circuit of the present invention comprises:
In view of the above point, a voltage controlled oscillator circuit, a programmable frequency divider for frequency-dividing an output signal of the voltage controlled oscillator circuit, and a phase comparison of a reference signal and a frequency-divided output signal of the programmable frequency divider. When the count value of the programmable frequency divider is locked for a predetermined time after the phase comparator circuit, the low-pass filter that supplies a control voltage to the voltage controlled oscillator circuit based on the output signal of the phase comparator circuit, and the PLL circuit are locked. And a control circuit for inhibiting the input to the low-pass filter of the phase comparison circuit.

Further, the control circuit operates intermittently in synchronization with the frequency of the reference signal.

[0008]

Since the present invention is configured as described above, the counter which constitutes the programmable frequency divider of the PLL circuit operates intermittently.

[0009]

An embodiment of the present invention will be described with reference to the drawings.
FIG. 1 shows, for example, a block diagram of a PLL circuit used in a radio receiver, and (1) is a voltage controlled oscillator circuit (VCO) capable of changing an oscillation frequency by a voltage applied to a control terminal, The oscillating output is fed to the mixing circuit of the radio receiver and is used to generate an intermediate frequency signal as is well known. (2) is a programmable frequency divider that divides the oscillation output signal of the VCO (1), and is configured so that the division ratio can be changed. The oscillation output signal of the VCO (1) is given to the programmable frequency divider (2) via the AND circuit (3). Reference numeral (4) is a reference oscillating circuit, which comprises a temperature-compensated crystal oscillator (TCXO) (5) which outputs a reference signal of a predetermined frequency, and a frequency divider (6) which divides the frequency. (7) inputs the output signal (fv) of the programmable frequency divider (2) and the output signal (fr) of the frequency divider (6), compares their phases, and outputs a signal corresponding to the phase difference. Locked state (phase matched) with the phase comparison circuit
When, the lock detection signal is output. (8) is a VCO based on the phase difference signal from the phase comparison circuit (7)
A low-pass filter (LP that supplies a control voltage to (1)
F).

A switch (9) is a phase comparison circuit (7).
And the low-pass filter (8) is disconnected. (10)
Is a control circuit consisting of a microprocessor, which outputs the output fr of the frequency divider (6) and the lock signal Lock of the phase comparison circuit (7).
Then, the control signal (STP) is supplied to the other input terminal of the AND circuit (3) and the switch (9). When the control signal is low, the connections in the AND circuit (3) and the switch (9) are opened.

The operation of the above configuration will be described with reference to FIG. First, when the radio receiver is in the search operation state, the control circuit (10) gives a high level signal as a control signal (STP) to the AND circuit (3) and the switch (9) to make the PLL circuit into a closed loop, and Each time the lock detection signal (Lock) is input, the frequency division ratio of the programmable frequency divider (2) is changed at predetermined step intervals. As a result, as is well known, the oscillation frequency of the VCO (1) changes, and it becomes possible for the broadcasting station to receive in a predetermined frequency band. When the radio receiver receives a predetermined broadcasting station, the control circuit (1
The search stop signal is output to 0), and the control circuit (10) receiving this signal stops the search, that is, stops changing the frequency division ratio of the programmable frequency divider (2).

Then, the control circuit (10) operates the AND circuit (3) in accordance with the timing of shifting from the search operation to the reception operation and also in accordance with the frequency of the output fr of the frequency divider (6). Supply a low level signal to the switch (9),
Programmable frequency divider (2) and low-pass filter (8)
Prohibits inputting signals to. As a result, the VCO (1) operates based on the voltage held in the low pass filter (8) in the locked state.

However, in this low-pass filter (8), as is well known, due to the leakage of the capacitor of the low-pass filter (8) and the power consumed in the circuit,
Its output voltage usually drops over time. Therefore, the control circuit (10) predetermines the time during which continuous reception is possible by the holding voltage of the low-pass filter (8),
When that time has passed, a high level signal is given to the AND circuit (3) and the switch (9) to close the loop of the PLL circuit. At this time, the holding voltage of the low-pass filter (8) has a slight voltage change as compared with that at the time of locking.
The lock is released, and the phase comparison processing is performed in the phase comparison circuit (7). After that, when the lock detection signal (Lock) is output from the phase comparison circuit (7), the control circuit (10) outputs a low level signal to the AND circuit (3) and the switch (9), and then, for a predetermined time. High with time
Output level signal. After that, the above operation is repeated in the receiving operation.

In this embodiment, the predetermined time is set to about 1 second. In the programmable frequency divider (2), when its input is cut off and the counting operation is stopped, its power consumption becomes extremely small.

By the way, in the present invention, the input of the programmable frequency divider (2) is cut off, but since the power supply to the programmable frequency divider (2) is continued, the programmable frequency divider (2) is ) Holds the count content. This is because when the power to the programmable frequency divider (2) is cut off, when the power is supplied to the programmable frequency divider (2) again to start up, the standby time until the operation stabilizes, the setting of initial data, etc. This is because it will take time. When the power supply is cut off, the AND circuit (3) and switch (9) are set to Hi early in consideration of the time required.
It is necessary to supply a gh level signal.

That is, if the continuous reception time by the holding voltage of the low-pass filter (8) is 1 second, the AND circuit (3) is reached when the start-up time of the programmable frequency divider (2) is subtracted from this. Since it is necessary to give a high level signal to the switch (9), the count down time of the programmable frequency divider (2) is shortened accordingly.
This is because low power consumption can be prevented.

A temperature compensated crystal oscillator (TCXO)
Supply of power to (5) and the frequency divider (6) is also continued. Therefore, the output fr of the frequency divider (6) can be shared as a synchronizing signal for the control circuit (10) to output a control signal.

[0018]

Since the present invention is configured as described above, the counter constituting the programmable frequency divider of the PLL circuit will operate intermittently, and its power consumption can be reduced. it can.

Further, since the programmable frequency divider or the like becomes inoperative while holding the count value, it is not necessary to consider its start-up time, and when performing continuous reception, the programmable frequency divider is correspondingly operated. It is possible to prolong the non-operation time such as, and further improve the low power consumption.

Further, since the power supply to the reference oscillation circuit is continued, this output can be used as a synchronizing signal for power saving operation.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the embodiment.

[Explanation of symbols]

 1 Voltage Controlled Oscillator 2 Programmable Frequency Divider 3 AND Circuit 4 Reference Oscillator 5 Temperature Compensated Crystal Oscillator 6 Frequency Divider 7 Phase Comparison Circuit 8 Low Pass Filter 9 Switch 10 Control Circuit

Claims (2)

[Claims] 1. A voltage controlled oscillator circuit, a programmable frequency divider for frequency-dividing an output signal of the voltage controlled oscillator circuit, and a phase comparison circuit for phase-comparing a reference signal and a frequency-divided output signal of the programmable frequency divider. , A low-pass filter that supplies a control voltage to the voltage controlled oscillator circuit based on the output signal of the phase comparison circuit and a PLL circuit are locked, and then the count value of the programmable frequency divider is held in a state when locked And a control circuit for inhibiting the input to the low-pass filter of the phase comparison circuit. 2. The control circuit causes the intermittent operation in synchronization with the frequency of the reference signal.
PLL circuit described in