JPH11213682A - Nonvolatile semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent data from being read out wrong due to deterioration of a threshold value. SOLUTION: A nonvolatile semiconductor storage device 10 is provided with reference memory cells RM of a count corresponding to multi-bit data writable to memory cells constituting a memory cell array 11, a reference write/read control circuit 14 which writes different data among the multi-bit data to the reference memory cells RM at the write time of data to the memory cell, reads data of the plurality of reference memory cells at the read time, and judges a threshold value voltage of each multi-bit data at the read time, a judgement voltage-setting circuit 15 for generating a judgment reference voltage according to the judgment result and a row decoder 16 which impresses the judgment reference voltage generated at the judgment voltage-setting circuit 15 to an address designated word line, thereby reading data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-level nonvolatile semiconductor memory device capable of recording at least three-level data in a memory cell.

[0002]

2. Description of the Related Art In a nonvolatile semiconductor memory device such as a flash memory, a binary memory cell structure in which data having two values "0" and "1" are recorded in one memory cell transistor is usually used. It is. Further, in response to recent demands for increasing the capacity of a semiconductor memory device, data of at least three values or more is recorded in one memory cell transistor.
A so-called multi-level nonvolatile semiconductor memory device has been proposed (for example, "A Multi-Level 32M").
b Flash Memory "'95 ISSCC
p. 132-).

FIG. 3 is a diagram showing the relationship between the threshold voltage Vth level and the data content when two-bit quaternary data is recorded in one memory transistor in a NAND flash memory. .

In FIG. 3, the vertical axis represents the threshold voltage Vth of the memory transistor, and the horizontal axis represents the distribution frequency of the memory transistor. The contents of 2-bit data constituting data to be recorded in one memory transistor are represented by [IO _{n + 1} , IO _n ] and [I _n
O _n + 1, IO _n] = [1,1], [1,0], [0,
1] and [0, 0]. That is, data “0”, data “1”, data “2”, data “3”
There are four states:

A NAND flash memory in which multi-level data is written in page units (word line units) has been proposed (for example, reference: 1996 IEEE Intern).
ational Solid-State Circuits Conference, ISSCC96 /
SESSION 2 / FLASH MEMORY / PAPER TP 2.1: A 3.3V 128Mb M
ulti-Level NAND Flash Memory For Mass Storage Appl
ication.pp32-33).

A read operation in a NAND flash memory in which quaternary data (2-bit data) is written in page units is performed as follows. First, the addressed word line voltage is raised to 2.4V (VWL
00) is read. At this time, if the threshold voltage Vth is higher than the word line voltage (2.4 V), no cell current flows. As a result, the bit line voltage holds the precharge voltage, and high is sensed. On the other hand, if the threshold voltage Vth is lower than the word line voltage (2.4 V), a cell current flows. This causes the bit line voltage to drop and a low to be sensed.

Next, the word line voltage is increased to 1.2 V (VWL01).
, And finally, reading is performed with the word line voltage of 0V.

Specifically, when the cell data is "00",
Since no current flows in all word lines, the bus IOi + 1,
(1, 1) is output to IOi. Cell data is "0"
In the case of "1", a current flows only in the case of the word line voltage VWL00, and (0, 1) is outputted to the buses IOi + 1 and IOi. , IOi have (0,1), (0,0)
Is read.

[0009]

However, the above-mentioned conventional nonvolatile semiconductor memory device can have only a certain criterion (word line voltage) at the time of reading.
There is a possibility that the written multi-valued data is deteriorated due to aging or electric stress, and deviates from the initial threshold distribution. In this case, there is a disadvantage that the data is read as erroneous data.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a nonvolatile semiconductor memory device capable of preventing reading of erroneous data due to deterioration of a threshold value.

[0011]

In order to achieve the above object, according to the present invention, the amount of charge stored in a charge storage section changes in accordance with the voltage applied to a word line and a bit line. A nonvolatile semiconductor memory device having a threshold voltage that changes and has at least one memory cell that stores data having a value corresponding to the threshold voltage, and that writes multi-bit data to the memory cell. Reference memory cells corresponding to the number of multi-bit data that can be written to the cells, and writing means for writing different data of the multi-bit data to the plurality of reference memory cells when writing data to the memory cells. Have.

Also, in the present invention, at the time of reading, the data of the plurality of reference memory cells is read, the threshold voltage of each multi-bit data at the time of reading is determined, and the determination reference voltage according to the determination result is set. There is provided a determination voltage setting means for generating, and a reading means for applying the determination reference voltage generated by the determination voltage setting means to an addressed word line to read data.

Further, in the present invention, preferably, data is written in page units, and the plurality of reference memory cells are provided in page units.

In the present invention, data is written and read in page units, and the plurality of reference memory cells are provided in page units.

According to the present invention, at the time of writing, writing of multi-bit data into each memory cell is performed, for example, on a page basis, and a plurality of reference memory cells provided on a page basis are read out of the multi-bit data. Different data is written by the writing means. At the time of reading, data of a plurality of reference memory cells is read by the determination voltage setting means, and the threshold voltage of each multi-bit data at the time of reading is determined. Then, a judgment reference voltage according to the judgment result is generated and supplied to the reading means. In the read means, data is read by applying the judgment reference voltage supplied from the judgment voltage setting means to the addressed word line.

[0016]

FIG. 1 is a block diagram showing one embodiment of a nonvolatile semiconductor memory device according to the present invention.

The nonvolatile semiconductor memory device 10 includes a memory cell array 11, a reference memory cell array 1
2. Multi-bit data write / read control circuit 13, reference write / read control circuit 14, decision voltage setting circuit 1
5 and a row decoder 16. In the nonvolatile semiconductor memory device 10 according to the present embodiment, 2-bit data is stored in one memory transistor, that is, as shown in FIG. 3, the content of the data is [IO _{n + 1} , IO _n ] =
[1,1], [1,0], [0,1], [0,0]
NAND capable of recording quaternary data in a state and writing quaternary data in page units (word line units)
A flash memory is described as an example.

The memory array 11, as shown in FIG.
Each memory cell has a common word line WL0-WL15
Are connected to the memory strings A0 to Am.

FIG. 2 shows the memory string A in FIG.
0, A1 and the corresponding write / read control circuit 1
3 is a circuit diagram showing a specific configuration example of a main part of FIG.

As shown in FIG. 2, the memory string A0
Is connected to the bit line BL1, and the memory string A1 is connected to the bit line BL2. Memory string A
0 is a memory cell transistor MT0A to MT0 composed of a nonvolatile semiconductor memory device having a floating gate.
15A is formed of a NAND string connected in series, and the drain of the memory cell transistor MT0A of this NAND string is connected to the bit line BL1 via the selection gate SG1A, and the memory cell transistor MT1
The source of 5A is connected to the reference potential line VGL via the selection gate SG2A. The memory string A1 is composed of a NAND string in which memory cell transistors MT0B to MT15B each composed of a nonvolatile semiconductor memory device having a floating gate are connected in series.
The drain of the memory cell transistor MT0B of the AND string is connected to the bit line BL2 via the selection gate SG1B.
, And the source of the memory cell transistor MT15B is connected to the reference potential line VGL via the selection gate SG2B.

The gates of the selection gates SG1A and SG1B are commonly connected to the selection signal supply line SSL, and the gates of the selection gates SG2A and SG2B are connected to the selection signal supply line G.
It is commonly connected to SL.

The write / read control circuit 13 controls writing and reading of data to and from the memory cell array 11 in page units (word line units), and its main part is, as shown in FIG. (NMOS) transistors NT1 to NT17, a p-channel MOS (PMOS) transistor PT1, and latch circuits Q1 and Q2 formed by coupling inputs and outputs of an inverter.

The NMOS transistor NT1 has a power supply voltage V
_The gate is connected between the supply line of _CC and the bit line BL1, and the gate is connected to the supply line of the inhibit signal IHB1. The NMOS transistor NT2 is connected between the supply line of the power supply voltage V _CC and the bit line BL2, and has a gate connected to the supply line of the inhibit signal IHB2. A depletion type NMOS transistor N is connected between a connection point between the bit line BL1 and the NMOS transistor NT1 and a connection point between the memory string A0 and the bit line BL1.
T18 is connected, and a depletion type NMOS transistor NT19 is connected between a connection point between the bit line BL2 and the NMOS transistor NT2 and a connection point between the memory string A1 and the bit line BL2. The gates of the NMOS transistors NT18 and NT19 are connected to a decouple signal supply line DCPL.

An NMOS is provided between a connection point between bit line BL1 and NMOS transistor NT1 and bus line IOi.
Transistors NT3, NT5 and NT16 are connected in series, and bit line BL2 and NMOS transistor NT2
The NMOS transistors NT4, NT7, and NT17 are connected in series between the connection point (1) and the bus line IOi + 1. The connection point between the NMOS transistors NT3 and NT5 and the connection point between the NMOS transistors NT4 and NT7 are grounded via the NMOS transistor NT6, and the drain of the PMOS transistor PT1 and N
It is connected to the gates of MOS transistors NT8 and NT13. Then, the gate of the NMOS transistor NT6 is connected to the supply line of the reset signal RST,
The source of the OS transistor PT1 is connected to the supply line of the power supply voltage V _CC, the gate of the PMOS transistor PT1 is connected to the supply line of the signal Vref.

First storage node N1a of latch circuit Q1
Is connected to a connection point between the NMOS transistors NT5 and NT16, and the second storage node N1b is grounded via NMOS transistors NT8 to NT10 connected in series. The first storage node N2a of the latch circuit Q2 is connected to a connection point between the NMOS transistors NT7 and NT17, and the second storage node N2b is connected in series.
It is grounded via MOS transistors NT13 to NT15. Also, the NMOS transistors NT8 and NT9
NMOS transistor NT whose connection point is connected in series
11, grounded via NT12. The gate of the NMOS transistor NT9 is connected to the first storage node N2a of the latch circuit Q2.
0 is connected to the supply line of the latch signal φLAT2, the gate of the NMOS transistor NT11 is connected to the second storage node N2b, and the NMOS transistor N
The gate of T12 is connected to the supply line of the latch signal φLAT1, and the gates of the NMOS transistors NT14 and NT15 are connected to the supply line of the latch signal φLAT3. The gate of the NMOS transistor NT16 as a column gate is connected to the supply line of the signal Yi, and the gate of the NMOS transistor NT17 is connected to the signal Yi.
It is connected to the i + 1 supply line.

The structures of the memory strings A2 to Am and the corresponding write / read control circuits have the same structure as that of FIG.

The reference memory cell array 12
The reference memory cells RM including memory cell transistors equivalent to the memory cell transistors forming the memory cell array 11 are arranged in, for example, 16 rows and 4 columns. The reason why the memory cells are arranged in four columns is that the present embodiment describes a device for 2-bit data as an example, and the number of columns is determined according to the number of bits of multi-bit data. For example, in the case of 3-bit data, it is possible to take eight values, so that it is arranged in eight columns. Then, at the time of writing, different data of the multi-bit data is written to the four memory cells in each row. For example,
Data [1, 1] in the memory cell in the first column, data [1, 0] in the memory cell in the second column, data [0, 1] in the memory cell in the third column, and memory in the fourth column Data [0,0] is written in the cell. At the time of reading, multi-bit data written in four columns of memory cells connected to the same word line as the memory cells forming the corresponding page is read.

Reference write / read control circuit 14
During writing, different data of 2-bit data is written to and read from four columns (four) of memory cells connected to the same word line as the memory cells constituting the page to be written in the memory cell array 11. At times, the multi-bit data written in the four memory cells connected to the same word line as the memory cells forming the corresponding page is read, and the result is output to the determination voltage setting circuit 15.

The determination voltage setting circuit 15 sets a voltage to be applied to the addressed word line at the time of writing and reading, and supplies the voltage to the row decoder 16. And
At the time of reading, the reference write / read control circuit 1
4 based on the read result of the multi-bit data written to the four memory cells of the reference memory cell array 12 connected to the same word line as the memory cells forming the corresponding page read by the corresponding page. A judgment reference voltage to be applied to the designated word line is set and supplied to the row decoder 16.

More specifically, if there is no change (deterioration) in the threshold value due to a change over time or electric stress, and erroneous data is not read at a standard judgment reference voltage,
Standard determination reference voltages, that is, 2.4 V, 1.2 V, and 0 V are generated and supplied to the row decoder 16. on the other hand,
When erroneous data reading is performed at the standard judgment reference voltage, a memory cell array composed of memory cell transistors whose change in threshold value due to aging or electrical stress is equivalent to that of a reference memory cell 11
, A voltage different from the standard judgment reference voltage is generated and supplied to the row decoder 16.

Specifically, for example, when a standard determination reference voltage of 2.4 V is applied to the word line, the threshold value is not degraded from the reference memory cell RM of the cell data "00". Cell current does not flow. In this case, a standard determination reference voltage of 2.4 V is applied to the row decoder 1.
6 to read the memory cell array 11.
On the other hand, when a standard determination reference voltage of 2.4 V is applied to the word line, when the threshold value is degraded and the cell current flows from the reference memory cell RM of the cell data “00”, Is set to a voltage lower than the determination reference voltage 2.4 V, for example, 2.3 V or 2.2 V, and supplied to the row decoder 16 to read the memory cell array 11.

Similarly, when a standard judgment reference voltage of 1.2 V is applied to the word line, the cell current from the reference memory cell RM of the cell data "01" is not changed unless the threshold value is degraded. Not flowing. In this case, a standard determination reference voltage of 1.2 V is supplied to the row decoder 16 to read the memory cell array 11. On the other hand, when a standard determination reference voltage of 1.2 V is applied to the word line, when the threshold value is degraded and a cell current flows from the reference memory cell RM of the cell data “01”, the standard Is lower than the determination reference voltage of 1.2 V, for example, 1.
The voltage is set as low as 1 V or 1.0 V and supplied to the row decoder 16 to read the memory cell array 11.

It should be noted that, instead of resetting to a lower value and immediately reading the memory cell array 11 as described above, 0.1
It is also possible to adopt a configuration in which the memory cell array 11 is read after the voltage is reduced by V and a voltage at which normal reading is performed is selected.

Next, the write and read operations according to the above configuration will be described.

The write operation will be described. For example, first, writing is performed by the data stored in the latch circuit Q1, then writing is performed by the latch circuit Q2, and finally by the data of the latch circuit Q1 again. When the write data is (Q2, Q1) = (1, 0), the latch circuit Q1 changes from “0” to “1” when the write operation is sufficient.
However, when (Q2, Q1) = (0, 0), the latch circuit Q1 must be used as the write data in the third step, so that even if the write becomes sufficient in the first step, it is "0". Is not inverted to “1” (cannot be done).

The determination of the end of writing in each step is made when all the latched data becomes "1". Since the inversion of the latch circuit Q1 in the first step does not occur in the cell where the write data (Q2, Q1) = (0, 0), the end determination by a wired OR (not shown) is not performed.

The above-described writing is performed in page units. At this time, two columns (four) of memory cells connected to the same word line as the memory cells forming the page to be written in the memory cell array 11 are used. Different data of the bit data is written. In particular,
For example, data [1,1],
Data [1, 0] is written to the memory cells in the second column, data [0, 1] is written to the memory cells in the third column, and data [0, 0] is written to the memory cells in the fourth column.

Next, the read operation will be described. First, the reference write / read control circuit 14
The multi-bit data written in the four memory cells connected to the same word line as the memory cells forming the corresponding page is read, and the result is output to the determination voltage setting circuit 15. In the determination voltage setting circuit 15, based on the read result of the multi-bit data written in the four memory cells of the reference memory cell array 12,
A determination reference voltage to be applied to the addressed word line is set and supplied to the row decoder 16. Specifically, when there is no change (deterioration) of the threshold value due to aging or electrical stress and erroneous data is not read at the standard judgment reference voltage, the standard judgment reference voltage,
That is, 2.4 V, 1.2 V and 0 V are generated and supplied to the row decoder 16. In addition, when erroneous data is read at a standard judgment reference voltage, a change in threshold value due to a change with time or electric stress is constituted by a memory cell transistor equivalent to a reference memory cell. As what also occurs in the memory cells of the memory cell array 11, a voltage lower than the standard judgment reference voltage by about 0.1 V or 0.2 V is generated and supplied to the row decoder 16.

Then, the multi-bit data write / read control circuit 13 reads the addressed data of the memory cell array 11 in page units.

Specifically, first, the reset signal RST and the signals PGM1 and PGM2 are set to a high level. Thus, the first storage nodes N1a, N1a,
N2a is pulled to the ground level. As a result, the latch circuits Q1 and Q2 are cleared. Next, the word line voltage V
Reading is performed with WL00 set to a standard 2.4 V or a voltage set in accordance with the deterioration of the threshold value, for example, 2.3 V. If the threshold voltage Vth is higher than the word line voltage VWL00, no cell current flows. As a result, the bit line voltage holds the precharge voltage, and high is sensed. on the other hand,
If the threshold voltage Vth is lower than the word line voltage VWL00, a cell current flows. This causes the bit line voltage to drop,
A low is sensed. Next, the word line voltage VWL01 is set to 1.
Reading is performed at 2 V or a voltage set in accordance with the deterioration of the threshold value, for example, 1.1 V, and finally reading is performed at a word line voltage of 0 V.

Specifically, when the cell data is "00",
Since no current flows in all word lines, the bus IOi + 1,
(1, 1) is output to IOi. First, when reading with the word line voltage set to 2.4 V, the latch signal φLAT1 is set to a high level. At this time, no cell current flows. As a result, the bit line is maintained at a high level,
Since MOS transistor NT8 is kept conductive and latch circuit Q2 is cleared, latch circuit Q2
The second storage node N2b is kept at a high level, so that the NMOS transistor NT11 is kept conductive.
Therefore, the NMOS transistors NT8, NT11,
NT12 is held in a conductive state, and the second
Is pulled to the ground level, and the first storage node N1a of the latch circuit Q1 transitions to the high level.

Next, when reading with the word line voltage set to VWL01, the latch signal φLAT3 is set to the high level.
At this time, since the cell current does not flow, the bit line is kept at a high level, so that the NMOS transistor NT13 is kept conductive, the second storage node N2b of the latch circuit Q2 is pulled to the ground level, and the latch circuit Q2 Transitions to the high level. Finally, when reading with the word line voltage set to 0 V, the latch signal φLA
T1 is set to a high level. At this time, the bit line is kept at a high level because no cell current flows, and the NMOS transistor NT8 is kept in a conductive state.
Since the second storage node N2b of the latch circuit Q2 is at a low level, the NMOS transistor NT11 is turned off, and the first storage node N1a of the latch circuit Q1 holds a high level.

When the cell data is "01", a current flows only when the word line voltage is VWL00, and buses IOi + 1, IO
(0, 1) is output to i. First, when reading with the word line voltage set to VWL00 (eg, 2.3 V), the latch signal φLAT1 is set to a high level. At this time, the bit line goes low due to the flow of the cell current, so that the NMOS transistor NT8 is kept in a non-conductive state, and the first storage node N1a of the latch circuit Q1 holds the low level. Next, when reading is performed with the word line voltage set to VWL01 (for example, 1.1 V), the latch signal φATH3 is set to a high level. At this time, since the cell line does not flow, the bit line is kept at a high level, so that the NMOS
Transistor NT13 is kept conductive, second storage node N2b of latch circuit Q2 is pulled to the ground level, and first storage node N2a of latch circuit Q2 transitions to the high level. Finally, when reading with the word line voltage set to 0 V, the latch signal φLAT1 is set to the high level. At this time, since the cell current does not flow, the bit line is kept at a high level, so that the NMOS transistor NT8
Is maintained in a conductive state, but the second storage node N2b of the latch circuit Q2 is at a low level, so that the NMOS transistor NT11 is turned off, and the first storage node N1a of the latch circuit Q1 holds a low level. Similarly, when the cell data is "10" and "11", IOi +
(0, 1) and (0, 0) are read out to 1, IOi.

As described above, according to the present embodiment, the number of reference memory cells RM corresponding to the multi-bit data that can be written to the memory cells constituting the memory cell array 11 and the number of times when data is written to the memory cells A reference which writes different data of the multi-bit data into the reference memory cell, reads the data of the plurality of reference memory cells at the time of reading, and determines the threshold voltage of each multi-bit data at the time of reading. Write / read control circuit 14 and determination voltage setting circuit 15 for generating a determination reference voltage according to the determination result
And a row decoder 16 for applying a judgment reference voltage generated by the judgment voltage setting circuit 15 to the addressed word line to read data, so that the threshold voltage may be changed due to aging or electric stress. Erroneous data can be prevented from being read due to the deterioration of the data.

In the present embodiment, the case where the multi-bit data is 2 bits has been described as an example.
It is needless to say that the same effect can be obtained even when the number of bits is more than that. Further, in the present embodiment, the resetting of the judgment reference voltage is performed for VWL00 and VWL01, but various modes are possible, such as setting only VWL00 as a resetting target.

[0046]

As described above, according to the nonvolatile semiconductor memory device of the present invention, there is an advantage that erroneous data reading due to deterioration of the threshold due to aging or electric stress can be prevented.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a nonvolatile semiconductor memory device according to the present invention.

FIG. 2 shows a NAND string and write / write according to the present invention.
FIG. 3 is a circuit diagram illustrating a specific configuration example of a read control circuit.

FIG. 3 is a diagram showing a relationship between a threshold voltage Vth level and data content when data of two bits and having four values is recorded in one memory transistor in a NAND flash memory.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Nonvolatile semiconductor memory device, 11 ... Memory cell array, 12 ... Reference memory cell array, 13 ... Multi-bit data write / read control circuit, 14 ... Reference write / read control circuit, 15 ... Judgment voltage setting circuit , A
0 to Am: memory string, WL0 to WL15: word line, BL0, BL1: bit line, NT11 to NT19
... NMOS transistor, PT1 ... PMOS transistor, Q1, Q2 ... Latch circuit, RM ... Reference memory cell.

Claims (4)

[Claims] An amount of charge stored in a charge storage unit changes according to a voltage applied to a word line and a bit line, and a threshold voltage changes according to the change. What is claimed is: 1. A nonvolatile semiconductor memory device having at least one memory cell for storing value data and writing multi-bit data to the memory cell, comprising: A non-volatile semiconductor storage device, comprising: a memory cell; and a writing unit that writes different data of multi-bit data to the plurality of reference memory cells when writing data to the memory cell. 2. A determination voltage for reading data of the plurality of reference memory cells at the time of reading, determining a threshold voltage of each multi-bit data at the time of the reading, and generating a determination reference voltage according to a determination result. 2. The non-volatile semiconductor memory device according to claim 1, further comprising: setting means; and reading means for reading data by applying a judgment reference voltage generated by said judgment voltage setting means to an addressed word line. 3. The nonvolatile semiconductor memory device according to claim 1, wherein data is written in page units, and said plurality of reference memory cells are provided in page units. 4. The nonvolatile semiconductor memory device according to claim 2, wherein data is written and read in page units, and said plurality of reference memory cells are provided in page units.