JP4029469B2 - Nonvolatile semiconductor memory device and data writing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a multi-value type nonvolatile semiconductor memory device that records data of at least three values or more in a memory cell and a data writing method thereof.
[0002]
[Prior art]
In a nonvolatile semiconductor memory device such as a flash memory, a binary memory cell structure in which data having two values “0” and “1” is recorded in one memory cell transistor is usually used.
In response to recent demands for increasing the capacity of semiconductor memory devices, so-called multi-value type nonvolatile semiconductor memory devices in which data of at least three values are recorded in one memory cell transistor have been proposed (for example, , "A Multi-Level 32Mb Flash Memory" '95 ISSCC p132-).
[0003]
FIG. 8 is a diagram showing the relationship between the threshold voltage Vth level and the data contents when recording data consisting of 2 bits and having 4 values in one memory transistor in a NAND flash memory.
[0004]
In FIG. 8, the vertical axis represents the threshold voltage Vth of the memory transistor, and the horizontal axis represents the distribution frequency of the memory transistor.
The contents of 2-bit data constituting data to be recorded in one memory transistor are [IO_{n + 1}, IO_n] And [IO_{n + 1}, IO_n] = [1,1], [1,0], [0,1], [0,0]. That is, there are four states of data “0”, data “1”, data “2”, and data “3”.
[0005]
And NAND-type flash memory that writes multi-level data in page units (word line units) has been proposed (for example, literature; 1996 IEEE International Solid-State Circuits Conference, ISSCC96 / SESSION 2 / FLASH MEMORY / PAPER TP 2.1: A 3.3V 128Mb Multi-Level NAND Flash Memory For Mass Storage Application.pp32-33).
[0006]
FIG. 9 is a circuit diagram showing a main configuration of a NAND flash memory that performs writing in units of pages disclosed in the above document.
In FIG. 9, 1 is a memory cell array, 2 is a write / read control circuit, and BL2 and BL1 are bit lines, respectively.
[0007]
The memory cell array 1 includes memory strings A0 and A1 in which memory cells are connected to common word lines WL0 to WL15. The memory string A0 is connected to the bit line BL1, and the memory string A1 is connected to the bit line BL2.
The memory string A0 has a NAND string in which memory cell transistors MT0A to MT15A made of a nonvolatile semiconductor memory device having a floating gate are connected in series, and the drain of the memory cell transistor MT0A in this NAND string is the selection gate SG1A. Is connected to the bit line BL1, and the source of the memory cell transistor MT15A is connected to the reference potential line VGL via the selection gate SG2A.
The memory string A1 has a NAND string in which memory cell transistors MT0B to MT15B made of a nonvolatile semiconductor memory device having a floating gate are connected in series, and the drain of the memory cell transistor MT0B in this NAND string is the selection gate SG1B. Is connected to the bit line BL2, and the source of the memory cell transistor MT15B is connected to the reference potential line VGL via the selection gate SG2B.
[0008]
The gates of the selection gates SG1A and SG1B are commonly connected to the selection signal supply line SSL, and the gates of the selection gates SG2A and SG2B are commonly connected to the selection signal supply line GSL.
[0009]
The write / read control circuit 2 includes n-channel MOS (NMOS) transistors NT1 to NT17, a p-channel MOS (PMOS) transistor PT1, and latch circuits Q1 and Q2 formed by coupling the input and output of an inverter. .
[0010]
The NMOS transistor NT1 has a power supply voltage V_CCAnd the gate is connected to the supply line of the inhibition signal IHB1. The NMOS transistor NT2 has a power supply voltage V_CCAnd the gate is connected to the supply line of the inhibition signal IHB2.
A depletion type NMOS transistor NT18 is connected between the connection point of the NMOS transistors NT3 and NT1 and the connection point of the memory string A0 and the bit line BL1, and the connection point of the NMOS transistor NT4 and NMOS transistor NT2 and the memory string. A depletion type NMOS transistor NT19 is connected between the connection point of A1 and the bit line BL2. The gates of the NMOS transistors NT18 and NT19 are connected to the decouple signal supply line DCPL.
[0011]
NMOS transistors NT3, NT5, NT16 are connected in series between the connection point of the depletion type NMOS transistor NT18 and NMOS transistor NT1 and the bus line IOi, and the connection point of the depletion type NMOS transistor NT19 and NMOS transistor NT2 NMOS transistors NT4, NT7, NT17 are connected in series between the bus line IOi + 1.
The connection point of the NMOS transistors NT3 and NT5 and the connection point of the NMOS transistors NT4 and NT7 are grounded via the NMOS transistor NT6, and are connected to the drain of the PMOS transistor PT1 and the gates of the NMOS transistors NT8 and NT13. . The gate of the NMOS transistor NT6 is connected to the supply line of the reset signal RST, and the source of the PMOS transistor PT1 is the power supply voltage V._CCThe gate of the PMOS transistor PT1 is connected to the supply line of the signal Vref.
[0012]
The first storage node N1a of the latch circuit Q1 is connected to the connection point between the NMOS transistors NT5 and NT16, and the second storage node N1b is grounded via the NMOS transistors NT8 to NT10 connected in series.
The first storage node N2a of the latch circuit Q2 is connected to the connection point between the NMOS transistors NT7 and NT17, and the second storage node N2b is grounded via the NMOS transistors NT13 to NT15 connected in series.
The connection point of the NMOS transistors NT8 and NT9 is grounded via NMOS transistors NT11 and NT12 connected in series.
The gate of the NMOS transistor NT9 is connected to the first storage node N2a of the latch circuit Q2, the gate of the NMOS transistor NT10 is connected to the supply line of the latch signal φLAT2, and the gate of the NMOS transistor NT11 is connected to the second storage node N2b. The gate of the NMOS transistor NT12 is connected to the supply line of the latch signal φLAT1, and the gates of the NMOS transistors NT14 and NT15 are connected to the supply line of the latch signal φLAT3.
The gate of the NMOS transistor NT16 as a column gate is connected to the supply line of the signal Yi, and the gate of the NMOS transistor NT17 is connected to the supply line of the signal Yi + 1.
[0013]
FIG. 10A shows a timing chart at the time of reading, and FIG. 10B shows a timing chart at the time of writing (programming).
As can be seen from FIG. 10B, quaternary writing is performed in three steps, and the process proceeds to the next step when it is determined that all the cells originally written in page units in each step are sufficiently written.
[0014]
A read operation will be described.
First, the reset signal RST and the signals PGM1 and PGM2 are set to a high level. As a result, the first storage nodes N1a and N2a of the latch circuits Q1 and Q2 are pulled to the ground level. As a result, the latch circuits Q1 and Q2 are cleared.
Next, reading is performed with the word line voltage set to 2.4V. If the threshold voltage Vth is higher than the word line voltage (2.4 V), the cell current does not flow, so that the bit line voltage holds the precharge voltage, and high is sensed. On the other hand, if the threshold voltage Vth is lower than the word line voltage (2.4 V), the cell current flows, so that the bit line voltage drops and low is sensed.
Next, reading is performed with a word line voltage of 1.2V, and finally reading is performed with a word line voltage of 0V.
[0015]
Specifically, when the cell data is “00”, no current flows through all the word lines, so (1, 1) is output to the buses IOi + 1 and IOi. First, when reading with the word line voltage 2.4V, the control signal φLAT1 is set to the high level. At this time, since the cell current does not flow, the bit line is maintained at a high level, so that the NMOS transistor NT8 is maintained in a conductive state, and the latch circuit Q2 is cleared, whereby the second storage node N2b of the latch circuit Q2 is cleared. Is kept at a high level, the NMOS transistor NT11 is kept in a conductive state. Therefore, NMOS transistors NT8, NT11, NT12 are held conductive, second storage node N1b of latch circuit Q1 is pulled to the ground level, and first storage node N1a of latch circuit Q1 transitions to a high level. Next, when reading with the word line voltage 1.2V, the control signal φLAT3 is set to the high level. At this time, since the cell current does not flow, the bit line is maintained at the high level, so that the NMOS transistor NT13 is maintained in the conductive state, the second storage node N2b of the latch circuit Q2 is pulled to the ground level, and the latch circuit Q2 The first storage node N2a transitions to a high level. Finally, when reading with the word line voltage set to 0V, the control signal φLAT1 is set to the high level. At this time, since the cell current does not flow, the bit line is maintained at a high level, so that the NMOS transistor NT8 is maintained in a conductive state. However, since the second storage node N2b of the latch circuit Q2 is at a low level, the NMOS transistor NT11. Becomes non-conductive, and the first storage node N1a of the latch circuit Q1 maintains the high level.
[0016]
When the cell data is “01”, current flows only when the word line voltage is VWL00, and (0, 1) is output to the buses IOi + 1 and IOi. First, when reading with the word line voltage 2.4V, the control signal φLAT1 is set to the high level. At this time, since the cell current flows, the bit line becomes low level, so that the NMOS transistor NT8 is kept nonconductive, and the first storage node N1a of the latch circuit Q1 holds low level. Next, when reading with the word line voltage 1.2V, the control signal φLAT3 is set to the high level. At this time, since the cell current does not flow, the bit line is maintained at the high level, so that the NMOS transistor NT13 is maintained in the conductive state, the second storage node N2b of the latch circuit Q2 is pulled to the ground level, and the latch circuit Q2 The first storage node N2a transitions to a high level. Finally, when reading with the word line voltage set to 0V, the control signal φLAT1 is set to the high level. At this time, since the cell current does not flow, the bit line is maintained at a high level, so that the NMOS transistor NT8 is maintained in a conductive state. However, since the second storage node N2b of the latch circuit Q2 is at a low level, the NMOS transistor NT11. Becomes non-conductive, and the first storage node N1a of the latch circuit Q1 maintains the low level.
Similarly, when cell data is “10” and “11”, (0, 1) and (0, 0) are read to IOi + 1 and IOi, respectively.
[0017]
Next, the write operation will be described.
In the circuit of FIG. 9, first, writing is performed using data stored in the latch circuit Q1, then writing is performed using data stored in the latch circuit Q2, and finally, the latch circuit Q1 again.
When the write data is (Q2, Q1) = (1, 0), the latch circuit Q1 is inverted from “0” to “1” when the write is sufficient, but (Q2, Q1) = (0, 0). In this case, since the latch circuit Q1 needs to be used as the write data for the third step, even if the write is sufficient in the first step, the latch circuit Q1 is not inverted from “0” to “1” (cannot be performed).
[0018]
The write end determination at each step is determined to be the end of the write at the stage where all the latch data (Q2 or Q1) on the target side becomes “1”.
In the cell of the write data (Q2, Q1) = (0, 0), the latch circuit Q1 is not inverted in the first step, so the end determination by the wired OR is not performed.
[0019]
[Problems to be solved by the invention]
By the way, in the circuit described above, as shown in FIG. 11, first, after writing the cells having the write data “10” and “00” (Step 1) according to the data of the latch circuit Q1, the latch circuit Q2 In accordance with the data, writing of cells with write data “01” and “00” is performed (Step 2), and finally writing of cells with write data “00” is performed (Step 3).
That is, in the above-described conventional circuit, the writing data “10” and “01” are written only in Step 1 and Step 2, so the writing time of “10” and “01” is the same as the writing of Step 1 and Step 2. It corresponds to the inclusion time. The cell with write data “00” is performed in all Steps 1 to 3, but Step 3 and Step 3 are written after the ISPP voltage is lowered in preparation for overwriting between Step 2 and Step 3. ing.
[0020]
From this, it is estimated that the write time of the cell whose write data is “00” is almost the same as the write time of Step 3. As a result, the writing is performed serially, which is one of the causes that the four-value writing time becomes longer.
As can be seen from FIG. 11, the sum of the write times of data “10” and “01” and the write time of data “00” take substantially the same time.
[0021]
Further, although writing is performed using self-boost, the write inhibit voltage for charging the bit line is lowered by the threshold voltage Vth by the NMOS transistor supplied with the signals PGM1, PGM2, and Vcc-Vth (B) (Vth (B): Vth affected by the back bias effect.
In order to enable self-boost in this state, it is necessary to set the selection gate on the drain side of the memory cell high, which is a hindrance in realizing a high-speed read operation.
In addition, the bit line is charged by the latch before writing. From the perspective of the latch, the bit line is a huge capacitor with a voltage of 0 V. When the latch data is “1”, the latch data is in contact with the bit line. It may be reversed.
In order to avoid this, when the bit line is charged in accordance with the write data, the gate voltage of the NMOS transistors NT5 and NT7 is set to be low. For this reason, the charging current is reduced, and it takes time to charge the bit line.
And it takes time for the verify reading.
[0022]
The present invention has been made in view of such circumstances, and an object of the present invention is to provide a nonvolatile semiconductor memory device and a data writing method thereof that can shorten writing and verify reading time.
[0023]
[Means for Solving the Problems]
  In order to achieve the above object, according to the present invention, the amount of charge stored in the charge storage unit changes according to the voltage applied to the word line and the bit line, and the threshold voltage changes according to the change. A non-volatile semiconductor memory device having a memory cell for storing data of a value corresponding to a threshold voltage and writing multi-bit data of three or more values to the memory cell in units of pages, wherein all bit lines are connected before writing Write control having precharge means for precharging to a predetermined voltage and a latch circuit for latching write data, and discharging the bit line selected according to the address according to the latch data and writing in parallel CircuitAndThe write control circuit includes a plurality of latch circuits for one bit corresponding to each bit line, and each latch circuit has a first storage node that holds a latch data level and a first storage node that holds an inversion level thereof. Two storage nodes, andProvided corresponding to each of the above latch circuits,The level of the second storage node of each latch circuit is a predetermined level.FirstWhen the level isGround potentialAnd connectMultiple discharges that discharge the bit linesWhen switch means and verify read,A first signal supplied in accordance with a threshold level to be verified, a second signal indicating whether or not a memory cell to be written has exceeded a target threshold, and another latch circuit Depending on the level of the first storage node, the level of the second storage node of each latch circuit is set to the second level that makes the switch means conductive or non-conductive. The second storage node of one latch circuit among the plurality of latch circuits is set to the first level or the above in accordance with the process to be determined, the first signal, and the second signal. The level of the first storage node of the one latch circuit determined according to the determined level of the second storage node and determined according to the determined level of the second storage node, the first signal, And the second signal in response to the second signal. Performs a process of determining the one of the second level the first level or the second level of the storage node of another latch circuit of the latch circuitCircuit,Whether or not rewriting is performed by determining whether or not writing to the memory cell is completed during a writing operation depending on whether or not the second storage nodes of the plurality of latch circuits have the same second level. A determination circuit for determining whether or notHave.
[0024]
  Further, according to the present invention, the amount of charge accumulated in the charge accumulating portion changes according to the voltage applied to the word line and the bit line, the threshold voltage changes according to the change, and the threshold voltage changes. A plurality of memory cells that store data of a given value are connected, and one end and the other end of the memory string are connected to the bit line and the ground line through a select transistor whose conduction state is controlled according to the gate voltage. A non-volatile semiconductor memory device in which control gates of memory cells in the same row are connected to a common word line and multi-bit data of three or more values is written to the memory cells in units of pages using self-boost. Therefore, it has precharge means for precharging all bit lines to a predetermined voltage before writing, and a latch circuit for latching write data, and is selected according to the address. Is discharged in accordance with bit line latch data includes a write control circuit for writing in parallel, and the write control circuit,Provided corresponding to each of the above latch circuits,The level of the second storage node of each latch circuit is a predetermined level.FirstWhen the level isGround potentialAnd connectMultiple discharges that discharge the bit linesWhen switch means and verify read,A first signal supplied in accordance with a threshold level to be verified, a second signal indicating whether or not a memory cell to be written has exceeded a target threshold, and another latch circuit Depending on the level of the first storage node, the level of the second storage node of each latch circuit is set to the second level that makes the switch means conductive or non-conductive. The second storage node of one latch circuit among the plurality of latch circuits is set to the first level or the above in accordance with the process to be determined, the first signal, and the second signal. The level of the first storage node of the one latch circuit determined according to the determined level of the second storage node and determined according to the determined level of the second storage node, the first signal, And the second signal in response to the second signal. Performs a process of determining the one of the second level the first level or the second level of the storage node of another latch circuit of the latch circuitCircuit,Whether or not rewriting is performed by determining whether or not writing to the memory cell is completed during a writing operation depending on whether or not the second storage nodes of the plurality of latch circuits have the same second level. A determination circuit for determining whether or notHave.
[0025]
  In the present invention, the amount of charge stored in the charge storage unit changes according to the voltage applied to the word line and the bit line, the threshold voltage changes according to the change, and the value according to the threshold voltage A method of writing data in a nonvolatile semiconductor memory device having a memory cell for storing a plurality of data and writing multi-bit data of three or more values to the memory cell in units of pages, wherein all bit lines are set to a predetermined voltage before writing. 1 bit having a first step of precharging, and a first storage node corresponding to each bit line and a second storage node holding its inversion level for the bit line selected according to the address at the time of writing MinpluralA second step of discharging in accordance with the latch data of the latch circuit and performing writing in parallel. In the second step, the level of the second storage node of the latch circuit is a predetermined level.FirstWhen levelBy switch meansWith the selected bit linegroundConnect the potentialDischarge the bit lineDuring verify read,A first signal supplied in accordance with a threshold level to be verified, a second signal indicating whether or not a memory cell to be written has exceeded a target threshold, and another latch circuit Depending on the level of the first storage node, the level of the second storage node of each latch circuit is set to the second level that makes the switch means conductive or non-conductive. The second storage node of one latch circuit among the plurality of latch circuits is set to the first level or the above in accordance with the process to be determined, the first signal, and the second signal. The level of the first storage node of the one latch circuit determined according to the determined level of the second storage node and determined according to the determined level of the second storage node, the first signal, And the second signal in response to the second signal. Performs a process of determining the one of the second level the first level or the second level of the storage node of another latch circuit of the latch circuit,It is determined whether rewriting is performed or not depending on whether the level of the second storage node of the plurality of latch circuits has reached the first level or the second level..
[0026]
  Further, according to the present invention, the amount of charge accumulated in the charge accumulating portion changes according to the voltage applied to the word line and the bit line, the threshold voltage changes according to the change, and the threshold voltage changes. A plurality of memory cells that store data of a given value are connected, and one end and the other end of the memory string are connected to the bit line and the ground line through a select transistor whose conduction state is controlled according to the gate voltage. Data of nonvolatile semiconductor memory devices arranged in the shape of memory cells, in which control gates of memory cells in the same row are connected to a common word line, and multi-bit data of three or more values are written into memory cells in units of pages using self-boost A first method for precharging all bit lines to a predetermined voltage before writing, and a bit line selected according to an address at the time of writing. , Of one bit and a second storage node for holding a first memory node corresponding to each bit line and an inverted levelpluralA second step of discharging in accordance with latch data of the latch circuit and performing writing in parallel. In the second step,A first signal supplied in accordance with a threshold level to be verified, a second signal indicating whether or not a memory cell to be written has exceeded a target threshold, and another latch circuit Depending on the level of the first storage node, the level of the second storage node of each latch circuit is set to the second level that makes the switch means conductive or non-conductive. The second storage node of one latch circuit among the plurality of latch circuits is set to the first level or the above in accordance with the process to be determined, the first signal, and the second signal. The level of the first storage node of the one latch circuit determined according to the determined level of the second storage node and determined according to the determined level of the second storage node, the first signal, And the second signal in response to the second signal. Performs a process of determining the one of the second level the first level or the second level of the storage node of another latch circuit of the latch circuit,It is determined whether rewriting is performed or not depending on whether the level of the second storage node of the plurality of latch circuits has reached the first level or the second level..
[0027]
The present invention further includes a verify read circuit that determines whether or not writing is sufficient for each write bit during the write operation by sequentially raising the word line voltage from a low level to a high level.
[0028]
Further, according to the present invention, the amount of charge accumulated in the charge accumulating portion changes according to the voltage applied to the word line and the bit line, the threshold voltage changes according to the change, and the threshold voltage changes. A method of writing data in a non-volatile semiconductor memory device having a memory cell for storing data of different values and writing multi-bit data of three or more values to the memory cell in units of pages, wherein all bit lines are connected to a predetermined bit before writing The voltage is precharged, and at the time of writing, the bit line selected according to the address is discharged according to the latch data, and writing is performed in parallel.
[0029]
According to the present invention, after all the bit lines are precharged to a predetermined voltage, for example, a power supply voltage, before writing, the bit line selected according to the address is discharged according to the latch data at the time of writing. Done in parallel.
[0030]
DETAILED DESCRIPTION OF THE INVENTION
First embodiment
FIG. 1 is a circuit diagram showing a first embodiment of a nonvolatile semiconductor memory device according to the present invention. The nonvolatile semiconductor memory device 10 includes a memory array 11, a write / read control circuit 12, and a determination circuit 20.
[0031]
As shown in FIG. 1, the memory array 11 includes memory strings A0 and A1 each having a memory cell connected to a common word line WL0 to WL15. The memory string A0 is connected to the bit line BL1, and the memory string A1 is connected to the bit line BL2.
The memory string A0 is a NAND string in which memory cell transistors MT0A to MT15A made of a nonvolatile semiconductor memory device having a floating gate are connected in series, and the drain of the memory cell transistor MT0A of this NAND string is connected via the selection gate SG1A. Connected to the bit line BL1, the source of the memory cell transistor MT15A is connected to the reference potential line VGL via the selection gate SG2A.
The memory string A1 is formed of a NAND string in which memory cell transistors MT0B to MT15B made of a nonvolatile semiconductor memory device having a floating gate are connected in series, and the drain of the memory cell transistor MT0B of this NAND string is connected via the selection gate SG1B. Connected to the bit line BL2, the source of the memory cell transistor MT15B is connected to the reference potential line VGL via the selection gate SG2B.
[0032]
The gates of the selection gates SG1A and SG1B are commonly connected to the selection signal supply line SSL, and the gates of the selection gates SG2A and SG2B are commonly connected to the selection signal supply line GSL.
[0033]
The write / read control circuit 12 includes NMOS transistors NT21 to NT43, a PMOS transistor PT21, an inverter INV21, and latch circuits Q21 and Q22 formed by coupling the input and output of the inverter.
[0034]
An NMOS transistor 21 and a depletion type NMOS transistor NT42 are connected in series between the node SA21 and the bit line BL1, and an NMOS transistor 22 and a depletion type NMOS transistor NT43 are connected in series between the node SA21 and the bit line BL2. It is connected to the.
An address decode signal Ai is supplied to the gate electrode of the NMOS transistor NT22, and a signal / Ai (/ indicates inversion) is supplied to the gate electrode of the NMOS transistor NT21. The gates of the NMOS transistors NT42 and NT43 are connected to the decouple signal supply line DCPL.
[0035]
NMOS transistor NT24 is connected between node SA21 and ground line GND, and node SA21 and power supply voltage V are connected._CCThe PMOS transistor PT21 is connected to the supply line. The connection point between the drain of the PMOS transistor PT21 and the node SA21 is connected to the gate electrodes of the NMOS transistors NT28 and NT34.
The reset signal RST1 is supplied to the gate electrode of the NMOS transistor NT24, and the signal Vref is supplied to the gate electrode of the PMOS transistor PT21.
[0036]
NMOS transistors NT23 and NT25 are connected in series between the node SA21 and the ground line, and an NMOS transistor NT26 is connected between the connection point of the NMOS transistors NT23 and NT25 and the ground line.
Then, the signal PGM is supplied to the gate electrode of the NMOS transistor NT23, the gate electrode of the NMOS transistor NT25 is connected to the second storage node N21b of the latch circuit Q21, and the gate electrode of the NMOS transistor NT26 is connected to the second electrode of the latch circuit Q22. It is connected to the storage node N22b.
[0037]
NMOS transistors NT27 and NT28 are connected in series between the first storage node N21a of the latch circuit Q21 and the ground line. Also, NMOS transistors NT29 and NT30 and NMOS transistors NT31 and NT32 connected in series are connected in parallel between the second storage node N21b of the latch circuit Q21 and the connection point of the NMOS transistors NT27 and NT28. ing.
[0038]
NMOS transistors NT33 and NT34 are connected in series between the first storage node N22a of the latch circuit Q22 and the ground line. Further, NMOS transistors NT35 and NT36 connected in series are connected between the second storage node N22b of the latch circuit Q22 and the connection point of the NMOS transistors NT33 and NT34.
The drain / source of the NMOS transistor NT37 is connected to the drain / source of the NMOS transistor NT35.
[0039]
The reset signal RST2 is supplied to the gate electrodes of the NMOS transistors NT27 and NT33, the gate electrode of the NMOS transistor NT29 is connected to the first storage node N22a of the latch circuit Q22, and the gate electrode of the NMOS transistor NT31 is connected to the latch circuit Q22. Connected to the second storage node N22b, the gate electrode of the NMOS transistor NT35 is connected to the first storage node N21a of the latch circuit Q21.
Further, the signal φLAT3 is supplied to the gate electrode of the NMOS transistor NT30, the signal φLAT2 is supplied to the gate electrode of the NMOS transistor NT32, the signal φLAT1 is supplied to the gate electrode of the NMOS transistor NT36, and the signal φLAT0 is supplied to the gate electrode of the NMOS transistor NT37. Is supplied.
[0040]
NMOS transistor NT38 is connected between first storage node N21a of latch circuit Q21 and bus line IOi, and NMOS transistor NT39 is connected between first storage node N22a of latch circuit Q22 and bus line IOi + 1. Yes.
The gate of the NMOS transistor NT38 as a column gate is connected to the supply line of the signal Yi, and the gate of the NMOS transistor NT39 is connected to the supply line of the signal Yi + 1.
[0041]
Further, the input terminal of the inverter INV21 is grounded, and the output terminal is connected to the determination circuit 20. In addition, NMOS transistors NT40 and NT41 are connected in parallel between the output terminal of the inverter INV21 and the ground line. The gate electrode of the NMOS transistor NT40 is connected to the second storage node N21b of the first latch circuit Q21, and the gate electrode of the NMOS transistor NT41 is connected to the second storage node N22b of the second latch circuit Q22. Yes.
[0042]
The determination circuit 20 determines, based on the potential of the output line of the inverter INV21, whether or not writing has been completed for all the memory cell transistors during the write operation.
Specifically, when the writing is completed, the first storage nodes N21a and 22a of the latch circuits Q21 and Q22 are connected to the power supply voltage V_CCThe second storage nodes N21b and 22b are at the ground level. As a result, the NMOS transistors NT40 and NT41 are held in a non-conductive state, and the potential of the output line of the inverter INV21 becomes the power supply voltage V._CCIt is determined that the writing has been completed.
On the other hand, if there is a cell that is not sufficiently written, either or all of the first storage nodes N21a and 22a of the latch circuits Q21 and Q22 are at the ground level, and the second storage nodes N21b and 22b are powered on. Voltage V_CCBecome a level. As a result, the NMOS transistor NT40 or NT41, or both transistors are held in a conductive state, and the potential of the output line of the inverter INV21 becomes the ground level, thereby determining that there is a cell with insufficient writing.
[0043]
Next, the write, verify read, and read operations with the above configuration will be described in order with reference to the drawings.
[0044]
First, the write operation will be described with reference to the timing chart of FIG.
[0045]
Prior to the start of the write operation, the signal Vref is set to the low level, and the PMOS transistor PT21 is held in the conductive state. As a result, all bit lines are connected to the power supply voltage V_CCIs charged.
At this time, the signal PGM and the signals φLAT0 to φLAT3 for controlling read / verify are set to the ground level (low level) so that the latch data is not affected, and the NMOS transistor NT23, NMOS transistors NT30, NT32, NT36, NT37 is held in a non-conductive state.
[0046]
At this time, the address decode signal Ai and its inverted signal / Ai have a high withstand voltage equal to or higher than Vcc + Vthh (B) (Vthh (B): a voltage obtained by adding the influence of the back bias effect to Vth of the high withstand voltage transistor). A signal DCPL for controlling the depletion type transistors NT42 and NT43 is a power supply voltage V._CCControlled by level.
As a result, the MMOS transistors NT21, NT22, NT42, NT43 become conductive, and as a result, the bit lines BL0, BL1 are both supplied with the power supply voltage V_CCIs charged.
[0047]
  Thereafter, one of the address decode signals Ai and / Ai is set to the ground level based on the address selection information.
  Here, it is assumed that the bit line BL2 is selected, and the address decode signal Ai.ButA case where the high level is set and the inverted signal / Ai is set to the ground level will be described as an example.
  At this time, since the NMOS transistor NT21 is in a non-conductive state, the bit line BL1 is in a floating state at the power supply voltage Vcc level.
  Thereafter, the signal Vref is switched to the power supply voltage Vcc level, the so-called precharge PMOS transistor PT21 is held in the non-conductive state, the signal PGM is switched to the power supply voltage Vcc level, and the NMOS transistor NT23 is held in the conductive state; The selection signal supply line SSL connected to the gate electrodes of the selection gates SG1A and SG1B on the drain side of the memory cell is set to the power supply voltage Vcc level.
[0048]
  At this time, when the write data is other than “11”, at least one of the second storage nodes N21b and N22b of the latch circuits Q21 and Q22 is at a high level, and at least one of the NMOS transistors NT25 or NT26. Is kept in a conductive state. For this reason, the bit line is discharged to the ground level.
  Note that the bit line is discharged by the NMOS transistor that serves as the gate input for the inverted signal of the latch data.latchThere is no impact on the data.
  When the write data is “11”, both the NMOS transistors NT25 and NT26 are held in the non-conductive state, so that the bit line voltage is held at the precharge voltage Vcc.
[0049]
At this stage, if the write data is other than “11”, the bit line and the memory cell channel are at the ground level, and if the write data is “11”, the bit line is V_CCThe memory cell channel has a voltage of Vcc−VthDSG (B) or lower, and the bit line on the non-selected bit line “BL1” side has V_CCThe channel of the memory cell has a voltage equal to or lower than Vcc−VthDSG (B).
Here, the word line is raised to the drive voltage while the NMOS transistor NT23 is kept in the conductive state, and the write operation is started.
[0050]
At this time, if the write data is other than “11”, the Fowler-Nordheim tunneling (hereinafter referred to as FN tunnel) phenomenon occurs due to the electric field between the word line voltage VPGM and the channel voltage 0 V, and the cell is written. That is, writing is performed on cells with write data “00”, “01”, and “10”.
In the case where the write data is “11” and in the memory cell on the non-selected bit line BL1 side, the channel voltage rises due to capacitive coupling due to the rise of the word line potential, whereby the channel is B bit by the drain side select gate SG1A. Disconnected from the line BL1.
Then, at the stage where the rise of the word line is completed, the channel becomes a forbidden voltage, the FN tunnel phenomenon does not occur, and the cell is held in the erased state.
[0051]
Here, in the case of the write data “11” and the cell on the non-selected bit line BL1 side, since the bit line BL1 is in a floating state, there is a concern that the bit line voltage drops due to leakage. When the bit line voltage becomes Vcc−VthDSG (B) or lower, the drain side select gate is turned on, and the bit line to channel capacitance ratio (C_BL>> C_chn) Causes the channel voltage to drop from the boost voltage (about 8V) to Vcc-VthDSG (B) at once.
As a result, an electric field sufficient to cause the FN tunnel phenomenon is applied between the floating gate and the channel, and writing occurs.
However, the threshold voltage Vth of the selection gate on the drain side is normally set high, and the threshold voltage Vth in the state where the back bias is applied is at least 1.5 V or more. Power supply voltage V_CCEven if the voltage is 3 V, this phenomenon does not occur unless a voltage drop of 1.5 V occurs.
On the other hand, the write time for one time is 10 μs to 20 μs. If there is a leak with a voltage drop of 1.5 V during this period, it is impossible to read with a NAND flash memory that performs reading on the order of μs.
As described above, the phenomenon that the bit line voltage drops due to the leak and the write operation occurs in the write inhibit cell cannot occur.
[0052]
When ending the writing, first, the word line is lowered to 0 V, and at the same time, the signal DCPL is set to the ground level and the reset signal RST1 is set to the high level to discharge the bit line and channel charges. The voltage applied to the selection signal supply line SSL to which the drain side selection gate is connected is lowered.
Thus, one write operation is completed, and the verify read operation is started.
[0053]
As described above, writing is performed by wired-OR (Wired-OR) of write data, whereby writing to memory cells that need to be written is started simultaneously.
As a result, it is not necessary to lower the ISPP voltage by switching the Step as in the prior art, so that the number of ISPP pulses until the final word line voltage is reached is reduced as shown in FIG. Shortening is realized.
[0054]
Next, the verify read operation will be described with reference to the timing chart of FIG.
In the verify operation, a write check of “00”, “01”, and “10” is performed every time one write is completed.
In this embodiment, when verifying is performed from a high level as in the prior art (the word line voltage is in the order of VVF2 → VVF1 → VVF0), it is necessary to recharge the bit line between each verify. (The word line voltage is in the order of VVF0.fwdarw.VVF1.fwdarw.VBF2), so that the bit line is charged once and the verify time is shortened. VVF0, VVF1, and VBF2 are verify word line voltages.
The verify operation will be specifically described below.
[0055]
First, the signal DCPL remains at the ground level, the signal Vref is set to the ground level, the PMOS transistor PT21 is held in the conductive state, the bit line is set to VthDEP (0V) (the threshold value of the depletion type transistor with the gate set to 0V). Voltage Vth).
At the same time, the selection signal supply line SSL to which the gate electrodes of the selection gates SG1A and SG1B on the drain side are connected is set to the same voltage as the unselected word line voltage of the selected string (P5V: a voltage with 5.0 to 6.0V). Is set.
When the charging is completed, the bit line is VthDEP (0 V), and the node SA21 is the power supply voltage V_CCThe depletion type transistors NT42 and NT43 are automatically turned off.
[0056]
Here, the signal Vref is set to a voltage that allows the PMOS transistor PT21 to pass a current sufficient to compensate for the leak current of the bit line. P5V is applied to the word line of the unselected memory cell, and VVF0 is applied to the word line of the selected cell. Is applied.
At this time, if the threshold voltage Vth of the memory cell is equal to or higher than the word line voltage VVF0, the cell current does not flow, so that the bit line is VthDEP (0 V) and the node SA21 is the power supply voltage V_CCRetained.
On the other hand, if the threshold voltage Vth of the memory cell is equal to or lower than the word line voltage VVF0, the cell current flows, the bit line voltage drops, the depletion type transistors NT42 and NT43 become conductive, and the bit line and the node SA21 Redistribution of charge occurs between the two nodes, and the voltage at the node SA21 suddenly drops to about VthDEP (0V) ′ (← voltage slightly lowered from the bit line precharge voltage VthDEP (0V)).
[0057]
  Here, when the signal φLAT3 is set to a high level, the NMOS transistor NT30 is held in a conductive state.
  At this time, when the write data is “10”, the first storage node N22a of the latch circuit Q22 is at the high level, the NMOS transistor NT29 is held conductive, and the node SA21 is held at the power supply voltage Vcc (Vth> When VVF0: writing is sufficient), the NMOS transistor NT28 is in a conductive state.InRetained.
  As a result, the second storage node N21b of the latch circuit Q21 is pulled to the ground level, and the first storage node N21a of the latch circuit Q21 is switched from the low level to the high level.
  As a result, the latch data of the latch circuits Q22 and Q21 becomes “11”, and writing is not performed in the subsequent rewriting.
  On the other hand, when the node SA21 is VthDEP (0 V) or the write data is “01” or “00”, the NMOS transistor NT28 or NT29 is held in the non-conductive state, and the latch data does not change. For this reason, writing is performed at the time of rewriting.
[0058]
That is, when verify is performed with the word line voltage VVF0, if the threshold voltage is greater than the word line voltage (Vth> VVF0), the latch data “10” of the latch circuits Q22 and Q21 changes to “11” (inverted) In other cases, there is no change in the latch data.
[0059]
Next, the word line voltage is set to VVF1 and verify reading is performed. After a predetermined time has elapsed, the signal φLAT1 is set to a high level. As a result, the NMOS transistor NT36 is held conductive.
At this time, if the write data is “01”, the first storage node N21a of the latch circuit Q21 is at a high level, so that the NMOS transistor NT35 is held in the conductive state, and the node SA21 is at the power supply voltage V_CCIs held (Vth> VVF1: sufficient writing), the NMOS transistor NT34 is held in a conductive state.
As a result, the second storage node N22b of the latch circuit Q22 is pulled to the ground level, and the first storage node N22a of the latch circuit Q22 is switched from the low level to the high level.
As a result, the latch data of the latch circuits Q22 and Q21 becomes “11”, and writing is not performed in the subsequent rewriting.
On the other hand, when the node SA21 is VthDEP (0V) or the write data is “00” or “10”, the NMOS transistor NT34 or NT35 is held in the non-conductive state, and therefore the latch data does not change. For this reason, writing is performed at the time of rewriting.
[0060]
That is, when the verify is performed with the word line voltage VVF1, if the threshold voltage is larger than the word line voltage (Vth> VVF1), the latch data “01” of the latch circuits Q22 and Q21 changes to “11” (inverted) In other cases, there is no change in the latch data.
[0061]
Finally, the word line voltage is set to VVF2, and verify reading is performed. After a predetermined time has elapsed, the signals φLAT1 and φLAT0 are set to a high level, and then the signal φLAT3 is set to a high level. As a result, the NMOS transistors NT36 and NT37 are held conductive, and the NMOS transistor NT30 is held conductive.
At this time, if the write data is “00”, the node SA21 is at the power supply voltage V_CCAre held (Vth> VVF2: sufficient writing), the NMOS transistors NT34 and NT28 are held in a conductive state.
As a result, the second storage node N22b of the latch circuit Q22 is pulled to the ground level, and the first storage node N22a of the latch circuit Q22 is switched from the low level to the high level. As a result, the NMOS transistor NT29 is held conductive.
Thereafter, when the signal φLAT3 is set to the high level, the NMOS transistor NT30 is held in the conductive state as described above.
As a result, the second storage node N21b of the latch circuit Q21 is pulled to the ground level, and the first storage node N22a of the latch circuit Q21 is switched from the low level to the high level.
As a result, the latch data of the latch circuits Q22 and Q21 becomes “11”, and writing is not performed in the subsequent rewriting.
On the other hand, when the node SA21 is VthDEP (0 V), the NMOS transistors NT34 and NT28 are held in a non-conductive state, so that there is no change in the latch data. For this reason, writing is performed at the time of rewriting.
[0062]
That is, when the verify is performed with the word line voltage VVF2, if the threshold voltage is larger than the word line voltage (Vth> VVF2), the latch data “00” of the latch circuits Q22 and Q21 changes to “11” (inverted) In other cases, there is no change in the latch data.
[0063]
After the above-mentioned 3 Step verification is completed, if all the cells are sufficiently written, the first storage nodes N21a and N22a of all the latch circuits Q22 and Q21 are at the high level.
Then, after the verify reading is completed, if the writing is sufficient, the second storage nodes N21b and 22b of the latch circuits Q21 and Q22 are set to the ground level. As a result, the NMOS transistors NT40 and NT41 are held in a non-conductive state, and the potential of the output line of the inverter INV21 becomes the power supply voltage V._CCThus, it is determined that writing has been completed.
On the other hand, if there is a cell that is not sufficiently written, either or all of the first storage nodes N21a and 22a of the latch circuits Q21 and Q22 are at the ground level, and the second storage nodes N21b and 22b are powered on. Voltage V_CCBecome a level. As a result, the NMOS transistor NT40 or NT41, or both transistors are held conductive, and the potential of the output line of the inverter INV21 becomes the ground level, so that it is determined that there is a cell with insufficient writing.
[0064]
Next, the read operation will be described with reference to the timing chart of FIG.
In the normal read operation, the signal DCPL is set to the ground level prior to reading, and one of the address decode signals Ai and / Ai is supplied with the power supply voltage V_CCThe signal Vref is set to the ground level, the selected bit line is VthDEP (0 V), and the node SA21 is the power supply voltage V_CCAt the same time, the reset signal RST2 is set to the high level, and the latch data of the latch circuits Q22 and Q21 is reset to the low level.
[0065]
Here, when reading is performed by switching the selected word line voltage in the order of VRD0 → VRD1 → VRD2 in the same manner as in verifying during normal reading, distribution 0 to distribution 2 in FIG. SA21 is the power supply voltage V_CCThe latch data of the latch circuit Q21 cannot be read. This is because in distribution 1, it is desired to set the latch data of the latch circuit Q21 to the low level, but it is inverted to the high level.
However, when reading is performed by switching the selected word line voltage in the order of VRD 2 → VRD 1 → VRD 0, the cells in the distribution 2 are turned on when the word line voltages VRD 2 and VRD 1 are read. Since the potential of SA21 drops, precharge (2 times in total) is required for each verification.
Therefore, in the present embodiment, reading is performed by switching the selected word line voltage in the order of VRD1 → VRD2 → VRD0.
As a result, the target latch data can be reliably inverted at each verify step, and re-precharge is performed once between readings at the word line voltage VRD2 and the word line voltage VRD0, and the reading time is shortened.
[0066]
As described above, after the precharge of the bit line / node SA21 and the reset of the latch circuits Q22 and Q21 are completed, the unselected word line is set to P5V, the selected word line is set to VRD1, and after a predetermined time has elapsed, the signal φLAT1 and φLAT0 is set to the high level, and the NMOS transistors NT36 and NT37 are held in the conductive state, and reading is performed.
At this time, if the memory cells are distribution 3 and distribution 2, the cell current does not flow, so that the node SA21 has the power supply voltage V_CCThe NMOS transistor NT34 is held in a conductive state.
As a result, the second storage node N22b of the latch circuit Q22 is pulled to the ground level, and the first storage node N22a of the latch circuit Q22 is switched from the low level to the high level.
On the other hand, if the memory cells are distribution 1 and distribution 0, the cell current flows and the node SA21 falls to VthDEP (0V) ′, so that the signals φLAT1 and φLAT0 are set to the high level, and the NMOS transistors NT36 and NT37 are turned on. Even if held, since the NMOS transistor NT34 is held in a non-conductive state, the latch data of the latch circuit Q22 does not change.
That is, the latch data when reading is performed with the selected word line voltage VRD1 is as follows.
Distribution 3, 2: {Q22, Q21} = {H, L}
Distribution 1, 0: {Q22, Q21} = {L, L}
[0067]
Next, the selected word line voltage is raised to VRD2 without precharging the bit line and the node SA21, and after a predetermined time has elapsed, the signal φLAT3 is set to the high level, and the NMOS transistor NT30 is held in the conductive state and read. Is done.
At this stage, the bit lines of distributions 3 and 2 are VthDEP (0 V), and the node SA21 is the power supply voltage V._CCIs held in. On the other hand, in the distributions 1 and 0, the bit line and the node SA21 are about VthDEP (0 V). However, even if the bit line and the node SA21 are reprecharged, if the read operation is performed with the selected word line voltage VRD2, the node SA21 is The voltage drops to about VthDEP (0 V) again. Therefore, even if reading is performed with the selected word line voltage VRD2 without re-precharging, the reading result is not affected.
[0068]
At this time, the potential of the node SA21 is originally about VthDEP (0V) in the distributions 1 and 0, and about VthDEP (0V) due to the cell current flowing in the distribution 2.
On the other hand, in the distribution 3, the cell current does not flow, so that the node SA21 has the power supply voltage V_CCTo a degree.
Here, when the signal φLAT3 is set to the high level, the second storage node N21b of the latch circuit Q21 is drawn to the ground level through the path of the NMOS transistors NT29, NT30, NT28, and the latch data of the latch circuit Q21 is at the low level. Switch to high level.
On the other hand, if the cell has a distribution of 2 to 0, the node SA21 falls to VthDEP (0V). Therefore, even if the signal φLAT3 is set to the high level, the NMOS transistor NT28 is held in the non-conductive state. The latch data of this does not change.
That is, the latch data when reading is performed with the selected word line voltage VRD2 is as follows.
Distribution 3: {Q22, Q21} = {H, H}
Distribution 2: {Q22, Q21} = {H, L}
Distribution 1, 0: {Q22, Q21} = {L, L}
[0069]
Finally, at the same time as the selected word line voltage is set to VRD0, the signal Vref is set to 0V, and the bit line and the node SA21 are recharged.
Then, after a predetermined time has elapsed, the signal φLAT3 is set to a high level and reading is performed.
At this time, the cell current does not flow in the distributions 3 to 1, so that the node SA21 has the power supply voltage V_CCTo a degree.
On the other hand, the cell current flows only in the case of distribution 0, and the node SA21 falls to about VthDEP (0V). Here, when the signal φLAT2 is set to a high level, when the second storage node N22b of the latch circuit Q22 is at a high level, that is, distribution 1 or 0, and the node SA21 is at a high level (distribution 1), the NMOS transistor NT31. , NT32, NT28 are held conductive, the second storage node N21b of the latch circuit Q21 is pulled to the ground level, and the latch data of the latch circuit Q21 is switched from the low level to the high level.
In other cases, the NMOS transistor NT31 or NT28 is held in a non-conductive state, and the latch data of the latch circuit Q21 does not change.
That is, the latch data when reading is performed with the selected word line voltage VRD1 is as follows.
Distribution 3: {Q22, Q21} = {H, H}
Distribution 2: {Q22, Q21} = {H, L}
Distribution 1: {Q22, Q21} = {L, H}
Distribution 0: {Q22, Q21} = {L, L}
[0070]
Thus, the read operation is completed.
[0071]
As described above, according to the first embodiment, all bit line voltages are set to the power supply voltage V before writing._CC, The bit line is discharged at high speed by discharging the bit line through the NMOS transistors NT25 and NT26 connected to the second storage nodes N21b and N22b of the latch circuits Q21 and Q22. The bit line voltage connected to the write inhibit voltage is the power supply voltage V_CCBy reducing the threshold voltage Vth of the drain-side selection gate and providing a margin for self-boost, and writing in parallel, this allows the bit line charge before data writing. As a result, the time is shortened, and as a result, the entire writing time can be shortened, and verify reading and normal reading can be performed at high speed.
[0072]
Second embodiment
FIG. 6 is a circuit diagram showing a second embodiment of the nonvolatile semiconductor memory device according to the present invention.
The second embodiment is different from the circuit shown in FIG. 1 according to the first embodiment in that an NMOS transistor NT44 is connected between the NMOS transistors NT23 and NT25, and the gate electrode of the NMOS transistor NT44 is connected to the latch circuit Q22. And the source of the NMOS transistor NT25 is connected not to the ground line but to a voltage source of a positive voltage VB (0 <VB <Vcc−VthDSG (B)). is there.
In the second embodiment, the bit line voltage at the time of writing is controlled at this portion.
Other configurations are the same as those of the circuit of FIG.
[0073]
In such a configuration, when the latch data of the latch circuits Q22 and Q21 is {Q22, Q21} = {H, H} and the write data is “11”, the second storage nodes N21b and N22b of the latch circuits Q21 and Q22 are used. Are both at the low level, the NMOS transistors NT25 and NT26 are both kept non-conductive, and the bit line voltage is the power supply voltage V_CCRetained.
[0074]
  When the latch data of the latch circuits Q22 and Q21 is {Q22, Q21} = {H, L} and the write data is “10”, the second storage node N of the latch circuit Q22.22Since b is at a low level and the first storage node N22a of the latch circuit Q22 and the second storage node N21b of the latch circuit Q21 are at a high level, the NMOS transistor NT26 is held in a non-conductive state, and the NMOS transistors NT44, NT25 is held conductive, and the bit line voltage is VB.
[0075]
When the latch data of the latch circuits Q22, Q21 is {Q22, Q21} = {L, H}, {L, L} and the write data is “01”, “00”, the first storage node N22a of the latch circuit Q22 Is at the low level and the second storage node N22a of the latch circuit Q22 is at the high level, the NMOS transistor NT44 is held in the non-conductive state, the NMOS transistor NT26 is held in the conductive state, and the bit line voltage is at the ground level. It becomes.
[0076]
Then, when the word line is raised after setting the bit line to the above voltage, the channel voltage becomes as follows.
That is, when the latch data of the latch circuits Q22 and Q21 is {Q22, Q21} = {H, H} and the write data is “11”, the channel is boosted to the write inhibit voltage (about 8V) by self-boost.
When the latch data of the latch circuits Q22 and Q21 is {Q22, Q21} = {H, L} and the write data is “10”, the channel voltage is VB.
When the latch data of the latch circuits Q22 and Q21 is {Q22, Q21} = {L, H}, {L, L} and the write data is “01” and “00”, the channel voltage is at the ground level.
[0077]
At this time, when the word line voltage at the start of writing is VPGM + VB, the voltage applied between the gate and the channel of the cell whose write data is “10” is VPGM, which is not different from the conventional one.
On the other hand, the voltage applied between the gate and the channel of the cell whose write data is “01” or “00” is VPGM + VB, and a higher electric field is applied between the floating gate and the channel.
However, in the case of write data “01” or “00”, since the write level is high, it is difficult to imagine a situation in which even the fast write memory cell suddenly exceeds the determination level in the first write.
Further, assuming that the ISPP step width is ΔV, writing of write data “01” and “00” is started from the preceding ISPP write pulse by VB / ΔV in FIG. 7 as compared with the first embodiment. On the other hand, since it is the cell of the write data “00” that defines the entire writing time, the entire writing time is further shortened compared to the first embodiment (see FIG. 7). ).
[0078]
【The invention's effect】
As described above, according to the nonvolatile semiconductor memory device of the present invention, the self-boost margin is increased, the bit line charging time before data writing is shortened, the entire writing time can be shortened, and further the verifying is performed. There is an advantage that reading and normal reading can be performed at high speed.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a first embodiment of a nonvolatile semiconductor memory device according to the present invention.
FIG. 2 is a timing chart for explaining a write operation of the circuit of FIG. 1;
FIG. 3 is a diagram showing a write sequence of the circuit of FIG. 1;
4 is a timing chart for explaining a verify read operation of the circuit of FIG. 1;
FIG. 5 is a timing chart for explaining a read operation of the circuit of FIG. 1;
FIG. 6 is a circuit diagram showing a second embodiment of a nonvolatile semiconductor memory device according to the present invention.
7 is a diagram showing a write sequence of the circuit of FIG. 6; FIG.
FIG. 8 is a diagram showing the relationship between the threshold voltage Vth level and data contents when recording data consisting of 2 bits and having 4 values in one memory transistor in a NAND flash memory;
FIG. 9 is a circuit diagram showing a main configuration of a conventional NAND flash memory.
10 is a timing chart for explaining the operation of the circuit of FIG. 9;
FIG. 11 is a diagram for explaining a conventional problem.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... Nonvolatile semiconductor memory device, 11 ... Memory array, A0, A1 ... Memory string, WL0-WL15 ... Word line, BL0, BL1 ... Bit line, 12 ... Write / read control circuit, 20 ... Stabilization circuit, NT21- NT44 ... NMOS transistor, PT21, PT22 ... PMOS transistor, INV21 ... inverter, Q21, Q22 ... latch circuit.

Claims (6)

The amount of charge stored in the charge storage unit changes according to the voltage applied to the word line and the bit line, the threshold voltage changes according to the change, and data having a value according to the threshold voltage is stored. A non-volatile semiconductor memory device having a memory cell for storing, and writing multi-bit data of three or more values into the memory cell in page units,
Precharge means for precharging all bit lines to a predetermined voltage before writing;
A write control circuit that has a latch circuit that latches write data, discharges a bit line selected according to an address according to the latch data, and performs writing in parallel;
The write control circuit
A plurality of latch circuits for one bit are provided corresponding to each bit line, and each of the latch circuits has a first storage node that holds a latch data level and a second storage node that holds its inverted level. And then
Provided corresponding to the respective latch circuits, bit connects the ground potential with the selected bit line when the second first level level is predetermined storage nodes of each latch circuit corresponding to the write data A plurality of switch means for discharging the wire ;
During verify read,
A first signal supplied in accordance with a threshold level to be verified, a second signal indicating whether or not a memory cell to be written has exceeded a target threshold, and another latch circuit Depending on the level of the first storage node, the level of the second storage node of each latch circuit is set to the second level that makes the switch means conductive or non-conductive. A process to decide on one,
Depending on the first signal and the second signal, the second storage node of one of the plurality of latch circuits is set to either the first level or the second level. And determining the level of the first storage node of the one latch circuit determined according to the determined level of the second storage node, the first signal, and the second signal. In response, a process of determining the level of the second storage node of another latch circuit of the plurality of latch circuits to be either the first level or the second level;
A circuit for performing
Whether or not rewriting is performed by determining whether or not writing to the memory cell is completed during a writing operation depending on whether or not the second storage nodes of the plurality of latch circuits have the same second level. nonvolatile semiconductor memory device having a determination circuit for determining Diseases. The determination of whether a sufficient write every write bit during the write operation, the nonvolatile semiconductor memory device according to claim 1, further comprising a verify read circuit performed sequentially raised to a high level word line voltage from a low level . The amount of charge stored in the charge storage unit changes according to the voltage applied to the word line and bit line, the threshold voltage changes according to the change, and data of a value corresponding to the threshold voltage is stored. A plurality of memory cells are connected, and one end and the other end of the memory strings are connected in the form of a matrix and connected to a bit line and a ground line via a select transistor whose conduction state is controlled according to the gate voltage. A non-volatile semiconductor memory device in which control gates of memory cells in a row are connected to a common word line, and multi-bit data of three or more values is written to the memory cells in page units using self-boost,
Precharge means for precharging all bit lines to a predetermined voltage before writing;
A write control circuit that has a latch circuit that latches write data, discharges a bit line selected according to an address according to the latch data, and performs writing in parallel;
The write control circuit
Provided corresponding to the respective latch circuits, bit connects the ground potential with the selected bit line when the second first level level is predetermined storage nodes of each latch circuit corresponding to the write data A plurality of switch means for discharging the wire ;
During verify read,
A first signal supplied in accordance with a threshold level to be verified, a second signal indicating whether or not a memory cell to be written has exceeded a target threshold, and another latch circuit Depending on the level of the first storage node, the level of the second storage node of each latch circuit is set to the second level that makes the switch means conductive or non-conductive. A process to decide on one,
Depending on the first signal and the second signal, the second storage node of one of the plurality of latch circuits is set to either the first level or the second level. And determining the level of the first storage node of the one latch circuit determined according to the determined level of the second storage node, the first signal, and the second signal. In response, a process of determining the level of the second storage node of another latch circuit of the plurality of latch circuits to be either the first level or the second level;
A circuit for performing
Whether or not rewriting is performed by determining whether or not writing to the memory cell is completed during a writing operation depending on whether or not the second storage nodes of the plurality of latch circuits have the same second level. nonvolatile semiconductor memory device having a determination circuit for determining Diseases. 4. The nonvolatile semiconductor memory device according to claim 3, further comprising: a verify read circuit that determines whether or not writing is sufficient for each write bit during the write operation by sequentially increasing the word line voltage from a low level to a high level. . The amount of charge stored in the charge storage unit changes according to the voltage applied to the word line and bit line, the threshold voltage changes according to the change, and data of a value corresponding to the threshold voltage is stored. A method of writing data in a nonvolatile semiconductor memory device having a memory cell that writes multi-bit data of three or more values to the memory cell in page units,
A first step of precharging all bit lines to a predetermined voltage before writing;
At the time of writing , latches of a plurality of latch circuits for one bit each having a first storage node corresponding to each bit line and a second storage node holding its inversion level are selected according to the address. A second step of discharging according to data and performing writing in parallel,
In the second step,
When the level of the second storage node of the latch circuit corresponding to the write data is a predetermined first level, the switch means connects the selected bit line and the ground potential to discharge the bit line ,
During verify read,
A first signal supplied in accordance with a threshold level to be verified, a second signal indicating whether or not a memory cell to be written has exceeded a target threshold, and another latch circuit Depending on the level of the first storage node, the level of the second storage node of each latch circuit is set to the second level that makes the switch means conductive or non-conductive. A process to decide on one,
Depending on the first signal and the second signal, the second storage node of one of the plurality of latch circuits is set to either the first level or the second level. And determining the level of the first storage node of the one latch circuit determined according to the determined level of the second storage node, the first signal, and the second signal. In response, a process of determining the level of the second storage node of another latch circuit of the plurality of latch circuits to be either the first level or the second level;
And
Non-volatile semiconductor memory device data writing for determining whether rewriting is performed or not depending on whether the level of the second storage node of the plurality of latch circuits has reached the first level or the second level Method. The amount of charge stored in the charge storage unit changes according to the voltage applied to the word line and bit line, the threshold voltage changes according to the change, and data of a value corresponding to the threshold voltage is stored. A plurality of memory cells are connected, and one end and the other end of the memory strings are connected in the form of a matrix and connected to a bit line and a ground line via a select transistor whose conduction state is controlled according to the gate voltage. A data writing method for a nonvolatile semiconductor memory device in which control gates of memory cells in a row are connected to a common word line, and multi-bit data of three or more values is written in memory cells in units of pages using self-boost,
A first step of precharging all bit lines to a predetermined voltage before writing;
At the time of writing , latches of a plurality of latch circuits for one bit each having a first storage node corresponding to each bit line and a second storage node holding its inversion level are selected according to the address. A second step of discharging according to data and performing writing in parallel,
In the second step,
When the level of the second storage node of the latch circuit corresponding to the write data is a predetermined first level, the switch means connects the selected bit line and the ground potential to discharge the bit line ,
During verify read,
A first signal supplied in accordance with a threshold level to be verified, a second signal indicating whether or not a memory cell to be written has exceeded a target threshold, and another latch circuit Depending on the level of the first storage node, the level of the second storage node of each latch circuit is set to the second level that makes the switch means conductive or non-conductive. A process to decide on one,
Depending on the first signal and the second signal, the second storage node of one of the plurality of latch circuits is set to either the first level or the second level. And determining the level of the first storage node of the one latch circuit determined according to the determined level of the second storage node, the first signal, and the second signal. In response, a process of determining the level of the second storage node of another latch circuit of the plurality of latch circuits to be either the first level or the second level;
And
Non-volatile semiconductor memory device data writing for determining whether rewriting is performed or not depending on whether the level of the second storage node of the plurality of latch circuits has reached the first level or the second level Method.

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