JP2000251485A - Non-volatile semiconductor memory and its data write-in method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten a write-in time for multi-value data by applying a bit line voltage in accordance with write-in data to a bit line connected to a memory cell as soon as threshold voltage of a memory cell reaches a voltage of an intermediate program state. SOLUTION: This device is provided with a memory cell having an erasing state and a program state of 2n-1 pieces to store data of (n) bits (n>=2). At the time of write-in operation, write-in pulse voltage applied to a word line is increased stepwise with the prescribed step width from the prescribed initial voltage in accordance with the number of write-in times, and data are written in a selected memory cell in page unit. At the time, it is detected that threshold voltage of a memory cell reaches a voltage of the prescribed intermediate program state being shallower than that of a program state being the shallowest voltage program state out of program states of 2n-1 pieces. As soon as threshold voltage of a memory cell reaches the voltage of this intermediate program state, the bit line voltage in accordance with write-in data is applied to a bit line connected to the memory cell.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device and a data writing method thereof, and
The present invention is suitable for application to a multi-level nonvolatile semiconductor memory device in which two-bit or more multi-level data is stored in one memory cell.

[0002]

2. Description of the Related Art Conventionally, flash memories for writing and reading data in page units, for example, NA
The ND type flash memory is used for storing a large amount of data. In recent years, as the degree of integration of flash memory chips has been improved and the storage capacity has been increasingly increased, a multi-value storage method for storing multi-value data of 2 bits or more in one memory cell has been developed. ing.

FIG. 6 shows the distribution of the threshold voltage of a memory cell and the contents of the stored data in a four-level flash memory in which two-bit data having four values are stored in one memory cell. The correspondence is shown. In FIG. 6, the vertical axis of the graph indicates the threshold voltage Vth of the memory cell, and the horizontal axis of the graph indicates the distribution frequency of the memory cell.

As shown in FIG. 6, a threshold voltage Vth of a memory cell in a four-level flash memory has four states corresponding to data "00", "01", "10", and "11". . That is, in FIG. 6, distribution A is a distribution of memory cells in which data "00" is written and brought into a third positive threshold voltage program state, and distribution B
Is a distribution of memory cells in which data "01" is written and brought into a second positive threshold voltage programmed state;
The distribution C is a distribution of memory cells in which data "10" is written and brought into a first positive threshold voltage programmed state. The distribution width of these program states is, for example, 0.2
About V. The distribution D is a distribution of the memory cells in which the data “11” is written and in the erased state of the negative threshold voltage. In FIG. 6, the selected word line voltages corresponding to each program state at the time of the write verify operation are indicated by VVF1, VVF2, VVF3, and the selected word line voltages corresponding to each program state at the time of the read operation are VRD1,
VRD2 and VRD3. The relationship is VVF3
>VRD3>VVF2>VRD2>VVF1> VRD1. For example, VVF3 = 2.8V, VRD3 = 2.4V,
VVF2 = 1.6V, VRD2 = 1.2V, VVF1 = 0.4
V, VRD1 = 0V.

In this four-valued flash memory, data writing and reading are performed based on the above-described correspondence between the threshold voltage of the memory cell and the content of the stored data.

[0006]

However, the multi-level flash memory described above has a problem that the data read time and the write time are longer than the binary flash memory. The reason will be described below.

In a conventional data writing method for a multi-level flash memory, a so-called multi-level parallel writing method, in which multi-level data is written at once by changing a bit line voltage in accordance with write data, is predominant. . In general, at the time of this writing, so-called ISPP (Incremental Step Pulse Programming) is performed in which writing is sequentially performed by gradually increasing a write pulse voltage applied to a word line from a predetermined initial voltage with a fixed step width.
The method is adopted. In this case, for each write operation, write is performed by applying a bit line voltage corresponding to write data to the bit line, and each time write verify for confirming a program state (threshold voltage) of the memory cell is executed. You. Then, the above-described write operation and verify operation are repeated until writing to all the memory cells in the page is completed.

In a verify operation, a predetermined comparison voltage is applied to a selected word line in a state where a bit line is precharged to a predetermined potential, and the presence or absence of a cell current at this time is determined by a sense amplifier connected to the bit line. The threshold voltage of the memory cell is determined by the detection by the circuit. That is, when a comparison voltage higher than the threshold voltage of the memory cell is supplied to its gate and a cell current flows, the voltage of the bit line drops. When a comparison voltage lower than the threshold voltage of the memory cell transistor is supplied to its gate,
No cell current flows, and the bit line is held at the precharge level. At the time of the verify operation, the threshold voltage of the memory cell is determined based on this relationship. At this time, in the multilevel flash memory, in order to determine the 2 ⁿ -1 pieces of program state corresponding to the stored data of n bits, 2 ⁿ a comparison voltage applied to a selected word line
It is necessary to sequentially determine the threshold voltage while changing the threshold voltage in one step. Specifically, for example, in a four-valued flash memory having a correspondence between the threshold voltage and the stored data content as shown in FIG. 6, the comparison voltage applied to the selected word line is, for example, VVF3 → VVF2 → VVF1 The threshold voltage of the memory cell is determined while gradually decreasing the order of the steps.

[0009] Similarly, when a read operation, in order to determine the 2 ⁿ -1 pieces of program state corresponding to the stored data of n bits, 2 ⁿ a comparison voltage applied to a selected word line
It is necessary to sequentially determine the threshold voltage by changing the threshold voltage in one step. For example, in a four-level flash memory having a correspondence relationship between the threshold voltage and the stored data content as shown in FIG. The threshold voltage of the memory cell is determined while the comparison voltage applied to the word line is gradually reduced in the order of, for example, VRD3 → VRD2 → VRD1.

As described above, in the conventional multi-level flash memory, it is necessary to change the comparison voltage applied to the word line in a stepwise manner at the time of a read operation or a verify operation in accordance with the number of program states. , The comparison voltage is 1
The number of comparisons is increased as compared with a binary flash memory that can be completed, and the total read operation time and the total write time increase. For example, at present, a conventional well-known successive approximation type quaternary flash memory requires about four to five times as long a read time and a write time as a binary flash memory. In particular, the increase in the write time in a multi-level flash memory is
Along with the problem of a decrease in reliability (a decrease in data retention characteristics due to multi-valued data), it has become a major obstacle to its practical use.

Accordingly, an object of the present invention is to provide a nonvolatile semiconductor memory device and a data writing method thereof capable of shortening the writing time when writing n-bit (n ≧ 2) multi-valued data into a memory cell. Is to do.

[0012]

In order to achieve the above object, a first aspect of the present invention is to change the amount of charge stored in a charge storage section according to a voltage applied to a word line and a bit line. The threshold voltage changes according to the change, so that the data of the value corresponding to the threshold voltage is stored, and the erase state and 2 ⁿ are stored in order to store the data of n bits (where n ≧ 2). -1 memory state having a programmed state, and in a write operation, a write pulse voltage applied to a word line is increased stepwise from a predetermined initial voltage by a predetermined step width according to the number of times of writing, and is selected. A nonvolatile semiconductor memory device in which data is written in memory cells in units of pages, wherein a predetermined initial bit line voltage is applied to a bit line while a write pulse voltage is applied to a word line. To write data to the memory cell, this time, it is detected that has reached the predetermined intermediate program state shallowest than shallower program state of the threshold voltage is 2 ⁿ -1 pieces of program state of the memory cell Detecting means; counting means for counting the number of times of writing since the start of writing; and when the threshold voltage of the memory cell reaches the intermediate program state, a bit line voltage corresponding to the write data is applied to a bit line connected to the memory cell. And a bit line voltage applying means for applying the voltage.

According to a second aspect of the present invention, the amount of charge stored in the charge storage portion changes according to the voltage applied to the word line and the bit line, and the threshold voltage changes according to the change. Has a memory cell having an erased state and 2 ⁿ -1 programmed states for storing data of a value corresponding to the threshold voltage and for storing n-bit (where n ≧ 2) data. In a write operation, a write pulse voltage applied to a word line is gradually increased from a predetermined initial voltage by a predetermined step width according to the number of times of writing, and data is written in a selected memory cell in page units. a data writing method for a nonvolatile semiconductor memory device, the shallowest programmed state of the threshold voltage is 2 ⁿ -1 pieces of program state of the memory cell from the write start Until a predetermined intermediate program state shallower is reached, a first write step of writing data to a memory cell by applying a predetermined initial bit line voltage to a bit line while applying a write pulse voltage to a word line is performed. In addition, each time, a verifying step for detecting whether or not the threshold voltage of the memory cell has reached the intermediate program state is performed, and when the threshold voltage of the memory cell reaches the intermediate program state, A second writing step of writing data by applying a bit line voltage according to write data to a connected bit line is performed.

In the present invention, the non-volatile semiconductor storage device is typically a NAND flash memory.

In the present invention, the 2 ⁿ -1 program states are states each having a positive threshold voltage having a different level, and the erase state is a state having a negative threshold voltage. Further, the initial bit line voltage is selected to be a predetermined voltage higher than the bit line voltage corresponding to the write data in the shallowest program state and lower than the initial voltage of the write pulse voltage applied to the word line at the time of writing. The intermediate program state is a program state between the shallowest program state and the erased state. Specifically, for example, the intermediate program state is a program state in which the threshold voltage of a memory cell is set to 0V.

In the present invention configured as described above, when writing n bits (where n ≧ 2) of data to a memory cell, the threshold voltage of the memory cell is 2 ⁿ −1 from the start of writing. Until a predetermined intermediate program state shallower than the shallowest program state among the program states is reached, data is written by applying a predetermined initial bit line voltage to the bit line, and each time the threshold of the memory cell is reached. Verification is performed by detecting whether the value voltage has reached the intermediate program state. As a result of this verification, when it is determined that the threshold voltage of the memory cell has reached the intermediate program state, a bit line voltage corresponding to the write data is applied to the bit line connected to the memory cell, and substantially Multi-level data is written, and in this single write, the threshold voltage of the memory cell is separated into 2 ⁿ -1 program states corresponding to the write data. By doing so, when writing n-bit multi-level data to a memory cell, the number of comparisons of the threshold voltage of the memory cell during the verify operation is 1
Times (binary verification is enough)
The total writing time is significantly reduced as compared with the conventional case.

In the first aspect of the present invention, the detecting means typically applies a predetermined comparison voltage capable of discriminating the intermediate program state to the word line, and determines whether there is a cell current at this time. By detecting, it is detected whether or not the threshold voltage of the memory cell has reached the intermediate program state. In the second aspect of the present invention, in the verifying step, typically, a predetermined comparison voltage capable of determining an intermediate program state is applied to a word line to detect the presence or absence of a cell current at this time. Thereby, it is detected whether or not the threshold voltage of the memory cell has reached the intermediate program state. At this time, the comparison voltage applied to the word line is a voltage between the threshold voltage of the memory cell in the shallowest program state and the threshold voltage of the memory cell in the erased state. Specifically, for example, When the threshold voltage of the memory cell in the intermediate program state is set to 0V, it is selected to be 0V.

In the first aspect of the present invention, the bit line voltage applying means preferably decreases the bit line voltage according to the write data stepwise with a predetermined step width according to the number of times of writing. According to the second aspect of the present invention, preferably, the bit line voltage corresponding to the write data to be applied to the bit line in the second write step is reduced stepwise by a predetermined step width according to the number of write operations. Let it. At the time of writing, the amount of change in the threshold voltage of the memory cell when the bit line voltage is switched from the initial bit line voltage to the bit line voltage according to the write data depends on the memory cell characteristics. Specifically, at this time, the amount of change in the threshold voltage of the memory cell becomes larger as the memory cell is written faster, and becomes smaller as the memory cell is written later. On the other hand, when the bit line voltage is switched from the initial bit line voltage to the bit line voltage according to the write data, the change amount of the threshold voltage of the memory cell is the change amount of the bit line voltage (the initial bit line voltage and the write data (The difference from the bit line voltage according to the above). Specifically, at this time, the amount of change in the threshold voltage of the memory cell increases as the amount of change in the bit line voltage increases, and decreases as the amount of change in the bit line voltage decreases. Therefore, the present invention utilizes the fact that the number of times of writing until reaching the intermediate program state is smaller for a memory cell with a faster writing and is larger for a memory cell with a slower writing. The voltage is reduced according to the number of times of writing. By doing so, when the bit line voltage is switched from the initial bit line voltage to the bit line voltage according to the write data, the amount of change in the bit line voltage can be reduced in a memory cell in which writing is fast. Since the amount of change in the bit line voltage can be increased in a memory cell in which writing is slow, the amount of change in the threshold voltage of the memory cell at this time can be made substantially constant regardless of the memory cell characteristics. Thereby, the distribution width of the memory cells in each program state can be narrowed. In this case, the step width for decreasing the bit line voltage according to the write data in accordance with the number of times of writing is obtained in advance by using statistical data.

In the first aspect of the present invention, preferably, the nonvolatile semiconductor memory device applies a bit line voltage corresponding to write data to a memory cell where the threshold voltage is detected to have reached the intermediate program state. After the writing by applying the voltage, the writing control unit further includes a writing control unit for inhibiting the writing of data to the memory cell. In the second invention of the present invention, preferably, in the second writing step, a bit line voltage according to the write data is applied to the memory cell whose threshold voltage has been detected to have reached the intermediate program state. After writing, the data writing to the memory cell is prohibited. As a result, excessive writing to the memory cell whose threshold voltage has reached a desired program state is prevented.

In the first invention of the present invention, preferably, the nonvolatile semiconductor memory device further comprises a confirmation means for confirming whether or not desired data has been written to the memory cell after completion of writing in page units. Have In the second aspect of the present invention, preferably, after the writing is completed, a confirmation step for confirming whether desired data has been written to the memory cell is performed.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic diagram illustrating a configuration example of a NAND flash memory according to an embodiment of the present invention.

As shown in FIG. 1, this NAND flash memory comprises a memory cell array 1, a main row decoder 2, a sub-row decoder 3, a booster circuit (level conversion circuit) 4, a data latch circuit 5, and a bit line voltage generation circuit 6. , A control circuit 7 and the like.

The memory cell array 1 includes a plurality of NAND strings arranged in a matrix in a row direction and a column direction, and word lines, bit lines, selection gate lines, source lines, and the like connected to these NAND strings. ing. The NAND string includes a predetermined number of memory cells and select transistors connected in series. This memory cell array 1 is usually divided into a plurality of blocks in the column direction. Within each block,
A predetermined number of NAND strings sharing a word line and a select gate line in the row direction are arranged in parallel. These blocks are erasing units when erasing data stored in the memory cells. This memory cell array 1
The specific configuration will be described later in detail with reference to FIG.

The main row decoder 2 includes an address decoder, a level conversion circuit, transfer gates for word lines and select gate lines. Main row decoder 2
Drives only the transfer gate in the selected block and drives the word line and the selection gate line in accordance with the address decode signal. Sub row decoder 3 outputs a signal whose level has been converted to a predetermined level by boosting circuit 4 according to the operation mode and the selection information. As the booster circuit 4, for example, one for a program voltage (VPGM) applied to a selected word line during a write operation, one for a write pass voltage (Vpass) applied to a non-selected word line during a write operation, and one for a write verify operation And a read pass voltage (P5V) applied to a non-selected word line during a write verify operation and a read operation. An output from the sub-row decoder 3 is supplied to a word line and a selection gate line of the memory cell array 1 via the transfer gate of the main row decoder 2.

The data latch circuit 5 is connected to the bit lines of the memory cell array 1, and is roughly composed of a bit line voltage setting circuit, a latch circuit, a verify / read control circuit, and the like. The bit line voltage setting circuit of the data latch circuit 5 is connected to a bit line voltage supply line derived from the bit line voltage generation circuit 6. Specific configurations of the data latch circuit 5 and the bit line voltage generation circuit 6 will be described later in detail with reference to FIG.

The control circuit 7 is for controlling the operation of the NAND flash memory. From the control circuit 7, signal lines for supplying control signals to the main row decoder 2, the sub row decoder 3, the booster circuit 4, the data latch circuit 5, and the like are led out.

Here, a specific configuration of the memory cell array 1 of the NAND flash memory will be described. FIG. 2 is an equivalent circuit diagram illustrating a configuration example of the memory cell array 1.

As shown in FIG. 2, in the memory cell array 1, a plurality of bit lines are arranged in parallel, and a NAND string is connected to each bit line. That is, the NAND string A0 is connected to the bit line BL0, and the NAND string A1 is connected to the bit line BL1. In FIG. 2, bit lines subsequent to the bit line BL2 are not shown.

The NAND string A0 includes a selection transistor DS0, memory cells M _{0-0 to} M _15-0, and a selection transistor SS0. The NAND string A1 includes a selection transistor DS1, a memory cell M
_{0-1 to} M _15-1 and a selection transistor SS1. These NAND strings A0, A1
Are NAND strings sharing a word line and a select gate line and arranged in the same block.

[0030] In the NAND string A0, the drain of the memory cell M _15-0 via the selection transistor DS0 is connected to the bit line BL0, source line SL source of the memory cell M _0-0 via the selection transistor SS0 It is connected. In the NAND string A1,
The drain of the memory cell M _15-1 is connected to the selection transistor DS1.
And the memory cell M _0-1
Is connected to the source line S via the selection transistor SS1.
L.

The memory cells M _{0-0 to} M _15-0 and the memory cells M _{0-1 to} M _15-1 are stacked gate type n-channel M
It consists of OS transistors and each functions as a 2-bit memory cell. The control gates of these memory cells M _{0-0 to} M _15-0 and memory cells M _{0-1 to} M _15-1 are connected to word lines WL0 to WL15, respectively. The gates of the selection transistors DS0 and DS1 are connected to a selection gate line DSG, and the selection transistors SS0 and S1
The gate of S1 is connected to the select gate line SSG.
NAND strings connected to each bit line after the bit line BL2 not shown have the same connection relationship as described above.

Next, specific configurations of the data latch circuit 5 and the bit line voltage generation circuit 6 of the NAND flash memory will be described. FIG. 3 is a schematic diagram illustrating a configuration example of the data latch circuit 5 and the bit line voltage generation circuit 6.

As shown in FIG. 3, the data latch circuit 5
Has a bit line voltage setting circuit 5a, a latch circuit 5b, and a verify / read control circuit 5c.

The bit line voltage setting circuit 5a of the data latch circuit 5 includes, for example, transistors NT1 to NT10 comprising n channel MOS transistors and a p channel M
Transistors PT1 to PT3 composed of OS transistors
It consists of.

[0035] In the bit line voltage setting circuit 5a, node SA and the power supply voltage Vcc (V _CC, for example 3.3
The transistor PT1 is connected to the supply line V). The control signal V is applied to the gate of the transistor PT1.
ref is supplied. The transistor NT1 is connected between the node SA and the ground line. The control signal DISC is supplied to the gate of the transistor NT1.

The drain of the transistor NT3 and the drain of the transistor PT3 are connected to the node SA via a transfer gate composed of the transistors NT2 and PT2. The control signal PRG is supplied to the gate of one transistor NT2 constituting the transfer gate, and the control signal / P which is an inverted signal of the control signal PRG is supplied to the gate of the other transistor PT2.
RG (/ represents inversion) is supplied.

The source of the transistor PT3 has the voltage VB0
(Initial bit line voltage) supply line (not shown). The source of the transistor NT3 is connected to the drains of the transistors NT4, NT6, NT8. The transistors NT4 and NT5 are connected in series between the source of the transistor NT3 and the bit line voltage supply line VBL3. A transistor N is connected between the source of the transistor NT3 and the bit line voltage supply line VBL2.
T6 and NT7 are connected in series. Transistor N
Transistors NT8 and NT9 are connected in series between the source of T3 and the bit line voltage supply line VBL1. Transistor NT1 between node SA and the bit line
0 is connected. The control signal BC is supplied to the gate of the transistor NT10.

Here, the bit line voltage supply line VBL
1, VBL2 and VBL3 are voltage supply lines used to supply bit line voltages corresponding to write data to bit lines, respectively.
Is derived from Specifically, in this case, the write data of the bit line voltage supply line VBL1 is “10”.
, The bit line voltage VB (DATA
= "10"), and the bit line voltage supply line VBL2 is a supply line for the bit line voltage VB (DATA = "01") to be applied to the bit line when the write data is "01". The bit line voltage supply line VBL3 is a supply line for the bit line voltage VB (DATA = "00") to be applied to the bit line when the write data is "00". However, VB0> VB (DATA = "10")> VB (DATA = "01")> V
B (DATA = "00"). In this embodiment, the bit line voltage VB (DATA = 1
0 "), VB (DATA =" 01 ") and VB (DATA =" 00 ")
It is a characteristic that the voltage decreases with a predetermined step width as the number of times of writing N increases.

In the following, the bit line voltages VB (DATA = “10”) and VB that change (decrease) according to the number N of write operations
(DATA = "01") and VB (DATA = "00")
B1 (N), VB2 (N), VB3 (N) (however, VB1
(1)> VB1 (2)>...> VB1 (N), VB2 (1)>
VB2 (2) >>...> VB2 (N), VB3 (1)> VB3
(2) >> VB3 (N)).
Note that these voltages VB1 (N), VB2 (N), VB3
The initial voltages VB1 (1), VB2 (1), VB3 (1) and the step width of (N) are obtained from statistical data.

The latch circuit 5b of the data latch circuit 5
For example, the latch circuit LD1 includes an inverter U1 and an inverter U2, and the latch circuit LD0 includes an inverter U3 and an inverter U4.

In the latch circuit 5b, the latch circuit LD1 is for storing the data of the upper bit of the 2-bit data, and in this case, the inverter U
The common connection point between the output terminal of the inverter 1 and the input terminal of the inverter U2 is a storage node D1, and the common connection point between the input terminal of the inverter U1 and the output terminal of the inverter U2 is an inverted storage node / D1. The latch circuit LD0 is for storing lower-order bit data of the 2-bit data. In this case, a common connection point between the output terminal of the inverter U3 and the input terminal of the inverter U4 is a storage node D0, Input terminal of inverter U3 and inverter U
The common connection point with the output terminal 4 is an inverted storage node / D0. Storage node D1 of latch circuit LD1 and storage node D0 of latch circuit LD0 are each connected to a data bus line.

Inverting storage node / D1 of latch circuit LD1
Are connected to the gates of transistors NT4 and NT6, and storage node D1 is connected to the gate of transistor NT8. Inverted storage node / D0 of latch circuit LD0 is connected to the gates of transistors NT5 and NT9, and storage node D0 is connected to the gate of transistor NT7.

The verify / read control circuit 5c of the data latch circuit 5 includes, for example, a latch circuit LQ including an inverter U5 and an inverter U6, an n-channel MOS
Transistors NT11 to NT20 comprising transistors
It is composed of

In the verify / read control circuit 5c, the latch circuit LQ operates as a flip-flop for determining the threshold voltage of the memory cell during the verify operation. In this case, the output terminal of the inverter U5 and the inverter A common connection point between the input terminal of U6 and the input terminal of the inverter U5 is set as a storage node Q, and a common connection point between the input terminal of the inverter U5 and the output terminal of the inverter U6 is set as an inverted storage node / Q.

The transistors NT11 and NT12 are connected in series between the inverted storage node / Q of the latch circuit LQ and the ground line. Transistors NT13 and NT14 are connected in series between storage node Q of latch circuit LQ and the ground line, and transistor NT15 is connected in parallel with transistor NT14 between the source of transistor NT13 and the ground line. . The transistor NT16 is connected between the storage node Q of the latch circuit LQ and the node SA. The control signal LAT1 is supplied to the gate of the transistor NT11.
The control signal LAT2 is supplied to the gate of the transistor 13, and the control signal LAT3 is supplied to the gate of the transistor NT16. The gate of the transistor NT12 is connected to the node SA. The gate of the transistor NT14 is connected to the inverted storage node / D0 of the latch circuit LD0, and the gate of the transistor NT15 is connected to the inverted storage node / D1 of the latch circuit LD1.

Inverting storage node / D1 of latch circuit LD1
Between the transistor and the ground line.
Are connected in series, and transistors NT19 and NT19 are connected between the inverted storage node / D0 of the latch circuit LD0 and the ground line.
T20 is connected in series. Transistor NT17
The control signal RD1 is supplied to the gate of the
The control signal RD0 is supplied to the gate of T19. The gate of the transistor NT18 and the gate of the transistor NT20 are connected to the node SA, respectively.

The bit line voltage generating circuit 6 includes a counter 1
1, a ROM 12, and D / A converters 13 to 15. The counter 11 counts, for example, the number N of times of writing since the start of writing during the writing operation. The count data of the counter 11 is input to the ROM 12. The ROM 12 outputs bit line voltage generation data corresponding to the count data using a predetermined conversion table. The bit line voltage generation data of the ROM 12 is D
/ A converters 13-15. D / A converter 13
To 15 generate a predetermined voltage signal by performing D / A conversion of the bit line voltage generation data. D / A converter 13
Is a bit line voltage supply line VBL as a voltage VB1 (N) corresponding to the bit line voltage VB (DATA = "10").
1 and the voltage signal of the D / A converter 14 is output to the bit line voltage supply line VBL2 as the voltage VB2 (N) corresponding to the bit line voltage VB (DATA = "01"), and the D / A
The voltage signal of the converter 15 is represented by a bit line voltage VB (DATA = 0
0 ") is output to the bit line voltage supply line VBL3 as a voltage VB3 (N).

Next, a method of writing data in the NAND flash memory according to the embodiment having the above-described configuration will be described. FIGS. 4 and 5 are schematic diagrams for explaining a data writing method of the NAND flash memory according to the embodiment. Here, FIG.
Shows the threshold voltage (change characteristic of the threshold voltage) of the memory cell after the N-th write operation, and FIG. 5 shows a setting example of the selected word line voltage and the bit line voltage at the N-th write operation Is shown. FIG. 4 also shows the correspondence between the threshold voltage distribution of the memory cells and the stored data in the NAND flash memory according to the embodiment.

As shown in FIG. 4, the threshold voltage Vth of a memory cell in this NAND flash memory is
It takes four states corresponding to data "00", "01", "10", and "11". That is, in FIG. 4, distribution A is a distribution of memory cells in which data "00" is written and brought into a programmed state of the third positive threshold voltage Vth (DATA = "00"), and distribution B is The distribution of the memory cells in which the data "01" is written to be in the program state of the second positive threshold voltage Vth (DATA = "01"). The distribution C is the distribution of the memory cells in which the data "10" is written. 1 positive threshold voltage Vth
This is the distribution of the memory cells in the programmed state (DATA = "10"). The distribution D is a distribution of the memory cells to which the data “11” is written and in the erased state of the negative threshold voltage Vth (DATA = “11”). The selected word line voltage corresponding to each program state at the time of the write verify operation and the read operation is, for example, the same as that in FIG. In this NAND flash memory, data is written based on the relationship shown in FIG. Also, in this data writing method,
ISPP for gradually increasing a write pulse voltage applied to a word line from a predetermined initial voltage by a predetermined step width
According to the method, data is written to the selected memory cell in page units, and the write operation and the verify operation are repeated until the write in page units is completed.

At this time, in the data writing method according to this embodiment, the program voltage is applied to the selected word line as a write pulse voltage from the start of writing until the threshold voltage of the memory cell reaches a predetermined intermediate program state. VPGM (N) (where N is the number of times of writing) is applied, and the write pass voltage Vpass is applied to unselected word lines.
While applying (N) (<VPGM (N), where N is the number of times of writing), a first writing step of writing data to a memory cell by applying an initial bit line voltage VB0 to a bit line is executed. Each time, a verify step is performed to detect whether the threshold voltage of the memory cell has reached the intermediate program state. The write operation is executed when the write data is other than “11” (when the latch data of the latch circuit 5b is (D1, D0) ０ (1, 1)), and when the write data is “11” ( Latch circuit 5
When the latch data of b is (D1, D0) = (1, 1), the bit line is set to a high impedance state and writing is prohibited.

Here, the intermediate program state is the shallowest program state among 2 ² −1 = 3 program states when 2-bit data is stored, that is, shallower than the program state corresponding to data “10”. Program state. More specifically, this intermediate program state is a state in which the threshold voltage is Vth (DATA = "10").
This is a program state between a program state (distribution C) corresponding to 10 "and an erase state (distribution D) corresponding to data" 11 "in which the threshold voltage is Vth (DATA =" 11 "). In this embodiment, for example, a program state in which the threshold voltage of the memory cell is set to 0 V is defined as an intermediate program state.

In the verify step, a predetermined threshold comparison voltage VVF is applied to the selected word line, and the presence or absence of the cell current at this time is detected, so that the threshold voltage Vth of the memory cell is changed to the intermediate program state (Vth = 0V) is detected. In this case, the threshold comparison voltage VVF applied to the selected word line is selected to be 0V.

In this verify step, if it is determined that the threshold voltage of the memory cell has reached the intermediate program state, the latch data (D1, D1) of the latch circuit 5b will be written in the next write operation for that memory cell.
0), the bit line voltage VB (DATA = "1") is applied to the bit line.
0 "), VB (DATA =" 01 "), or VB (DATA =" 00 "), and a second write step of writing data to the memory cell is performed. ,
This is a substantial multi-value data write step. By one write in the second write step, the threshold voltage of the memory cell is separated into a program state corresponding to the write data.

Hereinafter, with respect to the examples shown in FIGS. 4 and 5,
This will be specifically described. In the following, it is assumed that transistors and the like that are not specifically described in the description of the operation of the data latch circuit 5 are normally in an off state.

As shown in FIGS. 4 and 5, before the write operation is started, all the memory cells in the write page are in the erased state, and the threshold voltage is Vth (DATA = "11").
<0. When the control signal PRG is set to low level and the control signal / PRG is set to high level, the transistors NT2 and PT2 are turned off, and the bit line is disconnected from the bit line voltage supply line.

When the write operation is started in this state,
Prior to the actual write operation, write data is supplied to the latch circuit 5b via the data bus. Thereby, of the 2-bit data to be written to the memory cell,
The upper bit data is stored in the storage node D of the latch circuit LD1.
1 is set, and the lower bit data is latched by the latch circuit LD.
0 is set to the storage node D0.

The transistor PT1 is turned on by setting the control signal Vref to low level.
In this state, the control signal LAT1, which is a pulse signal, is set to a high level. Thereby, the transistor NT
11, NT12 is turned on. This allows
In verify / read control circuit 5c, inverted storage node / Q of latch circuit LQ is pulled to a low level, and storage node Q is set to a high level (Q = "1").

Subsequently, a control signal L which is a pulse signal
AT2 is set to a high level and the transistor N
T13 is turned on. At this time, when the write data is other than “11” (when the latch data of the latch circuit 5b is (D1, D0) ≠ (1, 1)), at least one of the transistor NT14 and the transistor NT15 is in an on state. Thereby, the storage node Q of the latch circuit LQ is inverted to a low level (Q = “0”). On the other hand, when the write data is "11" (the latch circuit 5b
(Latch data of (D1, D0) = (1, 1))
Indicates that the storage node Q of the latch circuit LQ is at a high level (Q
= "1").

At the time of the first write operation, the voltage VB1 (1) is supplied to the bit line voltage supply line VBL1, and the voltage VB2 is supplied to the bit line voltage supply line VBL2.
(1) is supplied, and the voltage VB3 (1) is supplied to the bit line voltage supply line VBL3.

Thereafter, the control signal Vref is set to the high level, and the transistor PT1 is turned off. Then, the control signal DISC is set to a high level to turn on the transistor NT1, and the control signal BC is set to a predetermined high level to turn on the transistor NT10. As a result, the bit line is grounded. Thereafter, the control signal DISC is switched to low level,
The bit line is disconnected from the ground line. Then, the control signal Vref is set to low level, and the bit line is charged to Vcc level.

Thereafter, the control signal PRG goes high,
The control signal / PRG is set to low level, and the transistors NT2 and PT2 are turned on. As a result, the bit line sets the latch data (D
1, D0) and latch data Q of verify / read control circuit 5c, and is connected to a predetermined bit line voltage supply line.

That is, the verify / read control circuit 5
When the latch data Q of c is Q = "0", the transistor PT3 is turned on, and the bit line is connected to the supply line of the initial bit line voltage VB0 regardless of the latch data (D1, D0) of the latch circuit 5b. Is done. When the latch data Q of the verify / read control circuit 5c is Q = "1", the transistor NT3 is turned on, and the bit line and the bit line voltage supply line according to the latch data (D1, D0) of the latch circuit 5b. The connection state with VBL1 to VBL3 changes as shown in (1) to (4). (1) (D
(1, D0) = (0,0), the transistor NT4
NT5 is turned on, and the bit line is connected to bit line voltage supply line VBL3. (2) (D1, D0) =
At (0, 1), the transistors NT6 and NT7 are turned on, and the bit line is connected to the bit line voltage supply line VBL.
2 is connected. (3) When (D1, D0) = (1, 0), the transistors NT8 and NT9 are turned on,
The bit line is connected to bit line voltage supply line VBL1. (4) When (D1, D0) = (1, 1), since the transistors NT4, NT5, NT6, and NT9 are off, the bit line is not connected to any bit line voltage supply line, and the precharge level It is left floating.

At the time of this first write operation, the latch data (D1, D0) of the latch circuit 5b becomes (D1, D0).
0) If (1, 1), the bit line is connected to the supply line of the initial bit line voltage VB0 because the latch data Q of the verify / read control circuit 5c is set to Q = "0". . Therefore, in this case, the initial bit line voltage VB0 is applied to the bit line. On the other hand, the latch data (D1, D0) of the latch circuit 5b is (D1, D
When (0) = (1, 1), the bit line is not connected to any of the bit line voltage supply lines VBL1 to VBL3, and is not connected to the supply line of the initial bit line voltage VB0. Therefore, in this case, the bit line is set to a high impedance state and writing is prohibited.

Thereafter, a program voltage VPGM (1) is applied as a write pulse voltage to a selected word line connected to the memory cell to be written among the word lines WL0 to WL15.
Is applied, and the write pass voltage Vpass (1) is applied to the other unselected word lines. Where VPGM
(1) and Vpass (1) are initial voltages of the program voltage VPGM (N) and the write pass voltage Vpass (N), which increase stepwise with a predetermined step width according to the number N of times of writing. In this case, the step width of the program voltage VPGM (N) and the write pass voltage Vpass (N) is set to dV (>
0), these are VPGM (N) = VPGM (1) + d
V × (N−1), Vpass (N) = Vpass (1) + dV ×
(N-1). However, VPGM (N)> Vpass (N)
> VB0.

In the first write operation, the latch data (D1, D0) of the latch circuit 5b is changed to (D1, D0).
In the case of ≠ (1, 1), as described above, the program voltage VPGM (1) is applied to the selected word line and the initial bit line voltage VB0 is applied to the bit line. (1) -VB0) (pulse width = several tens of μs) is applied. Then, charge is injected into the floating gate by this electric field, and the threshold voltage of the memory cell increases.

After writing to the selected memory cell, all word lines are set to the ground level. When the control signal PRG is set to low level and the control signal / PRG is set to high level, the transistors NT2 and PT2 are turned off, and the bit line and the bit line voltage supply line are disconnected. This gives 1
The second write operation ends. Here, as shown in FIG. 4, the threshold voltage of the fast-writing memory cell becomes Vth1 and the threshold voltage of the slow-writing memory cell becomes Vth2, as shown in FIG. . However, these threshold voltages Vth1 and Vth2
Satisfy the relationship of 0>Vth1>Vth2> Vth (DATA = "11").

Thereafter, the control signal DISC is set to the high level, and during this time, the bit line is grounded. And
After a lapse of a predetermined time, the control signal DISC is switched to the low level, and the verify operation is performed.

In the verify operation performed following the above-described write operation, the threshold voltage of the memory cell is determined by applying the threshold voltage VVF (= 0 V) to the selected word line, thereby performing the write operation. It is detected whether the threshold voltage of the memory cell has reached the intermediate program state.

In this case, first, after the control signal DISC is switched to the low level, before the verify operation is performed, the pulse-like control signal LAT3 is set to the high level and the transistor NT16 is turned on. At the same time, the control signals RD1 and RD0, which are pulse signals, are set to the high level, and the transistor NT1
7, NT19 is turned on.

At this time, verify / read control circuit 5
When the latch data Q of c is set to Q = "1", the transistors NT18 and NT20 are turned on, and the transistors NT17 and NT19 are turned on, so that the latch circuit LD of the latch circuit 5b is turned on.
The inverted storage node / D1 of 1 and the inverted storage node / D0 of the latch circuit LD0 are pulled to a low level, and the storage nodes D1 and D0 are inverted to a high level. Thereby, the latch data (D
(1, D0) = (D1, D0) = (1, 1), and the write operation is prohibited in the next and subsequent write operations.

On the other hand, when the latch data Q of the verify / read control circuit 5c is set to Q = "0",
Since the transistors NT18 and NT20 do not turn on, the latch data (D1, D0) of the latch circuit 5b is held in the set state.

After completion of the first write operation, at this time, the latch circuit L of the verify / read control circuit 5c is set.
The reason why the storage node Q of Q is set to the high level is as follows.
When the latch data of the latch circuit 5b is (D1, D0) =
This is only the case of (1,1), and at this time, the latch data (D1, D0) of the latch circuit 5b does not substantially change.

As described above, the latch data (D1, D
After the inversion of (0) is performed, the control signal Vref is set to the low level, the transistor PT1 is turned on, and the bit line is charged with the power supply voltage Vcc. After a certain period of time, the bit line is charged to a predetermined potential, and the node SA goes to the Vcc level. When the charging of the bit line is completed, the control signal Vref is set to a voltage of a predetermined level at which the transistor PT1 can supply a current sufficient to compensate for the leakage current of the bit line.

In the verify operation, in the above state,
The voltage of the selected word line is set to a predetermined value, and the presence or absence of the cell current at this time is reflected on the voltages of the bit line and the node SA,
The threshold voltage of the memory cell is determined, and after a lapse of a predetermined time, the control signal LAT1 which is a pulse signal is determined.
Is set to the high level, the result of the determination is transmitted to the latch circuit LQ of the verify / read control circuit 5c.
Reflected in the latch data. At this time, in this embodiment, as will be apparent from the following description, as the state of the memory cell at the time of the verify operation, (A) the threshold voltage of the memory cell is larger than 0 V and the distribution in FIG. A case where none of the program states shown by A to distribution C has been reached, and (B) a threshold voltage of the memory cell has reached one of the program states shown by distributions A to C in FIG. It is conceivable that the case (C) is such that the threshold voltage of the memory cell is smaller than 0 V and has not reached the intermediate program state.

In the case (A), the original write data to be written to the memory cell is other than "11", and the threshold voltage of the memory cell exceeds 0 V for the first time by this write operation, and To be reached. In this case, since the cell current does not flow even if the threshold comparison voltage VVF (= 0 V) is applied to the selected word line, the voltage of the bit line does not change and the node SA is kept at the Vcc level. Thereby, the transistor NT12
Is turned on. When the control signal LAT1 is set to a high level after a lapse of a predetermined time, the transistor NT11 is turned on, and at this time, the transistor N
Since T12 is in the ON state, in the verify / read control circuit 5c of the data latch circuit 5, the inverted storage node / Q of the latch circuit LQ is pulled to the low level, and the storage node Q is inverted from the low level to the high level. I do.

In the case (B), the original write data is other than “11”, the threshold voltage of the memory cell has exceeded 0 V by the previous write operation, and the distribution voltage has already been shown in FIG. This corresponds to a case where any one of the program states indicated by A to distribution C has been reached.
The operation in this case is the same as in the case of (A), except that the latch circuit LQ
Does not change here because the storage node Q of the memory cell is inverted to the high level.

In the case of (C), (C-1) the case where the original write data is other than "11" and the threshold voltage Vth of the memory cell is smaller than 0 V;
2) It is possible that the original write data is "11".

In the case of (C-1), by applying the threshold comparison voltage VVF (= 0 V) to the selected word line, a cell current larger than the leakage compensation current flows, and the voltage of the node SA drops. Charge redistribution occurs between the bit line capacitance CBL and the node SA capacitance CSA (<< CBL), and the voltage of the node SA becomes a low level (for example, about 1 V) substantially equal to the bit line voltage. . Therefore, the control signal L
Even if the transistor NT11 is turned on by AT1, the gate of the transistor NT12 is at a low level (for example, 1V
), The verify / read control circuit 5c cannot supply a current required to invert the storage node Q of the latch circuit LQ, and the storage node Q of the latch circuit LQ is in the set state. Is kept at the low level.

In the case of (C-2), since the original write data is "11", no data is written in the memory cell, and the threshold voltage Vth of the memory cell is changed.
Corresponds to the erased state shown by the distribution D in FIG. In this case, the storage node Q of the latch circuit LQ is always set to the high level. Therefore, in this case, the storage node Q of the latch circuit LQ is maintained at the high level as it is in the set state by the same operation as in the case of (C-1).

Thereafter, when the verify operation is completed by setting all word lines to the ground level, control signal V
When ref is set to high level, the transistor PT
1 is turned off. Then, the transistor NT1 is turned on when the control signal DISC is set to the high level. As a result, the bit line is grounded.

The verify operation is performed as described above. In the example shown in FIG. 4, at the end of the first write operation, the threshold voltage of any memory cell has not reached the intermediate program state (Vth = 0 V), so that the write data is stored in a memory cell other than "11". In corresponding data latch circuit 5, verify / read control circuit 5c
Of the latch data Q are all "0".

Next, in response to the result of the above-described verify operation, a second write operation is executed. When the second write operation is started, the control signal DISC is switched to the low level, as in the first write operation, and the bit line is disconnected from the ground line. Then, the control signal Vref is set to low level, and the bit line is charged to _Vcc level.

At the time of the second write operation, the bit line voltage supply circuit VBL
The voltages supplied to 1 to VBL3 are reduced as compared with the first write operation. That is, the voltage VB1 (2) (<VB1 (1)) is supplied to the bit line voltage supply line VBL1, and the voltage VB1 is supplied to the bit line voltage supply line VBL2.
2 (2) (<VB2 (1)), and the voltage VB3 (2) (<VB3 (1)) is supplied to the bit line voltage supply line VBL3.

After that, the control signal Vref is set to a voltage of a predetermined level at which the transistor PT1 can supply a current enough to compensate for the leakage current of the bit line. Then, after a lapse of a certain time, the control signal PRG becomes high level,
When the control signal / PRG is set to the low level, the transistors NT2 and PT2 are turned on.
As a result, the bit line is connected to the latch data (D1, D0) of the latch circuit 5b and the verify / read control circuit 5b.
A predetermined bit line voltage supply line is connected according to the latch data Q of c. Thereafter, the program voltage VPGM (2) is applied to the selected word line, and the write pass voltage Vpass (2) is applied to the non-selected word lines, so that data is written to the selected memory cell. In addition,
In the example shown in FIG. 4, in the second write operation, the latch data (D1, D0) is (D1, D0) Ｄ
Since the threshold voltage of any of the memory cells set to (1, 1) has not reached the intermediate program state, the latch data Q is Q = "0". Therefore, in these memory cells, VPGM (2) -VB0 = VPGM (1) + dV
Writing is performed by a voltage pulse of -VB0.

Thereafter, the same write operation and verify operation are repeated until the threshold voltage of the memory cell reaches the intermediate program state.

In FIG. 4, the memory cell to which the fastest writing is performed reaches the intermediate program state by exceeding the threshold voltage of 0 V by the third writing operation. And
By the verify operation performed after the end of the third write operation, in the data latch circuit 5 corresponding to the fastest write memory cell, the latch data Q of the verify / read control circuit 5c is inverted to Q = "1". . Thus, at the time of the next fourth write operation, the latch data Q of the verify / read control circuit 5c is
Is Q = “1”, the transistor NT3 is turned on, and the bit line is connected to one of the bit line voltage supply lines VBL1 to VBL3 according to the latch data (D1, D0) of the latch circuit 5b. Is done.

In the example shown in FIG. 4, the original write data to be written to the memory cell to which the fastest write is performed is "0".
0 ". In this case, in the data latch circuit 5 corresponding to the memory cell with the fastest write, the latch data Q of the verify / read control circuit 5c is Q ="
1 "and the latch data (D
Since (D1, D0) is (D1, D0) = (0, 0), the bit line is connected to the bit line voltage supply line VBL3. Therefore, in the fastest write memory cell that has reached the intermediate program state, VPGM (4) -V
Writing is performed by a voltage pulse of B3 (4) = VPGM (1) + dV × 3-VB3 (4). As a result, the threshold voltage of the memory cell with the fastest writing is the program state indicated by distribution A in FIG. 4, that is, the data "00" whose threshold voltage is Vth (DATA = "00"). Reaches the program state corresponding to. On the other hand, in other memory cells that have not reached the intermediate program state, VPGM
(4) Writing is performed by a voltage pulse of -VB0 = VPGM (1) + dV × 3-VB0.

Then, in the inversion process of the latch data (D1, D0) performed after the end of the fourth write operation, the data latch circuit 5 corresponding to the memory cell to which the fastest write is performed is verified by the previous verify operation. / Latch data Q of read control circuit 5c is Q
= "1", the control signal LAT
3 turns on the transistor NT16, and the control signals RD1 and RD0 turn on the transistor NT17.
When NT19 is turned on, the latch data (D1, D0) of the latch circuit 5b becomes (D1, D0) = (1, 1).
Flip to As a result, in the next and subsequent write operations, the write to the fastest write memory cell is prohibited.

Further, in the example shown in FIG. 4, the threshold voltage Vth of a predetermined memory cell to which writing is performed slower than a memory cell to which writing is performed fastest by the sixth write operation.
Reach an intermediate program state beyond 0V. Also in this case, similarly, as a result of the verify operation, the latch data Q of the verify / read control circuit 5c is inverted to Q = "1", and at the time of the next seventh write operation, the bit line is latched by the latch circuit 5b. According to the data (D1, D0),
Connected to any of bit line voltage supply lines VBL1 to VBL3. In the example shown in FIG. 4, the write data to be written to the memory cell into which the writing is slow is “01”. In this case, in the data latch circuit 5 corresponding to the memory cell in which the writing is slow, the latch data Q of the verify / read control circuit 5c is Q = "1",
Since the latch data (D1, D0) of the latch circuit 5b is (D1, D0) = (0, 1), the bit line is connected to the bit line voltage supply line VBL2.
Therefore, at the time of the seventh write operation, in the memory cell where the write is slow, VPGM (7) -VB2 (7) =
Writing is performed by a voltage pulse of VPGM (1) + dV × 6-VB2 (7). As a result, the threshold voltage of the memory cell in which writing is slow is in the program state shown by distribution B in FIG. 4, that is, the threshold voltage is Vth (D
ATA = "01") The program state corresponding to the data "01" is reached. Then, in the inversion process of the latch data (D1, D0) performed after the end of the seventh write operation, the latch data (D1, D1) of the latch circuit 5b in the data latch circuit 5 corresponding to the memory cell into which the write operation is slow. D0) is inverted to (D1, D0) = (1, 1).

In this way, the same writing is performed for the other memory cells, and the latch data (D1, D0) of the latch circuit 5b is sequentially changed from the one whose threshold voltage has reached a desired program state to ( Invert to 1,1). Then, in all the data latch circuits 5, the latch data (D1, D0) of the latch circuit 5b is (D1,
At the time point when (D0) = (1,1) is inverted, the entire writing is completed. If the writing is not completed within the designated number of times of writing, a writing error is determined.

Here, in the above-described data writing method, the following characteristics of the memory cell are used when 2-bit multi-value data is written in the memory cell.

That is, the ISPP system is a system in which the write pulse voltage applied to a word line is increased stepwise from a predetermined initial voltage by a predetermined step width, and data is sequentially written to memory cells. At this time, it is assumed that a certain bit line voltage, for example, VB0 is applied to the bit line. In this case, assuming that the initial voltage of the write pulse voltage is VWL0, the step width is dV, and the number of write times is n, the voltage pulse applied to the memory cell is VWL
WL0 + dV.times. (N-1) -VB0, and the amount of change dVth of the threshold voltage of the memory cell for each write cycle quickly converges to the amount of change dV of the word line voltage.

Next, the bit line voltage is changed to a certain voltage VB at the time of the m-th write when the change amount dVth of the threshold voltage of the memory cell converges to almost dV. In this case, the voltage pulse applied to the memory cell is VWL0 + dV ×
(M-1) -VB, and the change amount dVth 'of the threshold voltage of the memory cell at this time is approximately dVth' = dV
+ A (VB0−VB). However, VB0> VB,
It is assumed that 0 <a <1. Accordingly, the bit line voltage difference V
By associating B0-VB with the write data,
It becomes possible to separate the threshold voltage of the memory cell after this writing. Here, the coefficient a depends on the pulse width of the write pulse voltage and the characteristics of the memory cell, but has a characteristic that it hardly depends on the number of write times m when the bit line voltage is changed from VB0 to VB.
The coefficient a approaches 1 when the pulse width of the write pulse voltage is set to a relatively large value (for example, about 50 μs). Further, there is a feature that the coefficient a becomes larger as the memory cell is written faster, and becomes smaller as the memory cell is written later.

The above will be considered by applying the above embodiment. That is, in the above-described embodiment, the initial bit line voltage VB is applied to the bit line until the threshold voltage of the memory cell reaches the intermediate program state.
Writing is performed by giving 0. At this time, at the time of the first write, the change amount dV of the threshold voltage between the memory cell where the write is fast and the memory cell where the write is slow is performed.
Although there is a difference in th, in the subsequent M-th write,
The variation dVth of the threshold voltage converges to approximately dV (dV is the step width of the program voltage VPGM (N) applied to the selected word line).

The change amount dVth of the threshold voltage is d
Some times after the M-th time converged to V (for example, x-1 time)
When the threshold voltage Vth of the memory cell reaches the intermediate program state at the time of writing, the latch data (D1, D0) of the latch circuit 5b is written at the next (x-th) writing.
Is VB (DATA = "10") = VB1 (x) when (1,0), and VB (DATA = "01") = VB2 (x), (0,0) when (0,1) ), VB (DATA = "00") = VB3 (x), and so on, the bit line is supplied with a bit line voltage corresponding to the write data, and writing is performed.

In this case, the amount of change in threshold voltage dVth '
When the latch data (D1, D0) of the latch circuit 5b is (1, 0), dVth '= dV + a (VB0-VB (DATA = "10")) = dV + a (VB0-VB1 (x)), In the case of (0, 1), dVth '= dV + a (VB0-VB (DATA = "01")) = dV + a (VB0-VB2 (x)), and in the case of (0, 0), dVth' = dV + a (VB0- VB (DATA = "00") = dV + a (VB0-VB3 (x)).

By the x-th write operation, the threshold voltage Vth of the memory cell becomes Vth = Vth (DATA = "10") when the latch data (D1, D0) of the latch circuit 5b is (1, 0). ), (0,1), Vth = Vth (DATA = "01"), (0,0), Vth = Vth (DATA = "00"), and each program state corresponding to write data Is separated into In this embodiment, the threshold voltage of the memory cell after the x-th write performed by applying a bit line voltage corresponding to the write data to the bit line and the latch data (D1, D0) of the latch circuit 5b ) And the difference between the bit line voltages (the amount of change in the bit line voltage) VB0−VB1 based on the statistical data of the threshold voltage characteristics of the memory cell in advance so that
(x), VB0-VB2 (x) and VB0-VB3 (x) are set.

Further, in this embodiment, taking into account that the coefficient a becomes smaller as the memory cell is slower in writing, in other words, the memory cell in which the threshold voltage reaches the intermediate program state is larger in the number of times of writing. Bit line voltage VB (DATA = "10"), VB according to write data
(DATA = "01") and VB (DATA = "00") are monotonously reduced according to the number of times of writing. This is for the following reasons. That is, the amount of change dVth 'of the threshold voltage of the memory cell when the bit line voltage is switched from the initial bit line voltage VB0 to the bit line voltage according to the write data during writing depends on the coefficient a. The larger the memory cell with the larger write, the larger the memory cell, and the smaller the coefficient a, the smaller the memory cell with the slow write. On the other hand, the change amount dVth 'of the threshold voltage of the memory cell also depends on the change amount of the bit line voltage, and increases as the change amount of the bit line voltage increases, and decreases as the change amount of the bit line voltage decreases. Become. Therefore, in this embodiment, utilizing the fact that the number of times of writing until reaching the intermediate program state is smaller for a memory cell with a faster writing and greater for a memory cell with a slower writing, the bit line voltage corresponding to the writing data is increased. , According to the number of times of writing. By doing so, when the bit line voltage is switched from the initial bit line voltage VB0 to the bit line voltage according to the write data, the amount of change in the bit line voltage can be reduced in the memory cell where writing is fast. Since the amount of change in the bit line voltage can be increased in a memory cell in which writing is slow, the amount of change dVth 'in the threshold voltage of the memory cell at this time should be substantially constant regardless of the memory cell characteristics. Because it can be. As a result, in this embodiment, since the threshold voltage of the memory cell to which the same data is written rises to a substantially equal write level, the distribution width of the memory cell in each program state is narrowed.

According to this embodiment having the above-described configuration, when 2-bit data is written in a memory cell selected in a page unit by the ISPP method, the threshold voltage of the memory cell during the verify operation is Since only one comparison is required, the advantage that the total writing time is greatly reduced can be obtained.

Here, in the data writing method according to the embodiment configured as described above, the number of times of writing and the total writing time until the writing in page units is completed will be evaluated.

In the case of the writing method based on the ISPP method,
The maximum number of write times Np and the maximum write time T until the writing of all the memory cells in the write page is completed.
p is defined by _{Np = (DV C + DVpp +} DVch) / dV + 2 (1) Tp = Np × (Tpulse + Tvfy × Nvfy) -Tvfy (2). Here, DV _C : difference in threshold voltage change between the memory cell with the fastest write and the memory cell with the slowest write after the first write DVpp: output fluctuation of booster circuit DVch: channel voltage fluctuation dV : Step width of write pulse voltage in the case of using ISPP method Tpulse: Pulse width of write pulse voltage Tvfy: Comparison time of one threshold voltage in verify operation Nvfy: Comparison of threshold voltage in verify operation Number of times.

In the equations (1) and (2), the conditions in the data writing method of the conventional quaternary NAND type flash memory, for example, DV _C = 2.0 V, DVpp
= 0.5 V, DVch = 0.1 V, dV = 0.3 V (provisional value in case of 4 values), Tpulse = 20 μs, Tvfy = 2 μ
By substituting s and Nvfy = 3 times to obtain the maximum number of write times Np and the maximum write time Tp, respectively, Np = (2.0 + 0.5 + 0.1) /0.3+2=11
(Times) Tp = (20 + 2 × 3) × 11−2 × 3 = 280 (μ)
s) On the other hand, in the data writing method according to this embodiment, since Nvfy = 1, the maximum writing time Tp is: Tp = (20 + 2 × 1) × 11−2 × 1 = 240 (μ)
s), which indicates that the total writing time is significantly reduced as compared with the related art.

Further, the number of times of writing and the total writing time when the same method as the data writing method according to this embodiment is applied to an 8-level NAND flash memory will be evaluated.

In the equations (1) and (2), the conditions in the data writing method of the conventional 8-level NAND flash memory, for example, DV _C = 2.0 V, DVpp
= 0.5V, DVch = 0.1V, dV = 0.15V (8
Value, provisional value), Tpulse = 20 μs, Tvfy = 2
μs, Nvfy = 7 times, and the maximum number of write times Np
And the maximum write time Tp, respectively, Np = (2.0 + 0.5 + 0.1) /0.15+2=2
0 (times) Tp = (20 + 2 × 7) × 20−2 × 7 = 666 (μ
s) On the other hand, in a method similar to the data writing method according to this embodiment, since Nvfy = 1, the maximum writing time Tp becomes Tp = (20 + 2 × 1) × 20−2 × 1 = 438 ( μ
s), and also in this case, the total writing time is significantly reduced as compared with the conventional case.

According to this embodiment, the bit line voltage corresponding to the write data is reduced according to the number of times of writing, so that the distribution of memory cells in each program state can be narrowed. You can also get

Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above embodiments, and various modifications based on the technical concept of the present invention are possible. For example, the configurations, numerical values, operation timings, and the like described in the above-described embodiment are merely examples,
If necessary, different configurations, numerical values, operation timings, and the like may be used. Specifically, the overall configuration of the NAND flash memory, the configuration of the memory cell array 1, the data latch circuit 5, and the configuration of the bit line voltage generation circuit 6 in the above-described embodiment are merely examples, and have different configurations from those illustrated. There may be.

In the above-described embodiment, after completion of writing in page units, whether or not desired data has been written to the memory cells may be confirmed. In this case, after completion of writing in page units, data reading of all memory cells in the page is executed. Then, for example, an error check is performed using a check bit added to the page data at the time of writing. After executing the page read, for example, the read page data and
A complete write confirmation may be made by comparing all of the write page data with the copy data.

In the above-described embodiment, the data latch circuit 5 may be further provided with a bit line selection circuit, and one data latch circuit 5 may be shared by a plurality of (for example, two) bit lines. .

In the above-described embodiment, a case has been described in which the present invention is applied to a quaternary NAND flash memory in which one memory cell stores two-bit quaternary data. The present invention relates to a NAN that stores three or more bits of data in one memory cell.
The present invention can be applied to a D-type flash memory.

[0110]

As described above, according to the present invention, when writing n bits (where n.gtoreq.2) of data to a memory cell, the number of comparisons of the threshold voltage of the memory cell during the verify operation is reduced. Since only one time is required, there is an effect that the total writing time can be significantly reduced as compared with the related art.

[Brief description of the drawings]

FIG. 1 is a schematic diagram illustrating a configuration example of a NAND flash memory according to an embodiment of the present invention;

FIG. 2 is an equivalent circuit diagram showing a configuration example of a memory cell array of a NAND flash memory according to one embodiment of the present invention;

FIG. 3 is a schematic diagram illustrating a configuration example of a data latch circuit and a bit line voltage generation circuit of a NAND flash memory according to an embodiment of the present invention;

FIG. 4 is a schematic diagram for explaining a data writing method of the NAND flash memory according to the embodiment of the present invention;

FIG. 5 is a schematic diagram for explaining a data writing method of the NAND flash memory according to the embodiment of the present invention;

FIG. 6 is a schematic diagram for explaining the correspondence between the threshold voltage of a memory cell and the content of stored data in a flash memory that stores 4-bit data composed of 2 bits in one memory cell. .

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... memory cell array, 2 ... main row decoder, 3 ... sub row decoder, 4 ... booster circuit, 5
... Data latch circuit, 5a ... Bit line voltage setting circuit, 5b ... Latch circuit, 5c ... Verify /
Read control circuit, 6 ... bit line voltage generation circuit, 11
... Counter, 12 ... ROM, 13-15 ...
D / A converter, A0, A1... NAND string,
M _{0-0 to} M _15-0 , M _{0-1 to} M _15-1 ... memory cell, D
S0, DS1, SS0, SS1 ... select transistors, BL0, BL1 ... bit lines, SL ... source lines, WL0 to WL15 ... word lines, DSG, SSG
... Selection gate lines, NT1 to NT20, PT1 to PT
3 ... transistor

Claims (13)

[Claims] An amount of charge accumulated in a charge accumulating portion changes according to a voltage applied to a word line and a bit line, and a threshold voltage changes according to the change. Memory cell having an erased state and 2 ⁿ -1 program states for storing n-bit (where n ≧ 2) data, and a word line during a write operation. The write pulse voltage applied to the nonvolatile semiconductor memory device is increased stepwise from a predetermined initial voltage by a predetermined step width according to the number of times of writing, and data is written to the selected memory cell in page units. Then, while applying the write pulse voltage to the word line and applying a predetermined initial bit line voltage to the bit line, data is written to the memory cell. A detecting means for detecting that the threshold voltage of the cell reaches the shallowest program predetermined intermediate program state shallower than the state of the 2 ⁿ -1 pieces of program state, counting the number of times of writing from the writing start And a bit line voltage applying means for applying a bit line voltage according to write data to a bit line connected to the memory cell when the threshold voltage of the memory cell reaches the intermediate program state. A nonvolatile semiconductor memory device characterized by having: 2. The method according to claim 1, wherein the detecting means applies a predetermined comparison voltage capable of discriminating the intermediate program state to a word line and detects the presence or absence of a cell current at this time, thereby detecting the presence of the memory cell. 2. The nonvolatile semiconductor memory device according to claim 1, wherein whether or not a threshold voltage has reached the intermediate program state is detected. 3. The non-volatile memory according to claim 1, wherein said bit line voltage applying means decreases the bit line voltage according to said write data stepwise with a predetermined step width according to the number of times of writing. Semiconductor memory device. 4. A bit line voltage generating means for supplying a bit line voltage according to the write data to the bit line voltage applying means, wherein the bit line voltage generating means comprises:
4. The nonvolatile semiconductor memory device according to claim 3, wherein a bit line voltage according to said write data is changed based on a count value of said counting means. 5. A write operation is performed by applying a bit line voltage corresponding to the write data to a memory cell whose threshold voltage has been detected to have reached the intermediate program state.
2. The non-volatile semiconductor memory device according to claim 1, further comprising a write control means for prohibiting writing of data to the memory cell. 6. The non-volatile semiconductor memory device according to claim 1, further comprising a confirmation means for confirming whether or not desired data has been written to said memory cells after completion of writing in page units. 7. The nonvolatile semiconductor memory device according to claim 1, wherein
2. The nonvolatile semiconductor memory device according to claim 1, wherein said nonvolatile semiconductor memory device is a flash memory. 8. A charge amount stored in a charge storage portion changes in accordance with a voltage applied to a word line and a bit line, and a threshold voltage changes in accordance with the change. Memory cell having an erased state and 2 ⁿ -1 program states for storing n-bit (where n ≧ 2) data, and a word line during a write operation. The write pulse voltage applied to the non-volatile semiconductor memory device is increased stepwise from a predetermined initial voltage by a predetermined step width in accordance with the number of times of writing, and writes data to the selected memory cell in page units. a data writing method, the threshold voltage of the memory cell from the write start is shallower than the shallowest program state of the 2 ⁿ -1 pieces of program state Until a predetermined intermediate program state is reached, a first write step of writing data to the memory cell by applying a predetermined initial bit line voltage to the bit line while applying the write pulse voltage to the word line is performed. A verifying step for detecting whether or not the threshold voltage of the memory cell has reached the intermediate program state, each time the threshold voltage of the memory cell has reached the intermediate program state; A data writing method for a nonvolatile semiconductor memory device, comprising: performing a second writing step of writing data by applying a bit line voltage according to write data to a bit line connected to a memory cell. 9. In the verifying step, a predetermined comparison voltage capable of discriminating the intermediate program state is applied to a word line, and the presence or absence of a cell current at this time is detected. 9. The data writing method according to claim 8, wherein whether the threshold voltage has reached the intermediate program state is detected. 10. The method according to claim 1, wherein the bit line voltage corresponding to the write data to be applied to the bit line in the second writing step is reduced stepwise with a predetermined step width according to the number of times of writing. 9. The data writing method for a nonvolatile semiconductor memory device according to claim 8, wherein: 11. The method according to claim 11, wherein in the second writing step, writing is performed by applying a bit line voltage corresponding to the write data to the memory cell in which the threshold voltage is detected to have reached the intermediate program state. 9. The data writing method for a nonvolatile semiconductor memory device according to claim 8, wherein writing of data to the memory cell is prohibited. 12. The non-volatile semiconductor memory device according to claim 8, further comprising a step of confirming whether or not desired data has been written to said memory cells after completion of writing in page units. Data writing method. 13. The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device is a NAN.
9. A D-type flash memory.
The data writing method of the nonvolatile semiconductor memory device described in the above.