JP2000149577A - Nonvolatile semiconductor memory and method of writing data therein - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the write time by applying an ideal voltage suited to write data to the channel of a memory cell to be written. SOLUTION: In the write operation to an 8-valued NAND type flash memory, a drain side selected gate line DSG to a level Vcc to execute a multivalued parallel write, using a self boost. After setting a selected bit line to a bit line voltage according to a write data, a word line voltage VWL is boosted in three steps. According to the boost step of the word line voltage VWL, at specified timings, a bit line voltage feed line VBL3 for feeding a bit line voltage VB3 (=1.5 V) and a bit line voltage feed line VBL2 for feeding a bit line voltage VB2 (=1.5 V) are switched to the level Vcc one after the other to disconnect the channels of a memory cell from the bit lines. Thus the channel voltage of a memory cell with a write data '110' and the channel voltage of a memory cell with a write data '10x' are boosted to specified write potentials by the capacitive coupling with word lines.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device and a data writing method thereof,
The present invention is suitable for a multi-valued nonvolatile semiconductor memory device storing two or more bits of multi-valued data in one memory cell, and for writing the data.

[0002]

2. Description of the Related Art In recent years, flash memories, which have better electrical characteristics than various recording devices and hard disk devices, have become widespread as recording media in video / audio equipment, portable information equipment, and the like. A flash memory is an electrically rewritable non-volatile semiconductor memory device, and is roughly classified into NOR type and NAND type based on the connection relationship and structure of the memory cells.
Divided into types. In a nonvolatile semiconductor memory device such as a flash memory, data having two values “0” and “1” is stored in one memory cell.
A value type is usually used, but recently, in response to a demand for a large capacity of a semiconductor memory device, a so-called multi-value type in which three or more (two or more bits) multi-value data is stored in one memory cell. Has been proposed.

As such a multi-valued nonvolatile semiconductor memory device, for example, a four-valued NAND flash memory in which one memory cell transistor stores two-bit data having four values, There is an octal-type NAND flash memory that stores 3-bit data having three bits in each memory cell transistor. FIG. 7 shows the correspondence between the distribution of the threshold voltage Vth of the memory cell transistor and the data content in the 8-level NAND flash memory. In FIG. 7, the vertical axis of the graph indicates the threshold voltage Vth of the memory cell transistor, and the horizontal axis of the graph indicates the distribution frequency of the memory cell transistor.

As shown in FIG. 7, in an eight-level NAND flash memory, threshold voltages Vth of memory cell transistors are “000”, “001”, and “01”.
0 "," 011 "," 100 "," 101 "," 11 "
8 states (distribution 7 to distribution 0) corresponding to the data contents of "0" and "111" are taken. In FIG. 7, VVF1, VVF2, VVF3, V
VF4, VVF5, VVF6, VVF7 indicate the selected word line voltage at the time of reading in the verify operation corresponding to each state.
RD1, VRD2, VRD3, VRD4, VRD5, VRD6, VRD7 represent the selected word line voltage in the normal read operation corresponding to each state. The magnitude relation is VVF7>VRD7>VVF6> VRD
6>VVF5>VRD5>VVF4>VRD4>VVF3> VRD3
>VVF2>VRD2>VVF1> VRD1. For example, VVF7 = 3.8V, VRD7 = 3.6V, VVF6 =
3.2V, VRD6 = 3.0V, VVF5 = 2.6V, VRD5
= 2.4V, VVF4 = 2.0V, VRD4 = 1.8V,
VVF3 = 1.4V, VRD3 = 1.2V, VVF2 = 0.8
V, VRD2 = 0.6V, VVF1 = 0.2V, VRD1 = 0
V.

In general, in a multi-level NAND flash memory, as a method of writing data to a memory cell, multi-level data is written in a batch (parallel) by changing a bit line voltage according to write data. That is, so-called multi-level parallel writing is employed from the viewpoint of speeding up the writing operation. In the case of this 8-level NAND flash memory, ideally, for example, when the write data is “000”, the bit line voltage is 0 V and the write data is “ When the write data is “010”, the bit line voltage is 0.6 V, when the write data is “010”, the bit line voltage is 1.2 V, and when the write data is “011”, the bit line voltage is 1.8 V.
The bit line voltage when the write data is “100” is set to 2.4 V, the bit line voltage when the write data is “101” is set to 3.0 V, and the write data is set to “110”.
If the bit line voltage is set to 3.6 V in the case of (1) and the bit line voltage is set to 8.0 V in the case where the write data is "111", the writing of all data having different write levels can be completed almost simultaneously. It is.

[0006]

However, in the actual writing operation of the NAND flash memory, a so-called self-boost or local self-boost method is used from the viewpoint of saving power and reducing the element area.

Here, a writing method using self-boost will be described with reference to FIG. A memory cell in a NAND flash memory is configured by a MOS transistor having a floating gate (FG) and a control gate (CG). A memory string is constituted by a predetermined number of the memory cell transistors connected in series. In a memory cell array of a NAND flash memory, a plurality of memory strings are arranged in parallel,
Memory cell transistors in the same row are connected by a common word line. In the example shown in FIG. 8, a single memory strings by the memory cell transistors M ₀ ~M ₇ connected to the eight series. One end of the memory string (the drain of the memory cell transistor M ₇₎ is connected to the bit line BL via the selection transistor DS, the source line and the other end of the memory string (the source of the memory cell transistors M ₀₎ via a selection transistor SS Connected to SL. Then, the control gate of the memory cell transistors M ₀ ~M ₇ is connected to the word line WL0~WL7 respectively, selection transistor D
The gate of S is connected to the drain-side selection gate line DSG, and the gate of the selection transistor SS is connected to the source-side selection gate line SSG.

[0008] In the writing method using the self-boosting, the voltage of the drain side select gate line DSG is set to V _CC level, the source-side select gate line SSG
Is set to the GND level. When a memory string to be written is selected by an address decode signal, a bit line connected to the selected memory string is set to a voltage VBL according to write data.
, And the bit line connected to the unselected memory string is floated at the precharge level. Thereafter, the selected word line (word line WL4 in the example shown in FIG. 8) set as the write target page is set to a predetermined write voltage VPGM, and the other unselected word lines are set to the write pass voltage Vpass (<VPG
M) and data is written to the memory cell transistor to be written.

At this time, the channel of the memory cell transistor whose write data is the same as the erased state (the write data is “111”) and the channel of the memory cell transistor of the non-selected memory string are connected to the drain side of the memory string. The transistor DS is separated from the corresponding bit line BL and boosted to a non-write potential by capacitive coupling with a word line (mainly a non-selected word line).

However, in the writing method using self-boost or local self-boost, as described above, the drain-side selection gate line DSG is set to the V _CC level, and therefore, the memory cell of the memory string is connected via the bit line BL. The voltage that can be supplied to the channel of the transistor is limited to V _CC -VthDSG (VthDSG is the threshold voltage of the selection transistor DS) by the selection transistor DS on the drain side of the memory string. Therefore, the upper limit of the voltage that can be applied to the bit line BL at the time of writing is a voltage with a margin from V _CC -VthDSG, for example, 1.5 V.

In a multi-level NAND flash memory, it is desirable that the bit line voltage set according to the write data has a one-to-one correspondence with the write data from the viewpoint of the write speed. However,
In an 8-level NAND flash memory, it is necessary to fit the 8-level latch circuits in a pitch corresponding to several bit lines, so that the write data is actually “00x”.
The bit line voltage in the case of (x: 0 or 1) is 0 V, the bit line voltage in the case of write data “01x” (x: 0 or 1) is VB1, and the write data is “10x”.
The bit line voltage when (x: 0 or 1) is VB2, the voltage when the write data is "110" is VB3, and the bit line voltage when the write data is "111" is VB.
One bit line voltage is set for a plurality of data, such as _CC (where VB1, VB2, and VB3 are voltages larger than 0 V and smaller than V _CC ).

Therefore, an eight-level NAND has heretofore been used.
At the time of actual writing in the type flash memory, for example, as shown in FIG.
0x ”(x: 0 or 1) when the bit line voltage is 0V
When the write data is “01x” (x: 0 or 1), the bit line voltage is 1.2 V, and when the write data is “10x” (x: 0 or 1), the bit line voltage is 1.5 V. In addition, the bit line voltage when the write data is “110” is set to 1.5 V, and the bit line voltage when the write data is “111” is set to V _CC , whereby multi-level parallel writing is performed. .

Referring to the drawings, a description will be given of a configuration of an 8-level NAND flash memory for performing multi-level parallel writing and a write operation thereof.

FIG. 9 shows a main part of an eight-level NAND flash memory previously proposed by the present applicant. In FIG. 9, reference numeral 101 denotes a memory cell array, and reference numeral 102 denotes a bit line voltage generation circuit.

As shown in FIG. 9, the memory cell array 10
Reference numeral 1 denotes, for example, a MOS transistor (memory cell transistor) having a floating gate (FG) and a control gate (CG), each of which functions as a 3-bit memory cell, arranged in a matrix. Of memory cell transistors are configured by memory strings A0 to An connected to common word lines WL0 to WL15.
Note that FIG. 9 omits the illustration after the memory string A2.

The memory string has a plurality of memory cell transistors connected in series. The memory string A0 includes memory cell transistors M _{0-0 to} M _15-0
It consists of. Memory cell transistor M _15-0
Is connected to the source of the select transistor DS0, and the drain of the select transistor DS0 is connected to the bit line BL.
0 is connected. On the other hand, the memory cell transistor M
The source of _0-0 is connected to the drain of the selection transistor SS0, and the source of the selection transistor SS0 is connected to the source line S.
L. Further, the memory cell transistor M
_0-0 the control gates of ~M _15-0 is connected to each word line WL0 to WL15. Similarly, the memory string A1 includes the memory cell transistors M _{0-1 to} M _0-1
15-1 . Memory cell transistor M
The drain of _15-1 is connected to the source of the selection transistor DS1, and the drain of the selection transistor DS1 is connected to the bit line BL1. On the other hand, the source of the memory cell transistor M _0-1 is connected to the drain of the selection transistor SS1, and the source of the selection transistor SS1 is connected to the source line SL. The control gates of the memory cell transistors M _{0-1 to} M _15-1 are connected to word lines WL0 to WL15, respectively.

As described above, the memory strings A0 and A1 are connected to the respective lines, and the other memory strings A2 to An have the same connection relationship. Therefore, one ends of the memory strings A0 to An are connected to the bit lines BL0 to BLn through the selection transistors DS0 to DSn, and the other ends of the memory strings A0 to An are connected to the source lines SL through the selection transistors SS0 to SSn. It is connected. The gates of the select transistors DS0 to DSn are connected to a common drain-side select gate line DSG, and the gates of the select transistors SS0 to SSn are connected to a common source-side select gate line SSG. In the memory cell array 101, the memory strings A0 to An as described above are arranged in parallel.

Bit line voltage generation circuit 102 provided corresponding to bit lines BL0 and BL1 includes n-channel MOS transistors N101 to N101.
N111, a latch circuit LQ2, LQ1, LQ0 connecting the input and output of the inverter and a p-channel MOS
The transistor P101 is composed of a transistor. Further, from the bit line voltage generation circuit 102, bit line voltage supply lines VBL1, VBL2, VBL3 connected to a predetermined constant voltage source are derived. In this NAND flash memory, one bit line voltage generation circuit 10 including latch circuits LQ2 to LQ0 is provided.
In this configuration, two bit lines are selectively connected to bit line 2 (bit line shared). Note that the bit line BL
The bit line voltage generation circuits corresponding to the second and subsequent bit lines have the same configuration, and a description of these portions will be omitted for simplicity.

At the time of writing, a bit line voltage corresponding to the write data is generated by the bit line voltage generation circuit 102, and the bit line voltage is applied to the channel of the memory cell transistor of the memory cell array 101 through the bit lines BL0 and BL1.

Between bit line BL0 and node SA,
Transistors HN101 and HN103, which are high-breakdown-voltage n-channel MOS transistors, are connected in series. Further, between the bit line BL1 and the node SA,
Transistors HN102 and HN104 formed of a high-breakdown-voltage n-channel MOS transistor are connected in series. A common control signal TRN is supplied to the gates of the transistors HN101 and HN102. Transistor HN
An address decode signal AiB is supplied to the gate of 103, and an address decode signal AiN is supplied to the gate of the transistor HN104.

In the bit line voltage generation circuit 102,
Transistor P101 is connected between the supply line of the node SA and the power supply voltage Vcc (V _CC, for example 3.3V). The control signal Vre is applied to the gate of the transistor P101.
f is supplied. Further, the transistor N101 is connected between the node SA and the ground line. The control signal DIS is supplied to the gate of the transistor N101.

In the bit line voltage generating circuit 102, the drain of the transistor N102 is connected to the node SA. The source of the transistor N102 is connected to the drains of the transistors N103, N105, N107 and N109. The control signal PGM is supplied to a gate of the transistor N102.

The transistors N103 and N104 are connected in series between the source of the transistor N102 and the ground line. A transistor N10 is connected between the source of the transistor N102 and the bit line voltage supply line VBL1.
5, N106 are connected in series. Transistor N
Transistors N107 and N108 are connected in series between the source of the transistor 102 and the bit line voltage supply line VBL2. The transistors N109 and N109 are connected between the source of the transistor N102 and the bit line voltage supply line VBL3.
110 and N111 are connected in series.

Latch circuits LQ2, LQ1, and LQ0 have storage nodes Q2, Q1, and Q0, respectively, and inverted storage nodes / Q2, / Q1, and / Q0. In addition, / means a bar indicating inversion.

Inverting storage node / Q2 of latch circuit LQ2
Is connected to the gates of transistors N104 and N106, and storage node Q2 is connected to transistors N107 and N109.
Connected to the gate. Inverting storage node / Q1 of latch circuit LQ1 is connected to the gates of transistors N103 and N108, and storage node Q1 is connected to transistor N10.
5, N110. Latch circuit L
The inverted storage node / Q0 of Q0 is connected to the gate of transistor N111.

Next, the write operation of this 8-level NAND flash memory will be described with reference to the timing chart of FIG.

Before the write operation, the control signal PGM is set to the low level (GND level), the transistor N102 is turned off, and the bit lines BL0 and BL1 are disconnected from the write control circuit 102. Then, when the control signal DIS goes high (Vcc level), the control signal T
RN and the address decode signals AiB and AiN are (V
(cc-Vth) level. At this time, the transistors HN101, HN102, HN103, HN104
In addition, all bit lines are grounded because the transistor N101 is turned on. The bit line voltage supply line VBL1 is set to the voltage VB1, the bit line voltage supply line VBL2 is set to the voltage VB2, and the bit line voltage supply line VBL3 is set to the voltage VB3. These voltages VB1, VB2, VB3 is larger V _CC smaller voltage than 0V, As an example, the voltage VB1 = 1.2
V, voltage VB2 = 1.5V, and voltage VB3 = 1.5V.

When writing is started in this state, write data is supplied to the latch circuits LQ2, LQ1, LQ0 of the bit line voltage generation circuit 102 via the data bus, and the write data is supplied to the latch circuit LQ.
Q2, LQ1, and LQ0 take in and hold the data. Thereafter, the control signal DIS is switched to low level, and the bit lines BL0 and BL1 are disconnected from the ground line. Then, the control signal TRN and the address decode signal Ai
B, AiN is a predetermined high level equal to or higher than V _CC , for example, P5
The level is set to V (a pass voltage of about 5 to 6 V at the time of reading), and the control signal Vref is set to a low level (GND level). As a result, all bit lines are charged to Vcc. Further, the memory cell array 101
, The drain side select gate line DSG is set to the V _CC level, and the source side select gate line SSG is set to the GND level.
The channel CH0 of the memory cell transistor of the memory string A0 and the channel CH1 of the memory cell transistor of the memory string A1 are charged to (V _CC -VthDSG). VthDSG is the selection transistors DS0-DS
n is the threshold voltage.

Thereafter, the address decode signals AiB, AiB
The memory string to be written is selected by iN. Here, for example, a case where the memory string A0 is selected as a writing target will be described.
In this case, the control signal Vref is set to a voltage of a predetermined level (for example, 2 V) at which the transistor P101 can flow a current enough to compensate for a leakage current of the bit line BL0 or the like. Further, the address decode signal AiN is set to low level (GND level), and the transistor HN1
04 is turned off and the bit line B on the non-selected side is turned off.
L1 is held in a floating state in a state in which they are charged to Vcc, the channel CH1 of the memory cell transistors of the memory string A1 is held at (V _CC -VthDSG).

After a lapse of a predetermined time, the control signal PGM
Is set to the high level, and the transistor N102 is turned on. As a result, the selected bit line BL0 is connected to the bit line voltage generation circuit 102, and the selected bit line BL0 is set to a voltage according to the write data.

When the write data is "00x" (x: 0 or 1), the transistors N103 and N104 are turned on, a current path indicated by PATH1 in FIG. 9 is formed, and the bit line BL0 is connected to the ground line. Is done. Therefore, bit line BL0 and memory string A0
Is discharged to the GND level.

When the write data is "01x" (x: 0 or 1), the transistors N105 and N106 are turned on, a current path indicated by PATH2 in FIG. 9 is formed, and the bit line BL0 supplies the bit line voltage. Line VB
Connected to L1. Therefore, the bit line BL0 and the channel CH0 of the memory cell transistor of the memory string A0 are discharged to the voltage VB1 (= 1.2V).

When the write data is "10x" (x: 0 or 1), the transistors N107 and N108 are turned on, a current path indicated by PATH3 in FIG. 9 is formed, and the bit line BL0 is supplied with the bit line voltage. Line VB
L2. Therefore, bit line BL0 and channel CH0 of the memory cell transistor of memory string A0 are discharged to voltage VB2 (= 1.5V).

When the write data is "110",
The transistors N109, N110 and N111 turn on,
A current path indicated by PATH4 in FIG. 9 is formed,
Bit line BL0 is connected to bit line voltage supply line VBL3. Therefore, channel CH of memory cell transistor of bit line BL0 and memory string A0
0 is discharged to the voltage VB3 (= 1.5V).

When the write data is "111", no current path is formed, and the bit line BL0 is not connected to any of the ground line and the bit line supply lines VBL1 to VBL3. Accordingly, the bit line BL0 is in a floating state while being charged to Vcc, the channel CH0 of the memory cell transistors of the memory string A0 is held at V _CC -VthDSG.

After the selected bit line BL0 connected to the memory string A0 selected as described above is set to a voltage corresponding to the write data, the word lines WL0 to WL0 are set.
In WL15, the selected word line to be the page to be written is set to the write voltage VPGM, and the other unselected word lines are set to the write pass voltage Vpass (<VPGM).
M), and writing is performed for a predetermined memory cell transistor.

At this time, in a memory cell transistor whose write data is other than "111", Fowler-Nordheim Tunneling is caused by the electric field between the write voltage VPGM applied to the selected word line and the channel voltage of the memory cell transistor. : FN tunneling) phenomenon occurs, and data is written. The channel of the memory cell transistor whose write data is “111” and the channel CH of the memory cell transistor of the memory string A1 on the non-selected side.
1 is disconnected from the bit lines BL0 and BL1 by the drain-side select transistors DS0 and DS1, boosted to a non-write potential by capacitive coupling with the word line,
Data is not written to these memory cell transistors.

An eight-valued NAND configured as described above
In the type flash memory, since write data of different write levels are written in parallel, there is an advantage that the write time is reduced as compared with the case where write data of each level is written step by step.

However, the above-described eight-level NAND
In the write operation of the flash memory, the difference between the ideal bit line voltage and the actual bit line voltage (the ideal value of the channel voltage of the memory cell transistor and the actual Value) is larger. In the actual write operation, the write voltage VPGM applied to the selected word line is started from a predetermined initial voltage, and the write is sequentially performed by gradually increasing the write voltage VPGM at a predetermined step width in an ISPP ( Incremental St
ep Pulse Programming).

Therefore, when performing multi-level parallel writing, the memory cell transistor whose write level is the shallowest, the difference between the ideal bit line voltage and the actual bit line voltage is the largest, and the write data is "110" Must not be overwritten. For this reason, it is necessary to set the write voltage VPGM at the start of writing to a voltage at which the memory cell with the fastest write speed among the memory cells whose write data is “110” reaches the write level in the first write. is there. In this case, the write voltage VPGM starts from a voltage lower than the ideal initial voltage by the difference between the ideal bit line voltage when the write data is “110” and the actual bit line voltage. In a memory cell with a write level deeper than data "110", the electric field at the start of writing is set lower than in an ideal case, and as a result, the number of times of writing increases and the total writing time becomes longer. Inconvenience occurs.

Therefore, an object of the present invention is to apply an ideal voltage corresponding to write data to a channel of a memory cell to be written, while adopting self-boost or local self-boost. An object of the present invention is to provide a nonvolatile semiconductor memory device that can be shortened and a data writing method thereof.

[0042]

In order to achieve the above object, a first aspect of the present invention is to change the amount of charge stored in a charge storage section according to the voltage applied to a word line and a bit line. The threshold voltage changes according to the change, and a plurality of memory cells for storing data having a value corresponding to the threshold voltage are connected, and one end and the other end of the memory cell are controlled in conduction according to the gate voltage. The memory strings connected to the bit line and the source line via the selected transistor are arranged in parallel, the control gates of the memory cells in the same row are connected to a common word line, and n bits (n ≧ n)
The multi-valued data of 2) is written to the memory cells in parallel and in page units. At this time, the channel of the write-protected memory cell is separated from the bit line and boosted to the non-write potential by capacitive coupling with the word line. In a nonvolatile semiconductor memory device, during a write operation, after setting a selected bit line to which a memory cell to be written is connected to a bit line voltage according to write data, the word line voltage is gradually increased in a plurality of steps. At this time, the voltage of the selected bit line is increased at a predetermined timing in accordance with the step of boosting the word line voltage from the memory string and the bit line in order from the shallower write level of the write data. By switching to the voltage that cuts off the selection transistor, the channel of the memory cell to be written is From what the writing level is shallow,
It is characterized by having write control means which is sequentially separated from a selected bit line and boosted by capacitive coupling with a word line.

According to a second aspect of the present invention, the amount of charge stored in the charge storage portion changes according to the voltage applied to the word line and the bit line, and the threshold voltage changes according to the change. A plurality of memory cells for storing data of a value corresponding to the threshold voltage are connected, and one end and the other end are connected to a bit line and a source line via a selection transistor whose conduction state is controlled according to a gate voltage. Memory strings in the same row are connected to a common word line, and n-bit (n ≧ 2) multi-valued data are stored in parallel and in page units. In this case, a non-volatile semiconductor memory device in which the channel of the write-protected memory cell is disconnected from the bit line and boosted to a non-write potential by capacitive coupling with the word line. Setting a selected bit line connected to a memory cell to be written to a bit line voltage according to write data, and stepwise increasing a word line voltage in a plurality of steps. In response to the step of boosting the word line voltage, the voltage of the selected bit line is changed at a predetermined timing, and the selection transistors between the memory string and the bit line are sequentially cut from the shallower write level of the write data. Switching to a voltage to be turned off, and sequentially increasing the channel of the memory cell to be written from the bit line having the lower write data to the selected bit line by capacitive coupling with the word line. It is assumed that.

In the present invention, a nonvolatile semiconductor memory device is typically a NAND flash memory, and a memory cell is composed of a MOS transistor having a floating gate and a control gate.

In the nonvolatile semiconductor memory device according to the present invention, the write control means comprises n latch circuits for latching n-bit write data during a write operation, and a predetermined bit line corresponding to the selected bit line according to the write data. A plurality of bit line voltage supply sources for supplying voltages, and a switching circuit for switching a connection state between the selected bit line and the plurality of bit line voltage supply sources based on data latched in the latch circuit. is there. The process of switching the voltage of the selected bit line to a voltage that cuts off the selection transistor between the memory string and the bit line is performed by switching the voltage of a bit line voltage supply connected to the selected bit line. .

In the present invention, the writing control means includes:
The process of sequentially boosting the channel of the memory cell to be written by the capacitive coupling with the word line from the shallower write level of the write data by changing the channel voltage of the memory cell to be written from the bit line to the channel. This is performed only for a voltage that needs to be set to be equal to or higher than the upper limit of the voltage that can be applied. Thereby, the step of boosting the word line voltage is suppressed to the minimum necessary.

In the present invention, the writing control means includes:
In the first step of the word line voltage boosting step, a process of boosting the channel of the write-protected memory cell to a non-write potential by capacitive coupling with the word line is started,
In the second and subsequent steps of the step of boosting the word line voltage, a process of sequentially boosting the channels of the memory cells to be written by capacitive coupling with the word line is started from the one with the shallower write level of the write data. Thus, the channel of the write-inhibited memory cell is set to the non-write potential, and the channel of the memory cell to be written is set to the channel voltage at the time of writing according to the write data.

In the present invention, the writing control means includes:
The process of setting the selected bit line to the bit line voltage corresponding to the write data is performed after all the bit lines are precharged to a predetermined voltage.

According to the present invention, by gradually increasing the word line voltage in a plurality of steps, the selected word line is finally set to a predetermined write voltage, and the unselected word line is set at a higher voltage than the write voltage. A low write pass voltage is set. These write voltage and write pass voltage are generated by a predetermined booster circuit provided in the nonvolatile semiconductor memory device. In this case, the boosting circuit for generating the write voltage and its control circuit, and the boosting circuit for generating the write pass voltage and its control circuit are configured so that the voltage can be boosted stepwise in a plurality of steps. . The write operation is preferably performed by the ISPP method in which the write voltage is started from a predetermined initial voltage, and the write is sequentially performed while gradually increasing the write voltage with a predetermined step width in a stepwise manner.

In the present invention, at the time of the write operation,
The gate voltage of the selection transistor between the memory string and the bit line is, for example, a V _CC level (V _CC is a power supply voltage).
Is set to In this case, the write control unit performs a process of sequentially switching the voltage of the selected bit line to a voltage that cuts off the selection transistor between the memory string and the bit line, starting with a write data having a low write level. And the voltage of the selected bit line is V
_Switch to _CC level.

In the present invention, the memory cell stores, for example, 8-bit data composed of 3 bits.
In the nonvolatile semiconductor memory device in which 3-bit data is stored in the memory cell, when the gate voltage of the selection transistor is set to the V _CC level, the write control means
For example, when setting the selected bit line to a bit line voltage corresponding to the write data, the write data is set to “00x”.
The bit line voltage in the case of (x: 0 or 1) is 0 V, the bit line voltage in the case where the write data is “01x” (x: 0 or 1) is the voltage VB1 (0 <VB1 <V _CC ), and the write data is The bit line voltage when “10x” (x: 0 or 1) is VB2 (0 <VB2 <V _CC ), and the bit line voltage when the write data is “110” is VB3.
(0 <VB3 <V _cc ), the bit line voltage when the write data is “111” is set to the V _cc level, and the voltage of the selected bit line is sequentially changed from the shallow write data write level to the memory. When performing a process of switching to a voltage at which the selection transistor between the string and the bit line is cut off, the voltage of the selected bit line is switched to the V _CC level to perform multi-level parallel writing.

More specifically, for example, the word line voltage is stepped up in three steps, and in this case, in the first step, all the word lines are stepped up to the first write pass voltage, In the first step, all word lines are boosted to a second write pass voltage higher than the first write pass voltage,
In the third step, finally, the selected word line is set to a write voltage higher than the second write pass voltage, and the unselected word lines are set higher than the second write pass voltage and higher than the write voltage. It is set to a low third write pass voltage. Then, in the first step of the step of boosting the word line voltage, the write control means starts a process of boosting the channel of the write-protected memory cell to a non-write potential by capacitive coupling with the word line, In the second step of the voltage boosting step, the voltage VB
The voltage of the selected bit line set to 3 is switched to the V _CC level to start the process of boosting the channel of the memory cell whose write data is “110” by capacitive coupling with the word line. In the third step, the voltage of the selected bit line set to the voltage VB2 is switched to the V _CC level, so that the channel of the memory cell whose write data is “10x” (x: 0 or 1) is set to the word line. The process of increasing the voltage by the capacitive coupling is started. At this time, preferably, the first write pass voltage is a channel voltage (eg, 3.6) at the time of an ideal write when the channel of the memory cell whose write data is “110” is ideal.
V), and the second write pass voltage is such that the write data is “10x” (x: 0 or 1).
Are selected such that the channel of the memory cell is set to an ideal channel voltage (eg, 2.4 V) at the time of writing.
The third write pass voltage is selected such that the channel of the write-protected memory cell is set to a non-write potential (for example, 8 V).

In the present invention configured as described above, the channel voltage of the memory cell to be written is changed by disconnecting the channel of the memory cell from the selected bit line.
By boosting by capacitive coupling with the word line,
Supplying a voltage equal to or higher than the upper limit of the pass voltage of the selection transistor between the memory cell array and the bit line (the voltage that can be applied from the bit line to the channel of the memory cell) to the channel of the memory cell to be written. Is possible. Therefore, during a write operation, the word line voltage is stepped up in a plurality of steps, and at this time, the voltage of the selected bit line is changed at a predetermined timing according to the step of boosting the word line voltage. In order from the shallow level, the voltage is switched to the voltage at which the selection transistor between the memory string and the bit line is cut off, and the channel of the memory cell to be written is changed.
The ideal level corresponding to the write data while self-boost or local self-boost is adopted by sequentially separating from the selected bit line and boosting it by capacitive coupling with the word line, starting from the shallow write data level. Voltage can be applied to the channel of the memory cell to be written.

[0054]

Embodiments of the present invention will be described below with reference to the drawings.

FIGS. 1 and 2 show an 8-level NAND flash memory according to an embodiment of the present invention. FIG. 1 shows a configuration of a main part of the eight-level NAND flash memory, and FIG. 2 shows an equivalent circuit of a memory cell array of the eight-level NAND flash memory. This NAND flash memory includes a memory cell array 1, a bit line voltage generation circuit 2, a read / verify control circuit 3, and the like.

As shown in FIG. 2, the memory cell array 1 has, for example, a floating gate (FG) and a control gate (CG), and includes MOS transistors (memory cell transistors) each functioning as a 3-bit memory cell. The memory cells in the same row are arranged in a matrix and shared by common word lines WL0 to WL
It is composed of memory strings A0 to An connected to L15. Note that FIG. 2 omits the memory string A2 and thereafter.

One memory string has a plurality of memory cell transistors connected in series. The memory string A0 includes memory cell transistors M _0-0 to
M _15-0 . The drain of the memory cell transistor _M15-0 is connected to the source of the selection transistor DS0, and the drain of the selection transistor DS0 is connected to the bit line BL0. On the other hand, the source of the memory cell transistor M _0-0 is connected to the drain of the selection transistor SS0, and the source of the selection transistor SS0 is connected to the source line SL. The control gates of the memory cell transistors M _{0-0 to} M _15-0 are connected to word lines WL0 to WL15, respectively. Similarly,
The memory string A1 includes a memory cell transistor M
It is composed of _0-1 ~M _15-1. The drain of the memory cell transistor _M15-1 is connected to the source of the selection transistor DS1, and the drain of the selection transistor DS1 is connected to the bit line BL1. On the other hand, the source of the memory cell transistor M _0-1 is connected to the drain of the selection transistor SS1, and the source of the selection transistor SS1 is connected to the source line SL. The control gates of the memory cell transistors M _{0-1 to} M _15-1 are connected to word lines WL0 to WL15, respectively.

As described above, the memory strings A0 and A1 are connected to the respective lines, and the other memory strings A2 to An have the same connection relationship. Therefore, one ends of the memory strings A0 to An are connected to the bit lines BL0 to BLn through the selection transistors DS0 to DSn, and the other ends of the memory strings A0 to An are connected to the source lines SL through the selection transistors SS0 to SSn. It is connected. The gates of the select transistors DS0 to DSn are connected to a common drain-side select gate line DSG, and the gates of the select transistors SS0 to SSn are connected to a common source-side select gate line SSG. In the memory cell array 1, the memory strings A0 to An as described above are arranged in parallel.

As shown in FIG. 1, a bit line voltage generation circuit 2 provided corresponding to bit lines BL0 and BL1 connects transistors N1 to N14 formed of n-channel MOS transistors and the inputs and outputs of an inverter. LQ2, LQ1, LQ0 and a transistor P1 composed of a p-channel MOS transistor. From the bit line voltage generation circuit 2, bit line voltage supply lines VBL1, VBL2, and VBL3 connected to a predetermined constant voltage source are derived. This NAND flash memory employs a configuration (bit line shared) in which two bit lines are selectively connected to one bit line voltage generation circuit 2 including latch circuits LQ2 to LQ0. Note that the bit line voltage generation circuits corresponding to the bit line BL2 and subsequent bits have the same configuration, and a description of these portions will be omitted for simplicity. Also, regarding other circuit portions, only portions corresponding to the bit lines BL0 and BL1 are noted, and only the portions will be described.

At the time of writing, a bit line voltage corresponding to write data is generated by the bit line voltage generation circuit 2, and the bit line voltage is applied to the channel of the memory cell transistor of the memory cell array 1 through the bit lines BL0 and BL1. At the time of verification, when the storage nodes Q2, Q1, and Q0 of the latch circuits LQ2, LQ1, and LQ0 of the bit line voltage generation circuit 2 are sufficiently written into the memory cell transistors of the memory cell array 1,
It is set to “111”. At the time of reading, the threshold voltage of the memory cell transistor of the memory cell array 1 is detected, and data is read. At this time, the storage nodes Q2, Q1, L1 of the latch circuits LQ2, LQ1, LQ0
The read data is decoded and set to Q0.

The read / verify control circuit 3 includes a transistor N15 comprising an n-channel MOS transistor.
To N41. The read / verify control circuit 3 performs a read operation or a verify operation
It controls the states of the latch circuits LQ2, LQ1, LQ0. From the read / verify control circuit 3, supply lines for control signals φLAT0 to φLAT9 are derived. A pulse signal is supplied to a supply line of the control signals φLAT0 to φLAT9.

Between bit line BL0 and node SA,
Transistors HN1 and HN3 formed of a high breakdown voltage n-channel MOS transistor are connected in series. A transistor H composed of a high-breakdown-voltage n-channel MOS transistor is provided between the bit line BL1 and the node SA.
N2 and HN4 are connected in series. A common control signal TRN is supplied to the gates of the transistors HN1 and HN2. The gate of the transistor HN3 is supplied with the address decode signal AiB, and the gate of the transistor HN4 is supplied with the address decode signal AiN.

[0063] In the bit line voltage generating circuit 2, the node SA and the power supply voltage Vcc (V _CC is eg, 3.3V) and the transistor P1 is connected between the supply line of the. The control signal Vref is supplied to the gate of the transistor P1. Further, a transistor N1 is connected between the node SA and the ground line GND. The control signal DIS is supplied to the gate of the transistor N1.

In the bit line voltage generation circuit 2, the drain of the transistor N2 is connected to the node SA. The source of the transistor N2 is the transistor N
3, N5, N7 and N9 are connected to the drains. The control signal PGM is supplied to the gate of the transistor N2.

The transistors N3 and N4 are connected in series between the source of the transistor N2 and the ground line. Transistors N5 and N6 are connected in series between the source of the transistor N2 and the bit line voltage supply line VBL1. The transistors N7 and N8 are connected between the source of the transistor N2 and the bit line voltage supply line VBL2.
Are connected in series. Transistors N9, N10 and N11 are connected in series between the source of the transistor N2 and the bit line voltage supply line VBL3. In addition,
In the NAND flash memory according to this embodiment, the power supply for supplying the bit line voltage at the GND level is the ground line as described above. Is further provided, and a transistor N3 is provided between the source of the transistor N2 and the bit line voltage supply line VBL0.
N4 may be connected in series.

Latch circuits LQ2, LQ1, LQ0 have storage nodes Q2, Q1, Q0, respectively, and their inverted storage nodes / Q2, / Q1, / Q0. In addition, / means a bar indicating inversion.

Inverting storage node / Q2 of latch circuit LQ2
Is connected to the gates of transistors N4 and N6, and storage node Q2 is connected to the gates of transistors N7 and N9. Inverting storage node / Q1 of latch circuit LQ1 is connected to the gates of transistors N3 and N8, and storage node Q1 is connected to the gates of transistors N5 and N10. Inverting storage node / Q0 of latch circuit LQ0 is connected to the gate of transistor N11.

The storage node Q of the latch circuit LQ2
2. Storage node Q1 of latch circuit LQ1, latch circuit L
Transistors N12, N13 and N14 are connected between each of the storage nodes Q0 of Q0 and the ground line. A reset signal RST is supplied to gates of the transistors N12, N13, and N14.

In the read / verify control circuit 3, the gates of the transistors N15, N16 and N17 are
It is connected to the node SA of the bit line voltage generation circuit 2. The drain of the transistor N15 is connected to the latch circuit LQ2.
Of the transistor N1
6 is the inverted storage node / Q of the latch circuit LQ1.
1 and the drain of the transistor N17 is connected to the inverted storage node / Q0 of the latch circuit LQ0.

The transistor N18 is connected between the source of the transistor N15 and the ground line.
In parallel with this, transistors N19, N20, N21 are connected in series.

The source of the transistor N16 is connected to the drain of the transistor N22 and the drain of the transistor N27. Transistors N23 and N24 are connected in series between the source of the transistor N22 and the ground line, and are connected in parallel with the transistors N23 and N24.
25 and N26 are connected in series. Transistor N
27 between the source of C.27 and the ground line.
8, N29 are connected in series, and transistors N30, N31 are connected in series in parallel with this.

The source of the transistor N17 is connected to the drain of the transistor N32 and the drain of the transistor N37. Transistors N33 and N34 are connected in series between the source of the transistor N32 and the ground line, and are connected in parallel with the transistors N33 and N34.
35 and N36 are connected in series. Transistor N
37 between the source of C.37 and the ground line.
8, N39 are connected in series, and transistors N40, N41 are connected in series in parallel with this.

From the read / verify control circuit 3,
Supply lines for the control signals φLAT0 to φLAT9 are derived. The control signal φLAT is applied to the gate of the transistor N18.
0 is supplied. The control signal φLAT1 is supplied to the gate of the transistor N21. The control signal φLAT2 is supplied to the gate of the transistor N24. Transistor N
The control signal φLAT3 is supplied to the gate 26. The control signal φLAT4 is supplied to the gate of the transistor N29. The control signal φLAT is applied to the gate of the transistor N31.
5 are supplied. The control signal φLAT6 is supplied to the gate of the transistor N34. The control signal φLAT7 is supplied to the gate of the transistor N36. Transistor N
The control signal φLAT8 is supplied to the gate 39. The control signal φLAT9 is supplied to the gate of the transistor N41.

Inverting storage node / Q2 of latch circuit LQ2
Are connected to the gates of transistors N27 and N37, and storage node Q2 is connected to the gates of transistors N22 and N32. Inverting storage node of latch circuit LQ1 /
Q1 is connected to the gates of transistors N35 and N40, and storage node Q1 is connected to the gates of transistors N33 and N38. Inverted storage node / Q0 of latch circuit LQ0 is connected to the gates of transistors N28 and N23, and storage node Q0 is connected to transistors N30 and N2.
5, N20.

Then, storage node Q of latch circuit LQ2
2 is connected between the storage node Q1 of the latch circuit LQ1 and the bus line IO2, and the transistor N52 is connected between the storage node Q1 of the latch circuit LQ1 and the bus line IO1. Is connected to the transistor N53. Also, transistors N51, N52, N53 as column gates
Are connected to the supply line of the signal Y1_0.

Although not shown, the NAND flash memory has a booster circuit for generating a predetermined voltage to be supplied to each signal line, and a control circuit therefor. More specifically, this NAND flash memory includes a booster circuit for generating a write voltage VPGM and a control circuit therefor, a booster circuit for generating a write pass voltage and a control circuit therefor, and P5V (a pass voltage at the time of reading, for example, 5V). (About 6 V) and a booster circuit for generation and a control circuit therefor.

In the NAND flash memory according to this embodiment having the above-described structure, data having three bits and having eight values is recorded in one memory cell transistor. The distribution of the threshold voltage Vth of the data having three bits and taking eight values and the data contents have a correspondence relationship as shown in FIG. 7, for example.

More specifically, in FIG. 7, distribution 7 has a seventh positive threshold voltage Vth
Is the distribution of the memory cell transistors in the write state, and distribution 6 is the distribution of the data “001”.
Is the distribution of the memory cell transistors in the write state of the positive threshold voltage Vth, and distribution 5 is the data “01”.
"0" is written and the distribution of the memory cell transistors is set to the written state of the fifth positive threshold voltage Vth, and distribution 4 is the fourth positive threshold voltage when data "011" is written. The distribution of the memory cell transistors in the Vth write state is shown in FIG.
Is the distribution of the memory cell transistors in which the third positive threshold voltage Vth is written and the second positive threshold voltage Vth is written when data "101" is written. Distribution 1 is a distribution of memory cell transistors in a write state, and distribution 1 is a distribution of memory cell transistors in which data “110” is written and in a write state of a first positive threshold voltage Vth. In FIG. 7, distribution 0 is a distribution of memory cell transistors in which data "111" is written and erased with a negative threshold voltage Vth.

In FIG. 7, the selected word line voltage for each state at the time of reading in the verify operation described later is VVF1, VVF2, VVF3, VVF4, VVF5, VVF6, VVF7.
And the selected word line voltage for each state during normal read is VRD1, VRD2, VRD3, VRD4, VRD5, VRD6, VRD7.
Indicated by The magnitude relation is VVF7>VRD7> V
VF6>VRD6>VVF5>VRD5>VVF4>VRD4> VVF
3>VRD3>VVF2>VRD2>VVF1> VRD1. For example, VVF7 = 3.8V, VRD7 = 3.
6V, VVF6 = 3.2V, VRD6 = 3.0V, VVF5 =
2.6V, VRD5 = 2.4V, VVF4 = 2.0V, VRD4
= 1.8V, VVF3 = 1.4V, VRD3 = 1.2V, V
VF2 = 0.8V, VRD2 = 0.6V, VVF1 = 0.2
V, VRD1 = 0V.

A write operation, a verify operation, and a normal read operation in the NAND flash memory according to the embodiment configured as described above will be described below.

First, a write operation of the NAND flash memory according to the embodiment will be described. FIG.
FIG. 3 shows the states of signals at various parts in the write operation of the NAND flash memory according to the embodiment. Here, it is assumed that the memory string A0 is selected as a writing target. This write operation is referred to as an ISPP in which a write voltage VPGM applied to a selected word line is started from a predetermined initial voltage, and writing is sequentially performed while gradually increasing the write voltage VPGM stepwise with a predetermined step width. It is done in the way that is done.

Before the write operation, the control signal PGM is set to the low level (GND level), the transistor N2 is turned off, and the bit lines BL0 and BL1 are disconnected from the write control circuit 2. And the control signal DI
S goes to the high level (Vcc level), and the control signal TRN and the address decode signals AiB and AiN become (Vcc-Vt).
h) Set to level. At this time, the transistor H
N1, HN2, HN3, HN4 and transistor N1
Are on, all bit lines are grounded. The bit line voltage supply line VBL1 is connected to the voltage VB
1, the bit line voltage supply line VBL2 is the voltage VB2
The bit line voltage supply line VBL3 is set to the voltage VB3. These voltages VB1, VB2, VB3 is larger V _CC smaller voltage than 0V, As an example, the voltage VB1 = 1.2V, the voltage VB2 = 1.5V,
The voltage VB3 = 1.5V.

When writing is started in this state, write data is supplied to the latch circuits LQ2, LQ1, LQ0 of the bit line voltage generation circuit 2 via the data bus, and the write data is supplied to the latch circuit LQ.
2, LQ1 and LQ0. Thereafter, the control signal DIS is switched to low level, and the bit lines BL0 and BL1 are disconnected from the ground line. Then, the control signal TRN and the address decode signal Ai
B, AiN is a predetermined high level equal to or higher than V _CC , for example, P5
At the same time, the control signal Vref is set to the low level (GND level). As a result, all bit lines are charged to Vcc. In addition, the memory cell array 1
, The drain side select gate line DSG is set to the V _CC level, and the source side select gate line SSG is set to the GND level.
The channel CH0 of the memory cell transistor of the memory string A0 and the channel CH1 of the memory cell transistor of the memory string A1 are charged to (V _CC -VthDSG). VthDSG is the selection transistors DS0, DS
1 is the threshold voltage.

Thereafter, the address decode signals AiB, A
The memory string to be written is selected by iN. Here, for example, a case where the memory string A0 is selected as a writing target will be described.
In this case, the control signal Vref is set to a voltage of a predetermined level (for example, 2 V) at which the transistor P1 can supply a current enough to compensate for the leakage current of the bit line BL0 or the like. Further, the address decode signal AiN is set to the low level (GND level), the transistor HN4 is turned off, and the bit line BL1 on the non-selected side is set to the V level.
It is held in a floating state while being charged to cc,
Channel CH1 of the memory cell transistors of the memory string A1 is held at (V _CC -VthDSG) level.

After a lapse of a predetermined time, the control signal PGM
Is set to the high level, and the transistor N2 is turned on. As a result, the selected bit line BL0 and the bit line voltage generation circuit 2 are connected, and the selected bit line BL0
Is set to a voltage corresponding to the write data.

When the write data is "00x" (x: 0 or 1), the transistors N3 and N4 are turned on,
Bit line BL0 is connected to a ground line. Therefore, bit line BL0 and channel CH0 of the memory cell transistor of memory string A0 are discharged to the GND level.

When the write data is "01x" (x: 0 or 1), the transistors N5 and N6 turn on,
Bit line BL0 is connected to bit line voltage supply line VBL1. Therefore, channel CH of memory cell transistor of bit line BL0 and memory string A0
0 is discharged to the voltage VB1 (= 1.2V).

When the write data is "10x" (x: 0 or 1), the transistors N7 and N8 are turned on,
Bit line BL0 is connected to bit line voltage supply line VBL2. Therefore, channel CH of memory cell transistor of bit line BL0 and memory string A0
0 is discharged to the voltage VB2 (= 1.5V).

When the write data is "110",
The transistors N9, N10, N11 are turned on, and the bit line BL0 is connected to the bit line voltage supply line VBL3. Therefore, the bit line BL0 and the channel CH0 of the memory cell transistor of the memory string A0 are discharged to the voltage VB3 (= 1.5V).

When the write data is "111", no current path is formed, and the bit line BL0 is not connected to any of the ground line and the bit line supply lines VBL1 to VBL3. Accordingly, the bit line BL0 is in a floating state while being charged to Vcc, the channel CH0 of the memory cell transistors of the memory string A0 is held at V _CC -VthDSG.

As described above, the selected bit line BL0 connected to the selected memory string A0 is set to a voltage corresponding to the write data. Here, in the NAND flash memory before the present invention is applied, after that, of the word lines WL0 to WL15, the selected word line set as the page to be written is set to the write voltage VPG.
M, the other unselected word lines are set to the write pass voltage Vpass (<VPGM), and data has been written to a predetermined memory cell transistor. At the time of this write operation, the voltages of the bit line voltage supply lines VBL1, VBL2, VBL3 are set to the voltage VB1 (= 1.2V) and the voltage VB2, respectively.
(= 1.5 V) and the voltage VB3 (= 1.5 V).

On the other hand, the NA according to this embodiment is
In the ND type flash memory, as described below, the word line voltage VWL is stepped up in three steps, and at this time, all word lines are set to Vpa in the first step up.
ss1 and all word lines are V
After the voltage is increased to pass2, the voltage of the selected word line is increased to the write voltage VPGM and the voltage of the non-selected word line is increased to the write pass voltage Vpass in the third voltage increase step. Here, Vpass1 and Vpass2 are write pass voltages,
It is a voltage that satisfies the relationship of Vpass1 <Vpass2 <Vpass. Then, the selected bit line in the state set to the bit line voltage according to the write data is sequentially switched from the one with the lower write level to the V _CC level corresponding to the step of boosting the word line voltage VWL. This process
In the case of performing ideal writing, the write data that requires a channel voltage higher than the upper limit of the voltage that can be applied from the bit line is “110” and “10x”.
(X: 0 or 1) only when the write data is “01x” (x: 0 or 1).
In the case of “00x” (x: 0 or 1), the voltage of the selected bit line is maintained in the set state.

That is, the NAND according to this embodiment is
In the type flash memory, after the bit line BL0 is set to the voltage corresponding to the write data as described above,
Bit line voltage supply lines VBL1, VBL2, VBL3
Are voltages VB1 (= 1.2V) and V
With B2 (= 1.5 V) and VB3 (= 1.5 V) set, the voltage VWL of all word lines is boosted to the first write pass voltage Vpass1 (first boosting step).

At this time, the channel CH0 of the memory cell transistor whose write data is “111” is cut off from the bit line BL0 by the cutoff of the drain-side select transistor DS0 of the memory string A0, and the word line (mainly the non- Boosted by capacitive coupling with the selected word line). Write data is "00x"
The channel CH0 of the memory cell transistor (x: 0 or 1) is held at the GND level, and the channel CH0 of the memory cell transistor whose write data is “01x” (x: 0 or 1) has the voltage VB1 (= 1.2 V). And the write data is “10x” (x: 0 or 1)
Channel CH0 of the memory cell transistor of
2 (= 1.5 V) and the write data is “11
The channel CH0 of the memory cell transistor “0” is held at the voltage VB3 (= 1.5 V).

Next, after a lapse of a predetermined time, the word line voltage VWL
While holding the pass voltage Vpass1 write, the bit line voltage supply line VBL3 is switched from the voltage VB3 (= 1.5V) to V _CC level. Accordingly, the write data connected to the bit line voltage supply line VBL3 is the bit line BL0 of "110" is charged to (V _CC -VthN) level. VthN is a threshold voltage of the transistor N2. The threshold voltage VthN of the transistor N2
Is lower than the threshold voltage VthDSG of the drain side select transistors DS0 memory string A0, after the write data channel CH0 of the memory cell transistor of the "110" is charged to (V _CC -VthDSG) level, the memory The selection transistor DS0 on the drain side of the string A0 is cut off. Thereafter, the voltage VWL of all the word lines is changed to the second write pass voltage Vpass2 (where
The voltage is boosted to pass1 <Vpass2 <Vpass (second boosting step).

At this time, the channel CH0 of the memory cell transistor whose write data is “110” is connected to the bit line B by the cutoff of the select transistor DS0.
It is separated from L0 and boosted to a predetermined potential mainly by capacitive coupling with an unselected word line. However, this potential is a potential that does not reach the channel voltage at the time of writing when the write data is “110”. Channel CH of the memory cell transistor whose write data is “111”
0 and the channel CH1 of the memory cell transistor of the non-selected memory string A1 are boosted to a higher potential. The channel CH0 of the memory cell transistor whose write data is “00x” (x: 0 or 1) is held at the GND level, and the write data is “01x”.
The channel CH0 of the memory cell transistor (x: 0 or 1) is held at the voltage VB1 (= 1.2 V), and the channel CH0 of the memory cell transistor whose write data is “10x” (x: 0 or 1) is at the voltage VB2. (= 1.
5V).

Next, after a certain period of time, the word line voltage VWL
While holding pass voltage Vpass2 write, the bit line voltage supply line VBL2 is switched from voltage VB2 (= 1.5V) to V _CC level. At this time, the write data connected to the bit line voltage supply line VBL2 is “1”.
The bit line BL0 of “0x” (x: 0 or 1) is connected to (V _CC −
VthN) level. Therefore, after the channel CH0 of the memory cell transistor whose write data is “10x” (x: 0 or 1) is charged to the (V _CC −VthDSG) level, the select transistor DS0 on the drain side of the memory string A0 is cut off. . Thereafter, the selected word line is boosted to the write voltage PGM, and the unselected word line is set to the final third write pass voltage Vpass.
(Third boosting step).

At this time, the write data is “10x”
The channel CH0 of the memory cell transistor (x: 0 or 1) is cut off from the bit line BL0 by the cutoff of the select transistor DS0, and the write data is written by capacitive coupling with the word line (mainly an unselected word line). Is boosted to the channel voltage at the time of writing when “x” is “10x”. The channel CH0 of the memory cell transistor whose write data is “110” is boosted to a higher predetermined potential, and the write data becomes “11”.
It is boosted to the channel voltage at the time of writing in the case of "0". The channel CH0 of the memory cell transistor whose write data is “111” and the channel CH1 of the memory cell transistor of the non-selected memory string A1 are
Boosted to non-write potential. The channel CH0 of the memory cell transistor whose write data is “00x” (x: 0 or 1) is held at the GND level, and the channel CH0 of the memory cell transistor whose write data is “01x” (x: 0 or 1) has the voltage VB1. (= 1.2
V).

After the first to third boosting steps, the selected word line is finally set to the write voltage VPGM, and the unselected word line is set to the write pass voltage VPGM.
The pass is set, and data is written to a predetermined memory cell transistor. At this time, the channel voltage of the memory cell transistor corresponding to each write data is as follows.

That is, when the write data is "111", the selection transistor DS0 on the drain side of the memory string A0 is cut off when the bit line voltage is initially set according to the write data. Therefore, the channel CH0 of the memory cell transistor whose write data is “111” is boosted by the capacitive coupling with the word line (mainly a non-selected word line) at the same time as the start of the first boosting step of the word line voltage VWL. Become like After the selection transistor DS0 is cut off, the amount of charge stored in the memory cell transistor is preserved before and after the boost. Therefore, as shown equivalently in FIG. 4, the non-selected word lines are connected to the final write pass voltage V.
At the time of pass, the charge amount Q of the memory cell transistor whose write data is “111” is: Q = −Cins × (Vpass0−Vch0) + Cch0 × Vch0 = −Cins × (Vpass−Vch (111)) + Cch0 ′ × Vch (111) (1) Where Cins: series capacitance between channel-FG and FG-CG Cch0: depletion layer capacitance before boost Cch0 ': depletion layer capacitance after boost (varies according to Vch (111)) Vch0: channel voltage before boost Vch (111): Channel voltage after boost Vpass0: Word line voltage before boost Vpass: Word line voltage after boost. Here, the voltage Vpass0 is a voltage before the word line is boosted to the write pass voltage Vpass1, and can be arbitrarily set as needed. Here, this voltage Vpass0 is set to, for example, 0V. (1)
From the equation, Vch (111) is

[0101]

(Equation 1)

Is obtained. This Vch (111) corresponds to the non-writing potential. Note that when the unselected word line becomes the final write pass voltage Vpass, the channel of the memory cell transistor of the unselected memory string A1 also becomes
The voltage becomes equal to this Vch (111).

When the write data is "110", the word line voltage VWL is boosted to the write pass voltage Vpass1,
The bit line voltage supply line VBL3 is connected to the voltage VB3 (= 1.
After being switched to V _CC level from 5V), the selection transistor DS0 on the drain side of the memory string A0 is cut off. Therefore, the write data is "11
The channel CH0 of the memory cell transistor “0” is set at the same time as the start of the second step of boosting the word line voltage VWL.
It is boosted by capacitive coupling with word lines (mainly unselected word lines). Also at this time, the charge amount of the channel of the memory cell transistor is stored before and after the boost, so that when the unselected word line becomes the final write pass voltage Vpass, this write data is set to “1”.
The charge amount Q of the "10" memory cell transistor is as follows: Q = -Cins * (Vpass1-Vch1) + Cch1 * Vch1 = -Cins * (Vpass-Vch (110)) + Cch1 '* Vch (110) (3) Where Cins: series capacitance between channel-FG and FG-CG Cch1: depletion layer capacitance before boost Cch1 ′: depletion layer capacitance after boost (varies according to Vch (110)) Vch1: channel voltage before boost Vch (110): Channel voltage after boost Vpass1: Word line voltage before boost Vpass: Word line voltage after boost. From equation (3), Vch (110) is

[0104]

(Equation 2)

The following is obtained. This Vch (110) corresponds to the channel voltage at the time of writing when the write data is "110".

When the write data is “10x” (x: 0 or 1), the word line voltage VWL is
pass2 boosted to the bit line voltage supply line VBL2 is after being switched from the voltage VB2 (= 1.5V) to V _CC level, the selection transistor DS0 on the drain side of the memory string A0 is cut off. Therefore, the channel CH0 of the memory cell transistor whose write data is “10x” is boosted by the capacitive coupling with the word line (mainly the unselected word line) at the same time as the start of the third boosting step of the word line voltage VWL. Become like Also at this time, since the charge amount of the channel of the memory cell transistor is stored before and after the boost, when the non-selected word line becomes the final write pass voltage Vpass, this write data is stored in the memory cell transistor of “10x”. The charge amount Q is as follows: Q = −Cins × (Vpass2−Vch2) + Cch2 × Vch2 = −Cins × (Vpass−Vch (10x)) + Cch2 ′ × Vch (10x) (5) Where Cins: series capacitance between channel-FG and FG-CG Cch2: depletion layer capacitance before boost Cch2 ': depletion layer capacitance after boost (varies according to Vch (10x)) Vch2: channel voltage before boost Vch (10x): Channel voltage after boost Vpass2: Word line voltage before boost Vpass: Word line voltage after boost. From equation (5), Vch (10x) is

[0107]

(Equation 3)

Is obtained. This Vch (10x) corresponds to the channel voltage at the time of writing when the write data is "110".

When the write data is "0xx" (x: 0 or 1), the select transistor DS0 on the drain side of the memory string A0 is not cut off. Therefore, the voltage of the bit line BL0 is supplied as it is to the channel CH0 of the memory cell transistor whose write data is “0xx”. In summary, when the selected word line is set to the write voltage VPGM and the unselected word line is set to the write pass voltage Vpass, the channel voltage of the memory cell transistor corresponding to each write data is:

[0110]

(Equation 4)

Is obtained. In these equations, Vpass1,
If Vpass2 is determined, Cch1, Cch1 ', Vch1, Cch2,
Cch2 'and Vch2 are automatically determined, and Vch (10x) and Vch (1
10) is also determined. In this embodiment, Vpass1 and Vpass2 are determined so that Vch (10x) = 2.4V and Vch (110) = 3.6V.

As described above, by applying the voltage corresponding to the write data to the channel of the memory cell transistor, in the memory cell transistors whose write data is other than “111”, the write voltage VPGM applied to the selected word line is reduced. An FN tunneling phenomenon occurs due to an electric field with the channel voltage of the memory cell transistor, and data is written. When the write data is "11
The channel CH0 of the memory cell transistor “1” and the channel CH1 of the memory cell transistor of the non-selected memory string A1 are separated from the bit lines BL0 and BL1 by the drain-side selection transistors DS0 and DS1, and are connected to the word line (mainly The potential is boosted to the non-write potential by capacitive coupling with the selected word line, and no data is written to these memory cell transistors.

In the above-described write operation, an ideal voltage corresponding to write data can be applied to the channel of the memory cell transistor. can do. This makes it possible to write all the write data having different write levels almost simultaneously.

Next, the verify operation will be described.
FIG. 5 shows the states of signals at various parts in the verify operation of the NAND flash memory according to this embodiment. Here, following the above-described write operation,
It is assumed that the memory string A0 is selected as a verification target.

As described above, while the selected word line is set to the write voltage VPGM and the unselected word lines are set to the write pass voltage Vpass, data is written to the memory cell transistors for a predetermined time. was followed, with the word line voltage VWL is set to the GND level, the control signal PGM is switched from V _CC level to the GND level, the bit line BL0 and bit line voltage generating circuit 2
And is separated. Then, the control signal DIS is set to the high level, the address decode signal AiN is set to the P5V level, and the address decode signal AiB and the control signal TRN are set to the P5V level while writing, and during this time, all the bit lines are grounded. You. After a certain period of time, the control signal TRN is set to the GND level, and after a certain period of time, the control signal DIS is switched to the GND level. When the address decode signal AiN is G
Is set to ND level, the bit line BL1 of the non-selected side is in a floating state, the control signal TRN is set to (V _CC -Vth) level. At this time, the selected bit line BL0 is connected to the node SA because the address decode signal AiB is at the P5V level.

In this verify operation, every time one write is completed, data "000", "001", "01"
0 "," 011 "," 100 "," 101 "," 11 "
The determination of the threshold voltage Vth corresponding to "0" is performed. This determination of the threshold voltage Vth is performed after the control signal DIS is switched to the low level, and then the drain-side selection gate line DS
G and the source-side select gate line SSG are set to the same predetermined high-level voltage as the voltage of the unselected word line, for example, P5V, and the voltage VWL of the selected word line is changed to, for example, VVF7 → V
It is performed while gradually lowering in the order of VF6 → VVF5 → VVF4 → VVF3 → VVF2 → VVF1.

First, as a pre-process for determining the actual threshold voltage Vth at each word line voltage, the control signal Vref is set to a low level (GND level), the transistor P1 is turned on, and the bit line BL0 is turned on. Charging at the power supply voltage Vcc is performed. After a certain period of time, the bit line B
The voltage of L0 rises, and the potential difference between the gate and source of the transistor HN1 becomes Vth '(Vth' is the transistor HN1
, The transistors HN1 and HN3 are automatically turned off. Therefore, bit line BL
0 is the (Vcc-Vth-Vth ') level (for example, about 1 V)
, And the node SA goes to the Vcc level.

In the state described above, the voltage of the selected word line is set to a predetermined value, and the presence / absence of the cell current is determined by the bit lines BL0 and The threshold voltage Vth is determined by reflecting the threshold voltage Vth on the voltage of the node SA. That is,
When a voltage equal to or higher than the threshold voltage Vth of a predetermined memory cell transistor is supplied to its control gate and a cell current flows, the voltage of bit line BL0 drops, and transistors HN1 and HN3 are turned on. Therefore, the node SA is the voltage of the bit line BL0 (V _CC -Vth-Vth
)). When a voltage lower than the threshold voltage Vth of a predetermined memory cell transistor is supplied to its control gate, no cell current flows, the voltage of bit line BL0 does not drop, and the voltage of node SA does not decrease. Are kept at the Vcc level. The threshold voltage Vth is determined based on this relationship.

When the charging of the bit line BL0 is completed, the control signal Vref is set to a voltage of a predetermined level (for example, 2 V) at which the transistor P1 can supply a current sufficient to compensate for the leakage current of the bit line BL0. .

First, the voltage VWL of the selected word line is set to VVF7, and the threshold voltage Vth corresponding to the write data "000" is determined. Here, the threshold voltage Vth of the memory cell transistor is higher than VVF7 (V
th> VVF7), since no current flows through the cell, the voltage of the bit line BL0 does not change and the node SA
Held at cc level. At this time, the transistor N1
5, N16 and N17 are turned on.

After a lapse of a predetermined time, control signals φLAT0, φLAT2, and φLAT6, which are pulse signals, are sequentially set to a high level.

When the control signal φLAT0 is set to the high level, the transistor N18 is turned on. At this time, the transistor N15 is turned on.
The inverted storage node / Q2 of Q2 is set to low level, and storage node Q2 is inverted from low level to high level. At this time, the gates of the transistors N22 and N32 connected to the storage node Q2 of the latch circuit LQ2 go high.

When control signal φLAT2 is set to a high level, transistor N24 is turned on. At this time, transistors N23, N22 and transistor N16 are turned on, so that inverted storage node / Q1 of latch circuit LQ1 is at a low level. And the storage node Q1 is inverted from the low level to the high level. At this time, the gate of the transistor N33 connected to the storage node Q1 of the latch circuit LQ1 goes high.

When control signal φLAT6 is set to the high level, transistor N34 is turned on. At this time, transistors N33, N32 and transistor N17 are turned on, so that inverted storage node / Q0 of latch circuit LQ0 is at the low level. And the storage node Q0 is inverted from low level to high level.

As described above, the write data is "000".
If the threshold voltage Vth is larger than VVF7 (Vth> VVF7), the latch circuit L
The latch data of Q2, LQ1, and LQ0 are inverted to "111", and are in a write-inhibited state.

On the other hand, when the threshold voltage Vth of the memory cell transistor is smaller than VVF7 (Vth <VVF7), a cell current larger than the leakage compensation current flows, the voltage of the node SA drops, and the transistors HN1 and HN3 are turned on. ,
The capacitance CBL of the bit line BL0 and the capacitance CSA of the node SA (<
<Occur redistribution of charge between CBL), the voltage at the node SA is the voltage (V _CC -Vth-Vth') and almost the same low level of the bit line BL0 (for example, about 1V). Therefore, the control signals φLAT0, φLAT2, φLAT6
Therefore, even if the transistors N18, N24, and N34 are turned on, the gates of the transistors N15, N16, and N17 are at a low level (for example, 1 V). The latch circuits LQ2 to LQ
A current required to invert the storage nodes Q2 to Q0 of 0 cannot flow, and as a result, the set state is maintained.

When the determination of the threshold voltage Vth in a state where the voltage VWL of the selected word line is set to VVF7 is completed, the control signal Vref is set to the low level again, the transistor P1 is turned on, and the bit line BL0 Is charged at the power supply voltage Vcc. When the charging of the bit line BL0 is completed, the control signal Vref becomes a voltage of a predetermined level (for example,
2V).

Next, the voltage VWL of the selected word line is set to VVF6, and the threshold voltage Vth corresponding to the write data "001" is determined. Here, the threshold voltage Vth of the memory cell transistor is higher than VVF6 (V
th> VVF6), no current flows through the cell, the voltage of the bit line BL0 does not change, and the node SA
Held at cc level. At this time, the transistor N1
5, N16 and N17 are turned on.

After a lapse of a predetermined time, the control signals φLAT5 and φLAT1 which are pulse signals are sequentially set to the high level.

When control signal φLAT5 is set to the high level, transistor N31 is turned on. At this time, transistors N30 and N27 and transistor N16 are turned on, so that inverted storage node / Q1 of latch circuit LQ1 is at the low level. And the storage node Q1 is inverted from low level to high level. At this time, the gate of the transistor N19 connected to the storage node Q1 of the latch circuit LQ1 goes high. When the threshold voltage Vth of the memory cell transistor is Vth> VVF7, the judgment of the threshold voltage Vth in a state where the voltage VWL of the selected word line is set to VVF7 already causes the inversion of the latch circuit LQ1. Since the storage node / Q1 has been determined from the low level to the high level, no change occurs here.
When the write data is "000" and the threshold voltage Vth of the memory cell transistor is VVF7>Vth> VVF6, the transistor N30 is turned off because the storage node Q0 of the latch circuit LQ0 is at a low level, and the latch N1 is turned off. The storage node Q1 of the circuit LQ1 does not change.

When control signal φLAT1 is set to a high level, transistor N21 is turned on. At this time, transistors N20, N19 and transistor N15 are turned on, so that inverted storage node / Q2 of latch circuit LQ2 is at a low level. And the storage node Q2 is inverted from low level to high level. When the threshold voltage Vth of the memory cell transistor is Vth> VVF7, in the determination of the threshold voltage Vth when the voltage VWL of the selected word line is set to VVF7, the inversion of the latch circuit LQ2 has already been performed. Since the storage node / Q2 has been determined from the low level to the high level, no change occurs here.
When the write data is "000" and the threshold voltage Vth of the memory cell transistor is VVF7>Vth> VVF6, the transistor N30 is turned off because the storage node Q0 of the latch circuit LQ0 is at a low level, and the latch N1 is turned off. Since the storage node Q1 of the circuit LQ1 does not change, and thus the transistor N19 does not turn on, the storage node Q2 of the latch circuit LQ2 does not change.

As described above, the write data is "001".
If the threshold voltage Vth is higher than the word line voltage VVF6 (Vth> VVF6),
The latch data of the latch circuits LQ2, LQ1, and LQ0 is inverted to "111", and is in a write-inhibited state.

On the other hand, when the threshold voltage Vth of the memory cell is V
When the voltage is smaller than VF6 (Vth <VVF6), a cell current larger than the leak compensation current flows, the voltage of the node SA drops, the transistors HN1 and HN3 turn on, and the bit line BL
Between 0 volume CBL and node capacitance of SA CSA (<< CBL) occurs charge sharing, the voltage of the node SA is a bit line BL0 voltage (V _CC -Vth-Vth') and almost the same It becomes low level (for example, about 1 V). Therefore, the control signals φLAT5 and φLAT1 cause the transistor N3
1 and N21 are turned on, the transistors N15 and N16
Is at a low level (for example, 1 V), the drain-source of each of the transistors N15 and N16 is in a high resistance state, and the latch circuit LQ1
A current required to invert storage nodes Q1 and Q2 of LQ2 cannot flow, and as a result, the set state is maintained.

Thereafter, similarly, the voltage V of the selected word line is
When WL is set to VVF5 and the threshold voltage Vth corresponding to "010" is determined for the write data, the control signal φLAT, which is a pulse signal, is passed after a predetermined time.
8, .phi.LAT1 are sequentially set to the high level, and the threshold voltage Vth of the memory cell transistor whose write data is "010" is larger than VVF5 (Vth> VVF5).
Only in this case, control is performed so that the latch data of the latch circuits LQ2, LQ1, LQ0 is inverted to "111".

When the voltage VWL of the selected word line is set to VVF4 and the threshold voltage Vth corresponding to "011" is determined for the write data, the control signal φLAT1 which is a pulse signal after a lapse of a predetermined time. Is set to a high level, the write data is "011", and the latch circuits LQ2, LQ1, and LQ2 are provided only when the threshold voltage Vth is higher than VVF4 (Vth> VVF4).
Control is performed so that the latch data of LQ0 is inverted to “111”.

When the voltage VWL of the selected word line is set to VVF3 and the threshold voltage Vth corresponding to the write data of "100" is determined, the control signal .phi. , ΦLAT6 are sequentially set to a high level, and the write data is “100”.
Latch circuit L only when it is larger than VF3 (Vth> VVF3)
Control is performed so that the latch data of Q2, LQ1, and LQ0 is inverted to “111”.

When the voltage VWL of the selected word line is set to VVF2 and the threshold voltage Vth corresponding to "101" is determined for the write data, the control signal φLAT3, which is a pulse-like signal, after a lapse of a predetermined time. Is set to a high level, the write data is a memory cell transistor of "101", and the latch circuits LQ2, LQ1, LQ1, LQ1 and LQ2 are provided only when the threshold voltage Vth is higher than VVF2 (Vth> VVF2).
Control is performed so that the latch data of LQ0 is inverted to “111”.

When the voltage VWL of the selected word line is set to VVF1 and the threshold voltage Vth corresponding to "110" is determined for the write data, the control signal φLAT6, which is a pulse-like signal, after a lapse of a predetermined time. Is set to the high level, the write data is "110", and the latch circuits LQ2, LQ1, and LQ2 are provided only when the threshold voltage Vth is higher than VVF1 (Vth> VVF1).
Control is performed so that the latch data of LQ0 is inverted to “111”.

When the voltage VWL of the selected word line is VVF1
When the determination of the threshold voltage Vth in the state set to is completed, the wiped OR of the inverted signals of all the latch data is completed.
If there is at least one "0", the result of the wired OR goes to a low level, and the process proceeds to the rewriting process. If all of them are "1", the writing is completed. The above-described write and verify cycles are repeated until all memory cell transistors are determined to be sufficiently written, or until a predetermined number of times is reached.

Next, the normal read operation will be specifically described. FIG. 6 shows the states of signals at various parts during the normal read operation of the NAND flash memory according to the embodiment. Here, the memory string A
It is assumed that 0 is selected as a read target. It is also assumed that the write operation is performed on the memory cell transistor in accordance with the write data so that the distribution of the threshold voltage Vth and the write data have a correspondence relationship as shown in FIG. .

Before the normal read operation, the control signal PG
M is set to the GND level, the transistor N2 is turned off, and the bit lines BL0 and BL1 are disconnected from the bit line voltage generation circuit 2. The address decode signal AiB, AiN and control signal TRN is (V _CC -Vth)
Level, the control signal Vref is set to the Vcc level, the control signal DIS is set to the high level, the transistor N1 is turned on, and the bit lines BL0, BL
1 is set to the GND level.

When the normal read operation is started, the reset signal RST is set to a high level for a certain period prior to the operation, and all data held in the latch circuits LQ2 to LQ0 are reset to a low level. In the normal read operation, after the reset of the latch circuits LQ2 to LQ0 is completed, that is, after both the control signal DIS and the reset signal RST are switched to low level, the drain-side selection gate line DSG and the source-side selection gate line SSG are not selected. The voltage is set to a predetermined high level voltage equal to the word line voltage, for example, P5V (predetermined voltage of 5.0 to 6.0 V), and the voltage VWL of the selected word line is set to, for example, VRD7 → VRD6 →
VRD5 → VRD4 → VRD3 → VRD2 → VRD1 in this order while gradually lowering.

As a pre-process for determining the actual threshold voltage Vth at each word line voltage, the control signal Vref
Is set to the low level, the transistor P1 is turned on, and the bit line BL0 is charged with the power supply voltage Vcc. After a certain period of time, the voltage of the bit line BL0 increases, and when the potential difference between the gate and the source of the transistor HN1 becomes equal to or lower than Vth '(Vth' is the threshold voltage of the transistor HN1), the transistor HN is automatically turned on.
1, HN3 is turned off. Therefore, the bit line BL0 is charged to the (Vcc-Vth-Vth ') level (for example, about 1 V), and the node SA goes to the Vcc level.

In the above state, the threshold voltage Vth is determined by setting the voltage of the selected word line to a predetermined value and reflecting the presence or absence of the cell current on the voltage of the bit line BL0 and the node SA. That is, when a voltage equal to or higher than the threshold voltage Vth of a predetermined memory cell transistor is supplied to its gate and a cell current flows, the voltage of the bit line BL0 drops and the transistors HN1 and HN3 are turned on. Accordingly, the voltage of the node SA is lowered to approximately the voltage of the bit line BL0 (V _CC -Vth-Vth') and almost the same low level (e.g., about 1V). When a voltage lower than the threshold voltage Vth of a predetermined memory cell transistor is supplied to its gate, no cell current flows, the voltage of bit line BL0 does not drop, and the voltage of node SA becomes , Are held at the Vcc level. The threshold voltage Vth is determined based on this relationship.

When the charging of the bit line BL0 is completed, the control signal Vref is set to a predetermined level (for example, 2 V) at which the transistor P1 can supply a current sufficient to compensate for the leakage current of the bit line BL0. .

First, the threshold voltage Vth is determined in a state where the selected word line voltage VWL is set to VRD7.
Here, when the threshold voltage Vth of the memory cell transistor is higher than VRD7 (Vth> VRD7), the cell current does not flow, and the node SA is kept at the Vcc level. At this time, the transistors N15, N16 and N17 are turned on.

After a lapse of a predetermined time, the control signals φLAT0, φLAT2, φLAT6, which are pulse signals, are sequentially set to the high level.

When the control signal φLAT0 is set to the high level, the transistor N18 is turned on. At this time, since the transistor N15 is turned on, the latch circuit L18 is turned on.
The inverted storage node / Q2 of Q2 is set to low level, and storage node Q2 is inverted from low level to high level. At this time, the gates of the transistors N22 and N32 connected to the storage node Q2 of the latch circuit LQ2 go high.

When control signal φLAT2 is set to a high level, transistor N24 is turned on. At this time, transistors N23 and N22 and transistor N16 are turned on, so that inverted storage node / Q1 of latch circuit LQ1 is at a low level. And the storage node Q1 is inverted from low level to high level. At this time, the gate of the transistor N33 connected to the storage node Q1 of the latch circuit LQ1 goes high.

When control signal φLAT6 is set to the high level, transistor N34 is turned on. At this time, transistors N33, N32 and transistor N17 are turned on, so that inverted storage node / Q0 of latch circuit LQ0 is at the low level. And the storage node Q0 is inverted from the low level to the high level.

As described above, when the threshold voltage Vth of the memory cell transistor is higher than VRD7 (Vth> VRD7), the latch data of the latch circuits LQ2, LQ1, LQ0 is inverted to "111".

On the other hand, when the threshold voltage Vth of the memory cell transistor is smaller than VRD7 (Vth <VRD7), a cell current larger than the leakage compensation current flows, the voltage of node SA drops, and transistors HN1 and HN3 are turned on. ,
The capacitance CBL of the bit line BL0 and the capacitance CSA of the node SA (<
<Occur redistribution of charge between CBL), the voltage at the node SA is the voltage (V _CC -Vth-Vth') and almost the same low level of the bit line BL0 (for example, about 1V). Therefore, the control signals φLAT0, φLAT2, φLAT6
Therefore, even if the transistors N18, N24, and N34 are turned on, the gates of the transistors N15, N16, and N17 are at a low level (for example, 1 V). The latch circuits LQ2 to LQ
A current required to invert the storage nodes Q2 to Q0 of 0 cannot flow, and as a result, a low level state is maintained as it is reset.

When the determination of the threshold voltage Vth in a state where the voltage VWL of the selected word line is set to VRD7 is completed, the control signal Vref is set to the low level again, the transistor P1 is turned on, and the bit line BL0 Is charged with the power supply voltage Vcc. When the charging of the bit line BL0 is completed, the control signal Vref becomes a voltage of a predetermined level (for example,
2V).

Next, the threshold voltage Vth is determined in a state where the voltage VWL of the selected word line is set to VRD6. Here, the threshold voltage V of the memory cell transistor
When th is larger than VRD6 (Vth> VRD6), the node current is kept at Vcc level because no cell current flows. At this time, the transistors N15, N16, N1
7 turns on.

After a lapse of a predetermined time, the control signals φLAT0 and φLAT2, which are pulse signals, are sequentially set to the high level.

When the control signal φLAT0 is set to a high level, the transistor N18 is turned on. At this time, the transistor N15 is turned on.
The inverted storage node / Q2 of Q2 is set to low level, and storage node Q2 is inverted from low level to high level. At this time, the gate of the transistor N22 connected to the storage node Q2 of the latch circuit LQ2 goes high.

When control signal φLAT2 is set to a high level, transistor N24 is turned on. At this time, transistors N23, N22 and transistor N16 are turned on, so that inverted storage node / Q1 of latch circuit LQ1 is at a low level. And the storage node Q1 is inverted from low level to high level.

As described above, when the threshold voltage Vth of the memory cell transistor is higher than VRD6 (Vth> VRD6), the latch data of the latch circuits LQ2, LQ1, LQ0 is inverted to "110".

On the other hand, when the threshold voltage Vth of the memory cell transistor is smaller than VRD6 (Vth <VRD6), a cell current larger than the leakage compensation current flows, the voltage of node SA drops, and transistors HN1 and HN3 are turned on. ,
The capacitance CBL of the bit line BL0 and the capacitance CSA of the node SA (<
<Occur redistribution of charge between CBL), the voltage at the node SA is the voltage (V _CC -Vth-Vth') and almost the same low level of the bit line BL0 (e.g., 1V). Therefore, even if the transistors N18 and N24 are turned on by the control signals φLAT0 and φLAT2, the transistor N1
Since the gates of the transistors N5 and N16 are at a low level (for example, 1 V), the drain-source of each of the transistors N15 and N16 is in a high resistance state, and the storage nodes Q2 and Q1 of the latch circuits LQ2 and LQ1 are connected. The current necessary for the inversion cannot be supplied, and as a result, the low level state of the reset is maintained.

When the determination of the threshold voltage Vth in the state where the voltage VWL of the selected word line is set to VRD6 is completed, the control signal Vref is set to the low level again to turn on the transistor P1 and the bit line BL0 Is charged with the power supply voltage Vcc. When the charging of the bit line BL0 is completed, the control signal Vref becomes a voltage of a predetermined level (for example,
2V).

Next, the threshold voltage Vth is determined while the voltage VWL of the selected word line is set to VRD5. Here, the threshold voltage V of the memory cell transistor
When th is larger than VRD5 (Vth> VRD5), the node current is kept at Vcc level because no cell current flows. At this time, the transistors N15, N16, N1
7 turns on.

Here, the following cases can be considered for the latch data.

When Vth> VRD7: Latch data is "111" When VRD7>Vth> VRD6: Latch data is "11"
0 ”VRD6>Vth> VRD5: Latch data is“ 00 ”
0 "Here, only in the case of, it is necessary to cause the inversion of the nodes of the latch circuits LQ2 and LQ0 so that the read data becomes" 101 ". Need to be

That is, in this case, the control signals φLAT0 and φLAT7, which are pulse-like signals, are sequentially set to the high level after a predetermined time has elapsed.

When the control signal φLAT0 is set to the high level, the transistor N18 is turned on. At this time, since the transistor N15 is turned on, the latch circuit L
The inverted storage node / Q2 of Q2 is set to low level, and storage node Q2 is inverted from low level to high level. At this time, the gate of the transistor N32 connected to the storage node Q2 of the latch circuit LQ2 goes high. In the case of, there is no influence because the storage node Q2 of the latch circuit LQ2 is originally inverted to the high level.

When the control signal φLAT7 is set to the high level, the transistor N36 is turned on. In this case, the transistor N35 is turned on, and the transistors N32 and N17 are turned on. Thereby, the inverted storage node / Q1 of the latch circuit LQ0 is set to the low level, and the storage node Q0 is inverted from the low level to the high level. At this time, in the cases of and, the latch data does not change because the transistor N35 is off.

As described above, when the threshold voltage Vth of the memory cell transistor is higher than VRD5 (Vth> VRD5), the latch data of the latch circuits LQ2, LQ1, LQ0 is inverted to "101".

On the other hand, when the threshold voltage Vth of the memory cell transistor is smaller than VRD5 (Vth <VRD5), a cell current larger than the leak compensation current flows, the voltage of node SA drops, and transistors HN1 and HN3 are turned on. ,
The capacitance CBL of the bit line BL0 and the capacitance CSA of the node SA (<
<Occur redistribution of charge between CBL), the voltage at the node SA is the voltage (V _CC -Vth-Vth') and almost the same low level of the bit line BL0 (e.g., 1V). Therefore, even if the transistors N18 and N36 are turned on by the control signals φLAT0 and φLAT7, the transistor N1
Since the gates of the transistors N5 and N17 are at a low level (for example, 1 V), a high resistance state is set between the drains and the sources of the transistors N15 and N17. The current necessary for the inversion cannot be supplied, and as a result, the low level state of the reset is maintained.

Hereinafter, similarly, the voltage V of the selected word line is
When the threshold voltage Vth is determined with WL set to VRD4, the control signal φLAT0, which is a pulse-like signal, is set to a high level after a certain period of time, and the threshold voltage of the memory cell transistor is set. When the voltage Vth is VRD5> Vth
> VRD4 only when latch circuits LQ2, LQ1, LQ0
Is inverted to "100".

When the threshold voltage Vth is determined while the voltage VWL of the selected word line is set to VRD3,
After a lapse of a predetermined time, a control signal φLA which is a pulse signal
T4 and φLAT8 are sequentially set to the high level, and the threshold voltage Vth of the memory cell transistor becomes VRD4>Vth>
Only in the case of VRD3, control is performed so that the latch data of the latch circuits LQ2, LQ1, LQ0 is inverted to "011".

When the threshold voltage Vth is determined while the voltage VWL of the selected word line is set to VRD2,
After a lapse of a predetermined time, a control signal φLA which is a pulse signal
Only when T4 is set to the high level and the threshold voltage Vth of the memory cell transistor is VRD3>Vth> VRD2, the control is performed so that the latch data of the latch circuits LQ2, LQ1, LQ0 is inverted to "010".

When the threshold voltage Vth is determined in a state where the voltage VWL of the selected word line is set to VRD1,
After a lapse of a predetermined time, a control signal φLA which is a pulse signal
Only when T9 is set to the high level and the threshold voltage Vth of the memory cell transistor is VRD2>Vth> VRD1, the latch data of the latch circuits LQ2, LQ1, LQ0 is controlled to be inverted to "001".

The normal read operation is performed in this manner. When the normal read operation is completed, the latch circuits LQ2 to LQ2
An output corresponding to the threshold voltage Vth of the memory cell transistor is held in each of the storage nodes Q2 to Q0 of LQ0. That is, when the threshold voltage Vth is distribution 7, (Q2, Q1, Q0) = (1, 1, 1), and when the threshold voltage Vth is distribution 6, (Q2, Q1, Q0). =
(1, 1, 0), and when the threshold voltage Vth is distribution 5, (Q2, Q1, Q0) = (1, 0, 1), and
If the threshold voltage Vth is distribution 4, (Q2, Q1, Q
0) = (1, 0, 0), and when the threshold voltage Vth is distribution 3, (Q2, Q1, Q0) = (0, 1, 1), and the threshold voltage Vth is In the case (Q2, Q
1, Q0) = (0,1,0), and the threshold voltage Vth
Is distribution 1, (Q2, Q1, Q0) = (0, 0,
1), and when the threshold voltage Vth is distribution 0, (Q
2, Q1, Q0) = (0, 0, 0). Then, these inverted outputs are extracted as read data.

According to the one embodiment configured as described above, at the time of writing, an ideal voltage corresponding to write data can be applied to the channel of the memory cell transistor to be written. Therefore, the writing can be started by setting the writing voltage VPGM applied to the selected word line to an ideal initial voltage, and the writing of all data having different writing levels can be completed almost simultaneously. .

Here, the maximum number of write operations N until all write data is written is determined to be sufficient.
p is defined by the following equation.

Np = 1 + (ΔVth0 + δVpp + δVch +
δVBL) / ΔVpp where ΔVth0: difference in threshold voltage between the memory cell with the fastest write speed and the slowest memory cell after the first write δVpp: variation in write voltage VPGM during write (in the booster circuit) Variation) δVch: Variation of set voltage of bit line voltage δVBL: Maximum value of difference between originally desired bit line voltage and actually applied bit line voltage ΔVpp: Write voltage VPGM using ISPP
Is the step width of. In this equation, the conditions before the present invention is applied, that is, ΔVth0 = 2.0 V, δVpp = 0.5
V, δVch = 0.1V, δVBL = 3.6-1.5 = 2.
By substituting 1V and δVpp = 0.15V and calculating the maximum number of times of writing Np using ISPP, Np = 1 + ｛2.0 + 0.5 + 0.1 + (3.6-1.
5)｝ /0.15=33 On the other hand, in the case of the NAND flash memory according to the embodiment to which the present invention is applied, δVBL
= 0.6 V (because one bit line voltage is set for two data), and the maximum number of write operations Np
Np = 1 + (2.0 + 0.5 + 0.1 + 0.6) / 0.
15 = 23. As described above, according to this embodiment, the number of times of writing is greatly reduced, and thus the writing time can be shortened.

In this embodiment, the process of boosting the channel voltage of the memory cell transistor to be written by capacitive coupling with the word line is performed by applying the channel voltage from the bit line to the channel. (Bus voltage of the select transistor on the drain side of the memory string) must be set to a voltage equal to or higher than the upper limit, that is, when the write data is “110” and “10x” (x: 0 or 1). Since only the step is performed, the step of boosting the word line voltage VWL is suppressed to the minimum necessary. For this reason, the write time per write increases compared to the case where the word line voltage VWL is boosted in one stage, but the increase is slight. Therefore, in terms of the total writing time, the effect of time reduction due to the reduction in the number of writings by applying the present invention is greater.

Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above embodiments, and various modifications based on the technical concept of the present invention are possible. For example, the configurations of the memory cell array 1, the bit line voltage generation circuit 2, the read / verify control circuit 3, and the like in the above-described embodiment are merely examples, and may have circuit configurations different from those illustrated.

Further, in the above-described embodiment, the case where the present invention is applied to a NAND flash memory that stores data having three bits and taking eight values for one memory cell transistor has been described. The present invention can also be applied to a NAND flash memory that stores two-bit quaternary data for one memory cell transistor.

[0180]

As described above, according to the present invention, the voltage of the channel of the memory cell to be written is raised by the capacitive coupling with the word line by separating the channel of the memory cell from the selected bit line. Supplying a voltage equal to or higher than the upper limit of the pass voltage of the selection transistor between the memory cell array and the bit line (a voltage that can be applied from the bit line to the channel of the memory cell) to the channel of the target memory cell. It is possible. Therefore, during a write operation, the word line voltage is stepped up in a plurality of steps, and at this time, the voltage of the selected bit line is changed at a predetermined timing in accordance with the step of boosting the word line voltage. The write level is sequentially switched to a voltage for cutting off the selection transistor between the memory string and the bit line from the shallower write level, and the channel of the memory cell to be written is sequentially changed from the shallower write level of the write data. Applying the ideal voltage corresponding to the write data to the channel of the write target memory cell while adopting self-boost or local self-boost by separating from the selected bit line and boosting by capacitive coupling with the word line Can shorten the writing time. That.

[Brief description of the drawings]

FIG. 1 is an 8-level NAND according to an embodiment of the present invention;
FIG. 2 is a circuit diagram showing a configuration of a main part of a flash memory.

FIG. 2 is an 8-level NAND according to an embodiment of the present invention;
FIG. 2 is an equivalent circuit diagram of a memory cell array of a flash memory.

FIG. 3 is an 8-level NAND according to an embodiment of the present invention;
3 is a timing chart for explaining a write operation of the flash memory of the present invention.

FIG. 4 is an equivalent circuit diagram for explaining the principle of self-boost.

FIG. 5 shows an 8-level NAND according to an embodiment of the present invention;
FIG. 5 is a timing chart for explaining a verify operation of the flash memory.

FIG. 6 shows an 8-level NAND according to an embodiment of the present invention;
4 is a timing chart for explaining a normal read operation of the flash memory of the present invention.

FIG. 7 shows a correspondence relationship between data contents and a threshold voltage when storing three-bit data having eight values in one memory cell transistor, an ideal bit line voltage during writing, and an actual bit line. FIG. 4 is a schematic diagram for explaining an example of voltage application.

FIG. 8 is an equivalent circuit diagram for explaining a write operation using self-boost.

FIG. 9 shows an 8-level NAND before the present invention is applied.
FIG. 2 is a circuit diagram showing a configuration of a main part of a flash memory.

FIG. 10 shows an 8-level NAN before the present invention is applied.
5 is a timing chart for explaining a write operation of a D-type flash memory.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Memory cell array, 2 ... Bit line voltage generation circuit, 3 ... Read / verify control circuit, A0,
A1 ... memory string, WL0 to WL15 ...
Word lines, BL0, BL1,... Bit lines, LQ0 to LQ
Q2: latch circuit, VBL1 to VBL3: bit line voltage supply line

Claims (11)

[Claims] An amount of charge stored in a charge storage unit changes according to a voltage applied to a word line and a bit line, and a threshold voltage changes according to the change. A plurality of memory cells for storing value data are connected,
A memory string connected to a bit line and a source line via a selection transistor whose one end and the other end are controlled in accordance with a gate voltage is arranged in parallel, and a control gate of a memory cell in the same row is arranged. Are connected to a common word line, and n-bit (n ≧ 2) multi-valued data is written in parallel and in page units to the memory cell. At this time, the channel of the write-protected memory cell is separated from the bit line and the word line is A non-volatile semiconductor memory device that is boosted to a non-write potential by capacitive coupling with a selected bit line connected to a memory cell to be written to a bit line voltage according to write data during a write operation After that, the word line voltage is stepwise boosted in a plurality of steps. Then, at a predetermined timing, the voltage of the selected bit line is sequentially switched to a voltage that cuts off the selection transistor between the memory string and the bit line, starting from a shallow write data level. The channel of the memory cell to be written is changed from a channel having a low write data write level to
A nonvolatile semiconductor memory device comprising: a write control unit configured to sequentially increase the voltage by capacitive coupling with a word line by separating from a selected bit line. 2. The write control means comprises: n latch circuits for latching n-bit write data; and a plurality of bits for supplying a predetermined bit line voltage corresponding to the write data to the selected bit line. A line voltage supply source, and a switching circuit for switching a connection state between the selected bit line and the plurality of bit line voltage supply sources based on data latched in the latch circuit, wherein a voltage of the selected bit line is Switching the voltage to a voltage that cuts off the selection transistor between the memory string and the bit line by switching the voltage of a bit line voltage supply connected to the selected bit line. 2. The nonvolatile semiconductor memory device according to claim 1, wherein: 3. The write control unit according to claim 3, wherein the write control unit sequentially boosts the channel of the memory cell to be written by capacitive coupling with a word line, starting from a channel having a low write data write level. 2. The non-volatile semiconductor memory device according to claim 1, wherein the operation is performed only for a cell whose channel voltage needs to be set to be equal to or higher than an upper limit of a voltage that can be applied from the bit line to the channel. 4. The step of boosting the channel of the write-protected memory cell to a non-write potential by capacitive coupling with a word line in the first step of the step of boosting the word line voltage. Then, in the second and subsequent steps of the step of boosting the word line voltage, the channels of the memory cells to be written are sequentially boosted by the capacitive coupling with the word lines, starting from the one having the shallower write level of the write data. 2. The nonvolatile semiconductor memory device according to claim 1, wherein processing is started. 5. The write control unit according to claim 1, wherein the step of setting the selected bit line to a bit line voltage corresponding to write data is performed after all bit lines are precharged to a predetermined voltage. 2. The nonvolatile semiconductor memory device according to 1. 6. The word line voltage is stepwise raised in a plurality of steps, so that a selected word line is finally set to a predetermined write voltage and an unselected word line is lower than the write voltage. 2. The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device is set to a write pass voltage. 7. In the writing operation, a gate voltage of the selection transistor between the memory string and the bit line is set to a V _cc level (V _cc is a power supply voltage). Increase the bit line voltage from the one with the low write data write level.
Sequentially, in performing the process of switching the voltage to cut off the select transistor between said memory string and the bit lines, according to claim 1, wherein the switching the voltage of the selected bit line to V _CC level Nonvolatile semiconductor memory device. 8. The nonvolatile semiconductor memory device according to claim 1, wherein said memory cell is composed of three bits and stores data having eight values. 9. A during the write operation, the gate voltage V _CC level of the select transistor between said memory string and the bit line (V _CC is the supply voltage) is set to said write control means, the selection When setting the bit line to a bit line voltage corresponding to the write data, the bit line voltage is 0 V when the write data is “00x” (x: 0 or 1), and the write data is “01x” (x:
The bit line voltage in the case of 0 or 1 is set to the voltage VB1 (0 <
VB1 <V _CC ) and the write data is “10x” (x: 0)
Or 1) is changed to the voltage VB2 (0 <V
B2 <V _CC), sets the bit line voltage when the write data voltage of the bit line voltage in the case of "110" _{VB3 (0 <VB3 <V CC} ), the write data is "111" to the V _CC level, In addition, when performing a process of sequentially switching the voltage of the selected bit line to a voltage for cutting off the selection transistor between the memory string and the bit line from a low write data write level, the nonvolatile semiconductor memory device according to claim 8, wherein the switching the voltage of the selected bit line to V _CC level. 10. The word line voltage is boosted step by step in three steps, wherein all word lines are boosted to a first write pass voltage in a first step, and in a second step. All word lines are boosted to a second write pass voltage higher than the first write pass voltage, and finally the selected word line is set to a write voltage higher than the second write pass voltage in the third step. And the third word line voltage is set to a third write pass voltage higher than the second write pass voltage and lower than the second write pass voltage. In the first step, the process of boosting the channel of the write-protected memory cell to the non-write potential by capacitive coupling with the word line is started, and In the second step of the boosting step, the voltage of the selected bit line set to the voltage VB3 is switched to the V _CC level, and the write data is set to “1”.
The process of boosting the channel of the "10" memory cell by capacitive coupling with the word line is started, and the voltage of the selected bit line set to the voltage VB2 is set in the third step of the word line voltage boosting step. 10 is switched to the V _CC level to start a process of boosting the channel of the memory cell whose write data is “10x” (x: 0 or 1) by capacitive coupling with a word line. Non-volatile semiconductor storage device. 11. A charge amount stored in a charge storage portion changes according to a voltage applied to a word line and a bit line, a threshold voltage changes according to the change, and a threshold voltage changes. A plurality of memory cells for storing value data are connected, and one end and the other end are connected in parallel to a memory string connected to a bit line and a source line via a selection transistor whose conduction state is controlled according to a gate voltage. And the control gates of the memory cells in the same row are connected to a common word line, and n-bit (n ≧ 2) multi-valued data is written in parallel and in page units to the memory cells,
At this time, a data writing method of the nonvolatile semiconductor memory device, in which a channel of a write-protected memory cell is separated from a bit line and boosted to a non-write potential by capacitive coupling with a word line, Setting the selected bit line connected to the bit line voltage according to the write data; and stepwise increasing the word line voltage in a plurality of steps. At this time, the step corresponds to the step of boosting the word line voltage. ,
At a predetermined timing, the voltage of the selected bit line is sequentially switched to a voltage that cuts off the selection transistor between the memory string and the bit line, starting from a write data having a low write level, and A step of sequentially separating the selected memory cell from the selected bit line and boosting the channel of the target memory cell by capacitive coupling with the word line, starting with the shallower write level of the write data. Data writing method.