JP4667719B2 - Nonvolatile multilevel semiconductor memory - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile multilevel semiconductor memory that stores data of a plurality of bits in one memory cell and a method for operating the nonvolatile multilevel semiconductor memory.
[0002]
[Prior art]
A nonvolatile semiconductor memory such as a flash memory stores data by injecting electrons into a charge storage layer of a memory cell and changing a threshold voltage of the memory cell. The threshold voltage of the memory cell is high when electrons are present in the charge storage layer, and is low when electrons are not present in the charge storage layer. When a memory cell of a flash memory stores binary data, generally, a threshold voltage is high, and no current flows through the memory cell during a read operation is a state where “data 0” is written (“0 state”). A state in which the threshold voltage is low and a current flows through the memory cell during a read operation is a state in which “data 1” is written (“1 state” = erased state).
[0003]
The “0 state” and “1 state” are detected by comparing the current (memory cell current) flowing in the memory cell during the read operation with the reference current.
This type of nonvolatile semiconductor memory has a higher storage capacity (storage density) year by year. As a technique for increasing the storage density, a non-volatile multi-value semiconductor memory that stores multi-value data by controlling the threshold voltage of the memory cell in three or more ways has been developed (for example, see Patent Document 1). In addition, a nonvolatile memory cell that stores multivalued data by locally injecting electrons into the insulating film of the memory cell has been developed (see, for example, Patent Document 2).
[0004]
[Patent Document 1]
Japanese Patent Laid-Open No. 10-92186 (pages 7 to 8, FIGS. 2 and 3)
[Patent Document 2]
JP 2001-57093 A (3-4 pages, FIG. 3)
[0005]
[Problems to be solved by the invention]
In the conventional nonvolatile multilevel semiconductor memory, the threshold voltage of the memory cell is sequentially changed for each logical value of the write data, and the multilevel data is written into a plurality of memory cells. In a single write operation, only the same charge amount can be injected into a plurality of memory cells. For this reason, as the number of bits of data stored in one memory cell increases, the number of times of writing increases and the writing time becomes longer.
In general, in a nonvolatile semiconductor memory, a verify operation for checking that data is correctly written in a memory cell is necessary after the write operation. Conventionally, the verify operation is performed for each logical value. For this reason, as in the write operation, as the number of bits of data stored in one memory cell increases, the number of verifications increases and the verification time becomes longer.
[0006]
An object of the present invention is to shorten the time for writing multi-value data to a memory cell in a nonvolatile multi-value semiconductor memory.
Another object of the present invention is to shorten the verify time of multi-value data written in a memory cell in a non-volatile multi-value semiconductor memory.
[0007]
[Means for Solving the Problems]
3. The nonvolatile multilevel semiconductor memory according to claim 1 or 2, wherein a plurality of NOR type nonvolatile memory cells having a charge accumulation layer for accumulating charges in two regions in the same memory cell have a virtual ground type memory cell array configuration. Are connected in series via an input / output node. The voltage generation circuit generates a plurality of source voltages and drain voltages having different voltage values for each logical value written in a NOR type nonvolatile memory cell supplied to each of the plurality of source lines and drain lines. The plurality of switches are provided outside the memory cell array, and are arranged for each bit line between the bit line and each source line and between the bit line and the drain line. The switch control circuit generates a switch control signal for turning on the switch during a write operation for writing data to the memory cell and a verification operation for checking the logic level of the data written to the memory cell. The bit line is connected to one of a plurality of source lines and drain lines by a switch control signal.
[0008]
In a write operation or a verify operation, a plurality of source lines can be connected to an arbitrary bit line, so that a plurality of different source voltages can be supplied to input / output nodes of a plurality of memory cells via the bit lines. Therefore, a plurality of logical values can be written to a plurality of memory cells, respectively, by a single write operation. In addition, a plurality of memory cells in which different logical values are written can be verified by one verification operation. As a result, the execution time of the write operation and the verify operation can be shortened in the nonvolatile multilevel semiconductor memory that stores a plurality of bits in one memory cell. That is, the writing time (busy time) for writing data into the memory cell can be shortened.
[0009]
[0010]
According to another aspect of the nonvolatile multilevel semiconductor memory of the present invention, the switch control circuit outputs a switch control signal according to a plurality of bits of write data supplied via an external terminal and an address indicating a memory cell to which the write data is written. . For this reason, the logical value indicated by the write data can be reliably written into the memory cell selected according to the address. Further, the data written in the memory cell can be reliably verified.
[0011]
[0012]
[0013]
[0014]
[0015]
[0016]
According to another aspect of the nonvolatile multilevel semiconductor memory of the present invention, the word voltage generation circuit supplies a write word voltage to the word line during writing of data to the memory cell and also verifies data written to the memory cell. The verification word voltage is supplied to the word line. By forming a plurality of source lines, a plurality of logical values can be written in a plurality of memory cells connected to the word line by one write operation. In addition, a plurality of memory cells connected to the word line and written with different logic values can be verified by one verification operation.
[0017]
According to another aspect of the nonvolatile multilevel semiconductor memory of the present invention, the charge storage layer of each memory cell is formed as a trap insulating film that locally traps carriers according to the logical value of data. For example, data of a larger number of bits can be stored in one memory cell by trapping carriers in a plurality of locations of the trap insulating film. Even when data of a large number of bits is stored, the write operation time and the verification operation time can be shortened compared to the conventional case.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the figure, the signal lines indicated by bold lines are composed of a plurality of lines. Double circles in the figure indicate external terminals.
FIG. 1 shows a first embodiment of a nonvolatile multilevel semiconductor memory of the present invention. This embodiment corresponds to claims 1 to 3, claim 4 and claim 5.
This nonvolatile multilevel semiconductor memory is formed as a flash memory on a silicon substrate using a CMOS process.
[0019]
The flash memory includes an internal voltage generation circuit 10, a high voltage generation circuit 12, a state control circuit 14, a command register 16, an address register 18, a status register 20, a row address decoder 24, a column address decoder 26, a page buffer 28, and a memory cell array 30. , And an I / O buffer 32.
The internal voltage generation circuit 10 generates a plurality of types of internal voltages in response to a control signal from the state control circuit 14 and supplies the generated voltages to the row address decoder 24 and the column address decoder 26. The high voltage generation circuit 12 generates a high voltage such as a word line voltage in accordance with a control signal from the state control circuit 14 and supplies the generated voltage to the row decoder 24 and the memory cell array 30.
[0020]
The state control circuit 14 has a command signal CMD1 (address latch enable signal, command latch enable signal, spare area enable signal, write protect signal, etc.) and command signal CMD2 (chip enable signal, read enable signal) supplied via an external terminal. , And a control signal from the command register 16, and generates a plurality of control signals for executing a read operation, a write operation (program operation), and an erase operation. The state control circuit 14 outputs a ready / busy signal R / B according to the state of the chip.
[0021]
The command register 16 receives a command signal supplied to the input / output terminal I / O via the I / O buffer 32 and outputs the received signal to the state control circuit 14. The address register 18 receives an address signal supplied to the input / output terminal I / O via the I / O buffer 32 and outputs the received signal to the row address decoder 24 and the column address decoder 26. The I / O buffer 32 receives a command signal, an address signal, and a data signal via the input / output terminal I / O. The data signal is input / output to / from the sense amplifier / buffer 28.
[0022]
The row address decoder 24 selects one of the word lines WL according to an address signal (upper bit) from the address register 18. The row address decoder 24 supplies a program voltage, a verification voltage, a read voltage, or an erase voltage to the selected word line WL. The column address decoder 26 selects a predetermined bit line BL in accordance with an address signal (lower bit) from the address register 18. Specifically, the bit lines BL on both sides of the memory cell MC to be accessed are selected according to the address signal. The selected bit line BL is set to a predetermined voltage by a column address decoder 26 described later.
[0023]
The sense amplifier / buffer 28 has a plurality of sense amplifiers and a buffer for temporarily holding data. During the write operation, the sense amplifier / buffer 28 holds write data sequentially supplied from the input / output terminal I / O via the I / O buffer 32 in the buffer, and sets the bit line BL to a predetermined level according to the held data. Set to voltage. Further, the sense amplifier / buffer 28 compares the memory cell current from the memory cell MC transmitted via the bit line BL with the reference current during the read operation, and sets the logic level of the data held in the memory cell MC. To detect. That is, read data from the memory cell array 30 is amplified by the sense amplifier. The amplified data is stored in a buffer and output to the input / output terminal I / O via the I / O buffer 32.
[0024]
The memory cell array 30 has a plurality of memory cells MC arranged in a matrix, a plurality of word lines WL wired in the horizontal direction in the figure, and a plurality of bit lines wired in the vertical direction in the figure. Yes. The memory cells MC arranged in the horizontal direction in the figure are connected in series via an input / output node ND. The control gates of the memory cells MC arranged in the horizontal direction in the figure are connected to the same word line WL. The input / output nodes ND of the memory cells MC arranged in the vertical direction in the figure are connected to each other via a bit line BL. Each bit line BL is shared by adjacent memory cells MC on the left and right sides of the figure. This type of memory cell array is generally called a virtual ground type.
[0025]
Each memory cell MC is composed of a transistor (cell transistor) having a trap gate TG that accumulates carriers (electrons). Carriers trapped in the trap gate TG do not move in the trap gate TG. By utilizing this, the threshold voltage of the cell transistor can be changed locally.
In the present embodiment, each memory cell MC has write data in a trap region (white square in the figure) formed on both input / output nodes ND side (source side and drain side of the channel region of the cell transistor) in the trap gate TG. Can be held. That is, the memory cell MC has a double bit structure. Each trap region can hold 2-bit write data according to the amount of electrons trapped. Therefore, one memory cell MC can store 4-bit data (16 values).
[0026]
FIG. 2 shows essential parts of the memory cell array 30 and the column address decoder 26 shown in FIG.
The memory cell array 30 is composed of a plurality of memory blocks identified by upper bits of the address signal, and each memory block has eight memory areas MA0 corresponding to 8-bit data terminals I / O0-I / O7. -7. In each memory block, the word line WL is wired in common to the eight memory areas MA0-7.
[0027]
The column address decoder 26 has a plurality of source line areas SLA0 to SLA7 (corresponding to data terminals I / O0 to I / O7) corresponding to the memory areas MA0-7. Each source line region SLA0-SLA7 includes first and second switch control circuits 34, 36, a voltage control circuit 38, a plurality of first switches SW1, a plurality of second switches SW2, and a first switch control line SC1 (SC11, SC12). , SC13, SC14,...), A second switch control line SC2 (SC21, SC22, SC23, SC24,...), Source lines SL1-SL3, and drain lines DL.
[0028]
The first switch control circuit 34 applies a first high-level signal to a predetermined first switch control line SC1 in accordance with an address signal (lower bits) and a logical value of write data during a write operation and a verification operation after the write operation. Outputs a switch control signal. In response to the output of the first switch control signal, one of the switches SW1 is turned on every other bit line BL.
[0029]
The second switch control circuit 36 applies a second high-level signal to the predetermined second switch control line SC2 in accordance with the address signal (lower bit) and the logical value of the write data during the write operation and the verify operation after the write operation. Outputs a switch control signal. In response to the output of the second switch control signal, one of the switches SW2 is turned on every other bit line BL.
[0030]
The voltage control circuit 38 outputs three write voltages corresponding to the three kinds of logic values of the write data to the source lines SL1 to SL3 in the write cycle for writing data to the memory cell MC, and the first drain voltage to the drain line. Output to DL (write operation). Next, the voltage control circuit 38 outputs three verification voltages corresponding to the three kinds of logical values of the write data to the source lines SL1 to SL3, and outputs the second drain voltage to the drain line DL (verification operation). ).
[0031]
The write voltage, the verification voltage, and the first and second drain voltages are generated by the internal voltage generation circuit 10 shown in FIG.
FIG. 3 shows voltages generated by the internal voltage generation circuit 10 and the high voltage generation circuit 12 shown in FIG.
In the write operation (program operation), the internal voltage generation circuit 10 includes write voltages VS1, VS2, and VS3 (for example, 0.15V, 0.10V, and 0.05V, respectively) corresponding to the logic L1, L2, and L3 of the write data, The first drain voltage VDP (for example, 6.0 V) is output. The logics L1, L2, and L3 correspond to binary numbers “10”, “01”, and “00”, respectively. The high voltage generation circuit 12 outputs a gate voltage VGP (for example, 9.8 V). The gate voltage VGP is supplied to the word line WL selected by the row address decoder 24 according to the address signal (upper bit). A ground voltage is supplied to the unselected word lines WL.
[0032]
In the verification operation after the write operation, the internal voltage generation circuit 10 includes verification voltages VV1, VV2, and VV3 (for example, 0.15V, 0.10V, and 0.05V, respectively) corresponding to the write data logic L1, L2, and L3, respectively. The first drain voltage VDR (for example, 4.0V) is output. The high voltage generation circuit 12 outputs a gate voltage VRD (for example, 4.0 V). The gate voltage VRD is supplied to the selected word line WL during the write operation. A ground voltage is supplied to the unselected word lines WL.
[0033]
FIG. 4 shows the relationship between the logical value of the write data and the threshold voltage of the memory cell MC in the first embodiment. FIG. 4 shows one trap region (white square in FIG. 1) of the memory cell MC. As described above, one memory cell MC can store 16 values by two trap regions. In the following description, threshold voltage distribution regions corresponding to write data logic L0-L3 are referred to as regions L0-L3, respectively.
[0034]
The threshold voltage of each trap region of the memory cell MC is distributed in one of the regions L0 to L3 according to the logical value of data to be written. Regions L0 to L3 correspond to 2-bit data “11”, “10”, “01”, and “00”, respectively. The region L0 has a negative threshold voltage and is a distribution of erased memory cells MC (trap regions). In this region, the cell transistor operates as a depletion transistor. The memory cells in the region L1-L3 have a positive threshold voltage, and the cell transistor operates as an enhancement transistor.
[0035]
Memory cell MC stores logic L0 ("11") in the erased state. For this reason, three types of write voltages VS1-VS3 and three types of verification voltages VV1-VV3 are required to write the remaining three types of logic L1-L3 into the memory cell MC. In this embodiment, since the source lines SL1 to SL3 that supply the three kinds of write voltages VS1 to VS3 are independently formed, all the logic can be written to the memory cell MC in one write operation. . Further, since the source lines SL1 to SL3 that supply the three kinds of verification voltages VV1 to VV3 are independently formed, all the logics written in the memory cells MC can be verified by one verification operation.
[0036]
Data writing (programming) is performed for each trap region until the threshold voltage exceeds VT (VT1, VT2, VT3). For example, when logic “10” is written in the trap region, the write operation and the verify operation are repeated until the threshold voltage of the cell transistor exceeds VT1. Then, the threshold voltage of each trap region is set to one of the regions L0 to L3.
[0037]
Data is read by comparing the threshold voltage of the cell transistor with the reference voltage VR (VR1, VR2, VR3). When the threshold voltage of the cell transistor is lower than the reference voltage VR1, the data held in the trap region is determined as “11”. When the threshold voltage of the cell transistor is between the reference voltages VR1 and VR2, the data held in the trap region is determined as “10”. When the threshold voltage of the cell transistor is between the reference voltages VR2 and VR3, the data held in the trap region is determined to be “01”. When the threshold voltage of the cell transistor is higher than the reference voltage VR3, the data held in the trap region is determined as “00”.
[0038]
FIG. 5 shows a write operation in the first embodiment.
In the write operation, data is written to one memory cell MC selected by the word line WL and the bit line BL for each memory area MA0-7. In this example, logic L1 ("10") is written to the memory cell MC (one of the memory cells MC connected to the word line WL2) in the memory area MA corresponding to the data terminal I / O0, and the data terminal I / O Logic L2 (“01”) is written into the memory cell MC in the memory area MA corresponding to O1, and logic L3 (“00”) is written into the memory cell MC in the memory area MA corresponding to the data terminal I / O7. A gate voltage VGP (9.8 V) is supplied to the word line WL2, and a ground voltage is supplied to the other word lines WL.
[0039]
The voltage generation circuit 38 in the source line region SLA0 corresponding to the data terminal I / O0 outputs the write voltages VS1, VS2, and VS3 (0.15V, 0.10V, and 0.05V, respectively) to the source lines SL1 to SL3, respectively. 1 Drain voltage VDP (6.0 V) is output to the drain line DL.
The first and second switch control circuits 34 and 36 turn on the switches SW1 and SW2 indicated by circles in the drawing in accordance with the address signal and the write data, so that the first and second switch control lines SC1 and SC2 are turned on. A switch control signal (high level) is output to.
[0040]
The bit lines BL2 and BL3 connected to the memory cell MC to which the logic L1 is written change from the precharge voltage (floating) to the write voltage VS1 and the first drain voltage VDP, respectively. The other bit lines BL change to the write voltage VS1 or the first drain voltage VDP, respectively. For this reason, the memory cell MC to which no data is written has a source-drain voltage of 0 V, and erroneous writing is prevented.
[0041]
The voltage generation circuit 38 of the source line regions SLA1 and SLA7 corresponding to the data terminals I / O1 and I / O7 applies the write voltages VS1, VS2, and VS3 (0.15V, 0.10V, and 0.05V, respectively) to the source line SL1- Each is output to SL3, and the first drain voltage VDP (6.0 V) is output to the drain line DL. By the operation of the first and second switch control circuits 34 and 36 in the source line region SLA1, the pair of bit lines BL connected to the memory cell MC to which the logic L2 is written are changed from the precharge voltage (floating) to the write voltage VS2 and The first drain voltage VDP changes. The other bit lines BL change to the write voltage VS2 or the first drain voltage VDP, respectively. Similarly, by the operation of the first and second switch control circuits 34 and 36 in the source line region SLA7, the pair of bit lines BL connected to the memory cell MC to which the logic L3 is written are supplied from the precharge voltage (floating) to the source. It changes to voltage VS3 and drain voltage VDP, respectively. The other bit lines BL change to the write voltage VS3 or the first drain voltage VDP, respectively.
[0042]
Then, electrons corresponding to the logical value of the write data are trapped in one of the trap regions of the memory cell MC (the trap region on the left side of the drawing indicated by the black square). That is, a write operation is executed. Note that when the logic L1 is written to the other of the trap regions, the first drain voltage VDP is supplied to the bit line BL3, and the source voltage VS1 is supplied to the bit line BL2.
[0043]
As described above, in the present embodiment, the first and second switch control circuits 34 and 36 selectively connect the bit lines BL to the source lines SL1-3 and the drain lines DL, thereby writing data having different logical values. Data can be simultaneously written in a plurality of memory cells MC by one write operation.
FIG. 6 shows the verification operation after the write operation in the first embodiment. The verification operation is an operation for confirming that data is correctly written in the memory cell MC (the trap region on the left side of the figure).
[0044]
First, the gate voltage VGP (9.8 V) is supplied to the word line WL2, and the ground voltage is supplied to the other word lines WL.
The voltage generation circuit 38 in the source line region SLA0 corresponding to the data terminal I / O0 outputs the verification voltages VV1, VV2, and VV3 (0.15V, 0.10V, and 0.05V, respectively) to the source lines SL1 to SL3, The second drain voltage VDR (4.0 V) is output to the drain line DL.
[0045]
The first and second switch control circuits 34 and 36 turn on the switches SW1 and SW2 indicated by circles in the drawing in accordance with the address signal and the write data, so that the first and second switch control lines SC1 and SC2 are turned on. A switch control signal (high level) is output to.
The bit lines BL2 and BL3 connected to the memory cell MC in which the logic L1 is written by the write operation change from the precharge voltage (floating) to the verification voltage VV1 and the second drain voltage VDR, respectively. The other bit lines BL change to the source voltage VV1 or the second drain voltage VDR, respectively. For this reason, the memory cell MC to which no data is written has a source-drain voltage of 0 V, and erroneous writing is prevented.
[0046]
The voltage generation circuit 38 of the source line regions SLA1 and SLA7 corresponding to the data terminals I / O1 and I / O7 receives the verification voltages VV1, VV2, and VV3 (0.15V, 0.10V, and 0.05V, respectively) and the source line SL1- Each is output to SL3 and the second drain voltage VDR (4.0V) is output to the drain line DL. By the operation of the first and second switch control circuits 34 and 36 in the source line region SLA1, the pair of bit lines BL connected to the memory cell MC to which the logic L2 is written are changed from the precharge voltage (floating) to the verification voltage VV2. It changes to the second drain voltage VDR. The other bit lines BL change to the verification voltage VV2 or the second drain voltage VDR, respectively. Similarly, by the operation of the first and second switch control circuits 34 and 36 in the source line region SLA7, the pair of bit lines BL connected to the memory cell MC to which the logic L3 is written are supplied from the precharge voltage (floating) to the source. The voltage changes to the voltage VV3 and the second drain voltage VDR, respectively. The other bit lines BL change to the source voltage VV3 or the second drain voltage VDR, respectively.
[0047]
Then, the logical value of the data written in the memory cell MC is determined by detecting the memory cell current flowing between the source and drain of the memory cell MC with a sense amplifier. When verifying the logic L1 written to the other side of the trap region, the second drain voltage VDR is supplied to the bit line BL2, and the verification voltage VV1 is supplied to the bit line BL3.
[0048]
As described above, in the present embodiment, the first and second switch control circuits 34 and 36 are written in the memory cell MC by selectively connecting the bit line BL to the source line SL1-3 and the drain line DL. The write data having different logical values can be verified by one verification operation.
FIG. 7 shows the memory cell current in the verification operation of the first embodiment.
[0049]
In the present embodiment, in the verification operation, the source voltage is changed according to the logical value of the data written in the memory cell MC, and the selected word line voltage VG is constant (VRD). For this reason, as shown in FIG. 7, the current characteristics of the memory cell MC (cell transistor) in which data is written are the same regardless of the logical value of the written data. As a result, the verification operation of a plurality of memory cells MC connected to one word line WL can be performed simultaneously.
[0050]
FIG. 8 shows the memory cell current in the verification operation before the present invention.
Prior to the present invention, the verification operation is performed by changing the gate voltage VG while keeping the source voltage constant according to the logical value of the data written in the memory cell MC. Therefore, as shown in FIG. 8, the current characteristics of the plurality of memory cells MC connected to one word line WL differ depending on the logical value of the written data. Therefore, the verification operation can only be performed for each logical value.
[0051]
FIG. 9 shows a write operation and a verify operation in the first embodiment. This flow is automatically performed in the flash memory.
First, in step S10, as described with reference to FIG. 5, the flash memory simultaneously programs one of the logics L1, L2, and L3 in the memory cell MC selected by the address signal. Next, in step S11, as described with reference to FIG. 6, the flash memory simultaneously performs the verify operation of the memory cell MC in which the logics L1, L2, and L3 are programmed. The flash memory performs the write operation and the verify operation again for the memory cells MC that are determined to be insufficiently written in the verify operation.
[0052]
In the present invention, the write operation to the plurality of memory cells MC of the plurality of logic L1-L3 can be executed at one time. In addition, the verification operation of the memory cell in which the plurality of logics L1 to L3 are written can be executed once. For this reason, the time required for the write operation and the verify operation can be shortened. As a result, it is possible to prevent the flash memory write time (program time) from increasing even in the multilevel memory cell.
[0053]
FIG. 10 shows a write operation and a verify operation before the present invention.
Before the present invention, logics L1-L3 are sequentially programmed in memory cells MC connected to one word line (steps S20, S22, S24). The verification operation is performed for each of logic L1-L3 (steps S21, S23, S25). For this reason, the write time (program time) of the flash memory is significantly increased.
[0054]
As described above, in the first embodiment, in the write operation or the verify operation, the plurality of source lines SL1-LS3 can be connected to the predetermined bit line BL according to the address and data, so that the plurality of source voltages VS1-VS3, VV1- VV3 can be simultaneously supplied to the input / output nodes of the plurality of memory cells MC via the bit line BL. In other words, a plurality of write voltages VS1-VS3 corresponding to all the logic L1-L3 of the write data can be output to the source lines VS1-VS3, respectively. Each memory cell MC can be written. Note that since the logic L0 is an erased state (initial state) logic, no write voltage is required. In addition, since a plurality of verification voltages VV1-VV3 can be output simultaneously, a plurality of memory cells MC in which all the logical values L0-L3 are written can be verified in one verification operation. As a result, the execution time of the write operation and the verify operation can be shortened. That is, it is possible to shorten the writing time for writing data in the memory cell MC (the busy period of the ready / busy signal R / B).
[0055]
The first and second switch control circuits 34 and 36 output a switch control signal according to write data and an address supplied via the external terminal I / O, so that the memory cell MC selected according to the address In addition, the logical value indicated by the write data can be reliably written. Further, the data written in the memory cell MC can be reliably verified.
[0056]
In the write operation, a plurality of write voltages VS1 to VS3 and verification voltages VV1 to VV3 are simultaneously supplied to the bit line, so that a plurality of memory cells MC connected to one word line WL can Each logic value can be written. In the verification operation, since a plurality of verification voltages VV1 to VV3 are simultaneously supplied to the bit lines, a plurality of memory cells MC connected to one word line WL and written with different logic values are verified once. Can be verified by operation.
[0057]
By configuring the memory cell array 30 with the memory cells MC having the trap insulating film, data can be stored in a plurality of locations in one memory cell MC. Even when data of a large number of bits is stored in the memory cell MC, the write operation time and the verification operation time can be shortened compared to the conventional case.
FIG. 11 shows a second embodiment of the nonvolatile multilevel semiconductor memory of the present invention. This embodiment corresponds to claims 1 to 3, claim 4 and claim 5. The same circuits / signals as those described in the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.
[0058]
The flash memory has a column address decoder 40 and a memory cell array 42 instead of the column address decoder 26 and the memory cell array 30 of the first embodiment. The memory cell array 42 stores data only in one of the trap regions of each memory cell MC (only on the left side in the figure). That is, the memory cell MC has a single bit structure. One memory cell can store 2-bit data. The column address decoder 40 includes first and second switch circuits and a voltage control circuit similar to those of the first embodiment in order to write and verify data in the memory cell MC having a single bit structure. Other configurations are substantially the same as those of the first embodiment.
[0059]
As mentioned above, also in 2nd Embodiment, the effect similar to 1st Embodiment mentioned above can be acquired.
FIG. 12 shows a third embodiment of the nonvolatile multilevel semiconductor memory of the present invention. This embodiment corresponds to claims 1-5. The same elements as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.
[0060]
The flash memory has an internal voltage generation circuit 44, a column address decoder 46, and a memory cell array 48 instead of the internal voltage generation circuit 10, the column address decoder 26, and the memory cell array 30 of the first embodiment. The internal voltage generation circuit 44 generates seven types of write voltages, seven types of verification voltages, and first and second drain voltages in order to write seven logical values to the memory cell MC. There are eight types of logical values that can be stored in the memory cell MC, including the erased state. The column address decoder 46 selectively supplies the write voltage, verification voltage, and first and second drain voltages supplied from the internal voltage generation circuit 44 to a predetermined bit line corresponding to the address signal. The memory cell array 48 stores 3-bit data in both of the trap regions of each memory cell MC. That is, the memory cell MC has a double bit structure. One memory cell can store 6-bit (64 values) data. Other configurations are substantially the same as those of the first embodiment.
[0061]
FIG. 13 shows essential parts of the memory cell array 48 and the column address decoder 46 shown in FIG.
The memory cell array 30 is composed of a plurality of memory blocks, and each memory block has eight memory areas MA0-MA7 corresponding to 8-bit data terminals I / O0-I / O7. The word line WL is wired in common to the eight memory areas MA0 to MA7.
[0062]
The column address decoder 46 has a plurality of source line areas SLA0 to SLA7 corresponding to the memory areas MA0 to MA7. Each source line region SLA0-SLA7 includes first and second switch control circuits 50, 52, a voltage control circuit 54, a plurality of first switches SW1, a plurality of second switches SW2, and a first switch control line SC1 (SC11, SC12). , SC13, SC14,...), A second switch control line SC2 (SC21, SC22, SC23, SC24,...), Source lines SL1-SL3, and drain lines DL.
[0063]
The first switch control circuit 50 applies a first high-level signal to a predetermined first switch control line SC1 according to an address signal (lower bit) and a logical value of write data during a write operation and a verification operation after the write operation. Outputs a switch control signal. In response to the output of the first switch control signal, one of the switches SW1 is turned on every other bit line BL.
[0064]
The second switch control circuit 52 applies a second high-level signal to the predetermined second switch control line SC2 in accordance with the address signal (lower bit) and the logical value of the write data during the write operation and the verify operation after the write operation. Outputs a switch control signal. In response to the output of the second switch control signal, one of the switches SW2 is turned on every other bit line BL.
[0065]
In the write cycle for writing data to the memory cell MC, the voltage control circuit 54 first supplies four write voltages VS1 to VS4 respectively corresponding to the logic L1 to L4 among the seven types of logic L1 to L7 of the write data. Then, the first drain voltage VDP is output to the drain line DL (first write operation). Next, the voltage control circuit 38 outputs four verification voltages VV1-VV4 respectively corresponding to the logics L1-L4 to the source lines SL1-SL4, and outputs a second drain voltage VDR to the drain line DL (first). 1 verification operation). Next, the voltage control circuit 38 outputs three write voltages VS5-VS7 respectively corresponding to the logics L5-L7 to the source lines SL1-SL3, and outputs the first drain voltage VDP to the drain line DL (second). Write operation). Next, the voltage control circuit 38 outputs four verification voltages VV5-VV7 respectively corresponding to the logics L5-L7 to the source lines SL1-SL3, and outputs a second drain voltage VDR to the drain line DL (first). 2 verification operation).
[0066]
Write voltages VS1-VS7, verification voltages VV1-VV7, first and second drain voltages VDP, VDR are generated by internal voltage generation circuit 44 shown in FIG.
FIG. 14 shows voltages generated by the internal voltage generation circuit 44 and the high voltage generation circuit 12 shown in FIG.
In the first write operation (first program operation), the internal voltage generation circuit 44 writes the write voltages VS1 corresponding to the logic L1-L4 (“110”, “101”, “100”, “011”) of the write data, respectively. , VS2, VS3, VS4 (for example, 0.23V, 0.20V, 0.17V, 0.14V, respectively) and the first drain voltage VDP (for example, 6.0V) are output. The high voltage generation circuit 12 outputs a gate voltage VGP (for example, 9.8 V). The gate voltage VGP is supplied to the word line WL selected by the row address decoder 24 according to the address signal (upper bit).
[0067]
In the first verification operation after the first write operation, the internal voltage generation circuit 44 uses the verification voltages VV1 corresponding to the write data logic L1-L4 ("110", "101", "100", "011"), respectively. , VV2, VV3, VV4 (for example, 0.23V, 0.20V, 0.17V, 0.14V, respectively) and the first drain voltage VDR (for example, 4.0V) are output. The high voltage generation circuit 12 outputs a gate voltage VRD (for example, 4.0 V). The gate voltage VRD is supplied to the selected word line WL during the write operation.
[0068]
Next, in the second write operation (second program operation), the internal voltage generation circuit 44 writes the write voltages VS5, L5, L7 (“010”, “001”, “000”) of the write data respectively. VS6, VS7 (for example, 0.11V, 0.08V, 0.05V, respectively) and the first drain voltage VDP (for example, 6.0V) are output. The high voltage generation circuit 12 outputs a gate voltage VGP (for example, 9.8 V). The gate voltage VGP is supplied to the word line WL selected by the row address decoder 24 according to the address signal (upper bit).
[0069]
In the second verification operation after the second write operation, the internal voltage generation circuit 44 uses the verification voltages VV5, VV6, VV7 corresponding to the logic L5-L7 ("010", "001", "000") of the write data, respectively. (For example, 0.11 V, 0.08 V, and 0.05 V, respectively) and the first drain voltage VDR (for example, 4.0 V) are output. The high voltage generation circuit 12 outputs a gate voltage VRD (for example, 4.0 V). The gate voltage VRD is supplied to the selected word line WL during the write operation.
[0070]
In the present embodiment, since the write operation and the verify operation are executed in two steps in the write cycle, the source lines SL1 to SL4 can be shared by a plurality of write voltages VS in the write operation, and in the verify operation, the source line SL1 -SL4 can be shared by multiple verification voltages VV. As a result, the number of source lines SL1-SL4 can be made smaller than the logical number of write data, and the area of the multilevel memory cell column address / buffer can be reduced.
[0071]
FIG. 15 shows the relationship between the logical value of the write data and the threshold voltage of the memory cell MC in the third embodiment. FIG. 15 shows each of the two trap regions (white squares in FIG. 12) of the memory cell MC. As described above, one memory cell MC can store 64 values by two trap areas.
The threshold voltage of each trap region of the memory cell is distributed in one of the regions L0, L1, L2, L3, L4, L5, L6, and L7 according to the logical value of the data to be written. Regions L0, L1, L2, L3, L4, L5, L6, and L7 are 2-bit data “111”, “110”, “101”, “100”, “011”, “010”, “001”, Each corresponds to "000". In the region L0, the threshold voltage is negative. In this region, the cell transistor operates as a depletion transistor. The memory cells in the regions L1 to L7 have a positive threshold voltage, and the cell transistor operates as an enhancement transistor. Memory cell MC stores logic L0 ("111") in the erased state. For this reason, in order to write the remaining seven types of logic L1-L7 into the memory cell MC, seven types of write voltages are required. In this embodiment, since the common source lines SL1 to SL3 are formed corresponding to the seven types of write voltages VS1 to VS7, two write operations are required to write all the logic to the memory cells MC. Become. In addition, since the common source lines SL1-SL3 are formed corresponding to the seven types of verification voltages VV1-VV7, two verification operations are required to verify all the logic in the memory cells MC. However, since the number of source lines SL1-SL3 can be reduced, the chip size can be reduced.
[0072]
Data writing (programming) is performed for each trap area until the threshold voltage exceeds VT (VT1, VT2, VT3, VT4, VT5, VT6, VT7). For example, when logic “010” is written in the trap region, the program operation is repeated until the threshold voltage of the cell transistor exceeds VT5. Then, the threshold voltage of each trap region is set to any one of the regions L0 to L7.
[0073]
Data is read by comparing the threshold voltage of the cell transistor with a reference voltage VR (VR1, VR2, VR3, VR4, VR5, VR6, VR7). For example, when the threshold voltage of the cell transistor is lower than the reference voltage VR1, the data held in the trap region is determined as “111”. When the threshold voltage of the cell transistor is between the reference voltages VR1 and VR2, the data held in the trap region is determined as “110”.
[0074]
FIG. 16 shows a write operation and a verify operation in the third embodiment. This flow is automatically performed in the flash memory.
First, in step S30, the flash memory simultaneously programs one of the logic L1, L2, L3, and L4 in the memory cell MC selected by the address signal (first write operation). Next, in step S31, the flash memory simultaneously performs the verification operation of the memory cell MC in which the logics L1, L2, L3, and L4 are programmed (first verification operation). The flash memory performs the first write operation and the first verify operation again for the memory cells MC that are determined to be insufficiently written in the verify operation.
[0075]
Next, in step S32, the flash memory simultaneously programs any one of logic L5, L6, and L7 in the memory cell MC selected by the address signal (second write operation). Next, in step S33, the flash memory simultaneously performs the verification operation of the memory cell MC in which the logics L5, L6, and L7 are programmed (second verification operation). The flash memory performs the second write operation and the second verify operation again on the memory cell MC that is determined to have insufficient write in the verify operation.
[0076]
As described above, also in the third embodiment, the same effect as in the first embodiment described above can be obtained. Further, in this embodiment, the number of source lines SL1-SL3 is made smaller than the logical number of write data, and the write voltages VS1-VS7 and verification voltages VV1-VV7 are divided into the source lines SL1-SL3 and output in multiple times. By doing so, the number of source lines SL1-SL3 can be reduced. That is, all the logical values can be written into the memory cells MC with the wiring area being minimized, and the memory cells in which all the logical values are written can be verified. Since the wiring area is minimized, the chip size can be reduced.
[0077]
FIG. 17 shows a fourth embodiment of the nonvolatile multilevel semiconductor memory of the present invention. This embodiment corresponds to claims 1 to 3 and claim 4. The same circuits / signals as those described in the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.
The flash memory has a column address decoder 56 and a memory cell array 58 instead of the column address decoder 26 and the memory cell array 30 of the first embodiment. The memory cell MC of the memory cell array 58 has a floating gate layer that stores electrons according to the logical value of the write data. The memory cell MC has a single bit structure, and one memory cell can store 2-bit data according to the amount of accumulated electrons. The column address decoder 56 includes first and second switch circuits and a voltage control circuit similar to those in the first embodiment in order to write and verify data in the memory cells MC. Other configurations are substantially the same as those of the first embodiment.
[0078]
As described above, also in the fourth embodiment, the same effect as that of the above-described first embodiment can be obtained.
In the first embodiment described above, the voltage control circuit 38 is formed for each of the source regions SLA0 to SLA7.
The example in which the source lines SL1, SL2, and SL3 and the drain line DL are wired independently for each of the source regions SLA0 to SLA7 has been described. However, the present invention is not limited to such an embodiment. For example, the voltage control circuit 38 may be formed in common in the source regions SLA0 to SLA7, and the source lines SL1, SL2, and SL3 and the drain line DL may be wired in common to the source regions SLA0 to SLA7. In this case, since the number of voltage control circuits 38 is reduced, the chip size of the flash memory can be reduced.
[0079]
In the above-described embodiment, the example in which the present invention is applied to the flash memory has been described. However, the present invention is not limited to such an embodiment. The present invention can be applied to an electrically rewritable nonvolatile multilevel semiconductor memory such as an EEPROM.
The invention described in the above embodiments is organized and disclosed as an appendix.
[0080]
(Supplementary Note 1) A plurality of nonvolatile memory cells having a charge storage layer for storing charges and connected in series via input / output nodes;
A word line connected to the control gate of the memory cell;
A plurality of bit lines respectively connected to the input / output nodes;
A plurality of source lines each supplied with a plurality of source voltages;
A drain line to which a drain voltage is supplied; and
A voltage generation circuit for generating the source voltage and the drain voltage;
In order to connect the bit line to either the source line or the drain line, respectively, during a write operation for writing data to the memory cell and a verification operation for confirming a logic level of data written to the memory cell, A plurality of switches respectively disposed between each bit line and the source line and between each bit line and the drain line;
A non-volatile multilevel semiconductor memory comprising a switch control circuit for generating a switch control signal for turning on the switch.
[0081]
(Supplementary Note 2) In the nonvolatile multilevel semiconductor memory according to Supplementary Note 1,
The voltage generation circuit outputs a plurality of write voltages corresponding to logical values of write data to the source line and outputs a first drain voltage to the drain line in the write operation, respectively. Multi-level semiconductor memory.
(Supplementary Note 3) In the nonvolatile multilevel semiconductor memory according to Supplementary Note 2,
The switch control circuit outputs the switch control signal in accordance with a plurality of bits of write data supplied via an external terminal and an address indicating a memory cell to which the write data is written. Non-volatile multilevel semiconductor memory.
[0082]
(Additional remark 4) In the non-volatile multi-value semiconductor memory of Additional remark 2,
The number of source lines corresponds to the logical number of write data,
The voltage generation circuit outputs a plurality of write voltages respectively corresponding to logical values of the write data to the source line at a time in the write operation.
[0083]
(Supplementary Note 5) In the nonvolatile multilevel semiconductor memory according to Supplementary Note 2,
The number of source lines is less than the logical number of write data,
The non-volatile multilevel semiconductor memory, wherein the voltage generation circuit outputs a plurality of write voltages respectively corresponding to the logical values of the write data to the source line in a plurality of times in the write operation.
[0084]
(Supplementary note 6) In the nonvolatile multi-value semiconductor memory according to supplementary note 2,
The voltage generation circuit outputs a plurality of verification voltages corresponding to logical values of write data to the source line and outputs a second drain voltage to the drain line in the verification operation, respectively. Multi-level semiconductor memory.
(Supplementary note 7) In the nonvolatile multilevel semiconductor memory according to supplementary note 6,
The number of source lines corresponds to the logical number of write data,
In the verification operation, the voltage generation circuit outputs a plurality of verification voltages respectively corresponding to the logical values of the write data to the source line at a time.
[0085]
(Supplementary Note 8) In the nonvolatile multilevel semiconductor memory according to Supplementary Note 6,
The number of source lines is less than the logical number of write data,
In the verification operation, the voltage generation circuit outputs a plurality of verification voltages respectively corresponding to the logical values of the write data to the source line in a plurality of times.
[0086]
(Supplementary note 9) In the nonvolatile multilevel semiconductor memory according to supplementary note 1,
A word voltage generation circuit that supplies a write word voltage to the word line during writing of data to the memory cell and supplies a verification word voltage to the word line during verification of data written to the memory cell. A non-volatile multi-level semiconductor memory comprising:
[0087]
(Supplementary Note 10) In the nonvolatile multilevel semiconductor memory according to the supplementary note 1,
The non-volatile multi-value semiconductor memory according to claim 1, wherein the charge storage layer of each memory cell is formed as a trap insulating film that locally traps carriers according to the logical value of the data.
(Supplementary Note 11) In the nonvolatile multilevel semiconductor memory according to the supplementary note 10,
Each of the trap insulating films traps carriers in a trap region formed on both the input / output node sides,
Each of the trap regions stores a plurality of bits of write data according to the amount of trapped carriers, respectively.
[0088]
(Supplementary Note 12) In the nonvolatile multilevel semiconductor memory according to the supplementary note 11,
Each of the trap insulating films traps carriers in one of the trap regions formed on both the input / output node sides,
One of the trap areas stores a plurality of bits of write data in accordance with the amount of trapped carriers, respectively.
[0089]
(Supplementary note 13) In the nonvolatile multilevel semiconductor memory according to supplementary note 1,
The non-volatile multi-value semiconductor memory according to claim 1, wherein the charge storage layer of each memory cell is formed as a floating gate for storing carriers according to the logical value of the data.
As mentioned above, although this invention was demonstrated in detail, said embodiment and its modification are only examples of this invention, and this invention is not limited to this. Obviously, modifications can be made without departing from the scope of the present invention.
[0090]
【The invention's effect】
In the nonvolatile multilevel semiconductor memory according to the first and second aspects, a plurality of logical values can be written in a plurality of memory cells by one write operation. In addition, a plurality of memory cells in which different logical values are written can be verified by one verification operation. As a result, the execution time of the write operation and the verify operation can be shortened in the nonvolatile multilevel semiconductor memory that stores a plurality of bits in one memory cell. That is, the writing time (busy time) for writing data into the memory cell can be shortened.
[0091]
According to another aspect of the nonvolatile multilevel semiconductor memory of the present invention, the logical value indicated by the write data can be reliably written in the memory cell selected according to the address. Further, the data written in the memory cell can be reliably verified.
[0092]
[0093]
According to another aspect of the nonvolatile multilevel semiconductor memory of the present invention, a plurality of logical values can be written in a plurality of memory cells connected to the word line by one write operation. In addition, a plurality of memory cells connected to the word line and written with different logic values can be verified by one verification operation.
[0094]
In the nonvolatile multilevel semiconductor memory according to the fifth aspect, data of a larger number of bits can be stored in one memory cell by trapping carriers in a plurality of locations of the charge storage layer. Even when data of a large number of bits is stored, the write operation time and the verification operation time can be shortened compared to the conventional case.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a first embodiment of a nonvolatile multilevel semiconductor memory of the present invention.
FIG. 2 is a block diagram showing the main parts of the memory cell array and column address decoder shown in FIG. 1;
3 is an explanatory diagram showing voltages generated by an internal voltage generation circuit and a high voltage generation circuit shown in FIG. 1; FIG.
FIG. 4 is an explanatory diagram showing a relationship between a logical value of write data and a threshold voltage of a memory cell in the first embodiment.
FIG. 5 is an explanatory diagram showing a write operation in the first embodiment.
FIG. 6 is an explanatory diagram showing a verification operation after a write operation in the first embodiment.
FIG. 7 is a characteristic diagram showing a memory cell current in the verification operation of the first embodiment.
FIG. 8 is a characteristic diagram showing a memory cell current in a verification operation before the present invention;
FIG. 9 is a flowchart showing a write operation and a verify operation in the first embodiment.
FIG. 10 is a flowchart showing a write operation and a verify operation before the present invention.
FIG. 11 is a block diagram showing a second embodiment of the nonvolatile multilevel semiconductor memory of the present invention.
FIG. 12 is a block diagram showing a third embodiment of the nonvolatile multilevel semiconductor memory of the present invention.
13 is a block diagram showing the main parts of the memory cell array and column address decoder shown in FIG. 12;
14 is an explanatory diagram showing voltages generated by the internal voltage generation circuit and the high voltage generation circuit shown in FIG. 12. FIG.
FIG. 15 is an explanatory diagram showing a relationship between a logical value of write data and a threshold voltage of a memory cell in the second embodiment.
FIG. 16 is a flowchart showing a write operation and a verify operation in the third embodiment.
FIG. 17 is a block diagram showing a fourth embodiment of a nonvolatile multilevel semiconductor memory of the present invention.
[Explanation of symbols]
10, 44 Internal voltage generation circuit
12 High voltage generator
14 State control circuit
16 Command register
18 Address register
20 Status register
24 row address decoder
26, 40, 46, 56 Column address decoder
28 page buffer
30, 42, 48, 58 Memory cell array
32 I / O buffers
34, 50 First switch control circuit
36, 52 Second switch control circuit
38, 54 Voltage control circuit
BL bit line
CMD1, CMD2 command signal
DL Drain line
I / O input / output terminal
MA0-7 memory area
MC memory cell
R / B Ready / Busy signal
SC1 1st switch control line
SC2 Second switch control line
SL1-SL3 source line
SLA0-SLA7 Source line area
SW1 1st switch
SW2 second switch
TG trap gate
VS1-VS7 write voltage
VDP first drain voltage
VDR Second drain voltage
VGP gate voltage
VRD gate voltage
VV1-VV7 Verification voltage
WL word line

Claims (5)

A plurality of NOR type nonvolatile memory cells having a charge storage layer for storing charges in two regions in the same memory cell, arranged in a virtual ground type memory cell array configuration and connected in series via input / output nodes When,
A plurality of source lines connected to a source end of the NOR type nonvolatile memory cell and supplied with a plurality of source voltages each having a different voltage value for each logical value written to the NOR type nonvolatile memory cell;
A drain line connected to a drain end of the NOR type nonvolatile memory cell and supplied with a drain voltage;
A voltage generating circuit for generating the plurality of source voltages and the drain voltage;
Provided for each bit line, the time verification operation to check the logic level of data written to the write operation and the NOR type nonvolatile memory cell write data to nonvolatile memory cells, each of said bit lines of said plurality In order to connect to either the source line or the drain line, the bit line and each of the plurality of source lines and between the bit line and the drain line are arranged, respectively. A plurality of switches provided outside;
A non-volatile multilevel semiconductor memory comprising a switch control circuit for generating a switch control signal for turning on the switch. A plurality of NOR type nonvolatile memory cells having a charge storage layer for storing charges in two regions in the same memory cell, arranged in a virtual ground type memory cell array configuration and connected in series via input / output nodes When,
A plurality of source lines connected to the source end of the NOR type nonvolatile memory cell and supplied with a plurality of source voltages each having a different voltage value for each logical value written to the NOR type nonvolatile memory cell;
A drain line connected to a drain end of the NOR type nonvolatile memory cell and supplied with a drain voltage;
A voltage generating circuit for generating the plurality of source voltages and the drain voltage;
Provided for each bit line, the time verification operation to check the logic level of data written to the write operation and the NOR type nonvolatile memory cell write data to nonvolatile memory cells, each of said bit lines of said plurality In order to connect to either the source line or the drain line, the bit line and each of the plurality of source lines and between the bit line and the drain line are arranged, respectively. A plurality of switches provided outside;
A non-volatile multilevel semiconductor memory comprising a switch control circuit for generating a switch control signal for turning on the switch. The nonvolatile multilevel semiconductor memory according to claim 1 or 2,
The switch control circuit outputs the switch control signal in accordance with a plurality of bits of write data supplied via an external terminal and an address indicating a memory cell to which the write data is written. Non-volatile multilevel semiconductor memory. The nonvolatile multilevel semiconductor memory according to claim 1 or 2,
A word voltage generation circuit that supplies a write word voltage to the word line during writing of data to the memory cell and supplies a verification word voltage to the word line during verification of data written to the memory cell. A non-volatile multi-level semiconductor memory comprising: The nonvolatile multilevel semiconductor memory according to claim 1 or 2,
The non-volatile multi-value semiconductor memory according to claim 1, wherein the charge storage layer of each memory cell is formed as a trap insulating film that locally traps carriers according to the logical value of the data.

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