JPH10112196A - Non-volatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor memory in which the number of times of verifying and the number of times of charge and discharge of a decoder can be reduced, and a total writing time can be shortened. SOLUTION: This device is provided with AND gates 16a, 16b in which, if writing data of (n) bits stored in a page buffer 15 has bit data of the prescribed logic '0', data is converted to a low level data, and if it has not bit data of logic '0', data is converted to a high level data, writing/reading control circuits 12a, 12b which has a latch, latches high or low data outputted from the gates 16a, 16b, outputs it to a selected bit line and performs writing when the latch data is a low level, and discriminating circuits 17a, 17b in which rear out data is compared with corresponding writing data stored in the page buffer 15, it is discriminated whether writing is sufficient or not, and if writing is sufficient, data is converted to a non-writing data, and rewritten in the page buffer 17a, 17b.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-valued nonvolatile semiconductor memory device for recording data of at least three values in a memory cell.

[0002]

2. Description of the Related Art Conventionally, in a semiconductor nonvolatile storage device such as an EPROM or a flash memory, a binary memory in which data having two values of "0" and "1" is recorded in one memory cell transistor. Cell structure is usual. However, with the recent demand for increasing the capacity of the nonvolatile semiconductor memory device, at least three memory cell transistors are required.
A so-called multilevel nonvolatile semiconductor memory device that records data equal to or larger than a value has been proposed (for example, “A
Multi-Level 32Mb Flash Me
molly "'95 ISSCC p132-).

FIG. 15 shows a NAND-type flash memory in which one memory transistor has two bits.
Threshold voltage Vth when recording data having a value
FIG. 4 is a diagram illustrating a relationship between a level and data content.

In FIG. 15, the vertical axis represents the threshold voltage Vth of the memory transistor, and the horizontal axis represents the distribution frequency of the memory transistor. The content of 2-bit data constituting data to be recorded in one memory transistor is represented by [IO _{n + 1} , IO _n ], and [IO _{n + 1} , IO _n ].
_{n + 1} , IO _n ] = [1, 1], [1, 0], [0,
1] and [0, 0]. That is, data “0”, data “1”, data “2”, data “3”
There are four states:

A NAND flash memory in which multi-level data is written in page units (word line units) has been proposed (for example, reference: 1996 IEEE Intern).
ational Solid-State Circuits Conference, ISSCC96 /
SESSION 2 / FLASH MEMORY / PAPER TP 2.1: A 3.3V 128Mb M
ulti-Level NAND Flash Memory For Mass Storage Appl
ication.pp32-33).

FIG. 16 is a circuit diagram showing a configuration of a main part of a NAND flash memory which performs writing in page units disclosed in the above document. In FIG. 16, 1 is a memory cell array, 2 is a write / read control circuit, and BLL and BLR.
Indicates bit lines.

The memory cell array 1 is composed of memory cell blocks A0 and A1 whose memory cells are connected to common word lines WL0 to WL15. The memory cell block A0 is connected to the bit line BLR, and the memory cell block A1 is connected to the bit line BLL. The memory cell block A0 has a NAND string in which memory cell transistors MT0A to MT15A each composed of a nonvolatile semiconductor memory device having a floating gate are connected in series, and the drain of the memory cell transistor MT0A in the NAND string is a selection gate. SG
The memory cell transistor MT15A is connected to the reference potential line VGL via the select gate SG2A. The memory cell block A1 includes a memory cell transistor MT formed of a nonvolatile semiconductor memory device having a floating gate.
0B to MT15B have a NAND string connected in series, and the memory cell transistors MT of this NAND string
0B is connected to the bit line BLL via the select gate SG1B, and the memory cell transistor MT15B
Is connected to the reference potential line VG via the selection gate SG2B.
L.

Then, the gates of the selection gates SG1A and SG1B are commonly connected to the selection signal supply line SSL, and the gates of the selection gates SG2A and SG2B are connected to the selection signal supply line G.
It is commonly connected to SL.

The write / read control circuit 2 has an n-channel MO
S (NMOS) transistors NT1 to NT17, p-channel MOS (PMOS) transistor PT1, and latch circuit Q1,
Q2.

The NMOS transistor NT1 has a power supply voltage V
_The gate is connected between the supply line of _CC and the bit line BLR, and the gate is connected to the supply line of the inhibit signal IHB1. The NMOS transistor NT2 is connected between the supply line of the power supply voltage V _CC and the bit line BLL, and has a gate connected to the supply line of the inhibit signal IHB2. A depletion type NMOS transistor NT18 is connected between a connection point between the bit line BLR and the NMOS transistor NT1 and a connection point between the memory cell block A0 and the bit line BLR, and a connection point between the bit line BLL and the NMOS transistor NT2 and the memory. A depletion-type NMOS transistor NT19 is connected between the connection point between the cell block A1 and the bit line BLL. The gates of the NMOS transistors NT18 and NT19 are connected to a decouple signal supply line DCPL.

An NMOS is provided between a connection point between the bit line BLR and the NMOS transistor NT1 and the bus line IOi.
Transistors NT3, NT5, and NT16 are connected in series, and bit line BLL and NMOS transistor NT2 are connected.
The NMOS transistors NT4, NT7, and NT17 are connected in series between the connection point (1) and the bus line IOi + 1. The connection point between the NMOS transistors NT3 and NT5 and the connection point between the NMOS transistors NT4 and NT7 are grounded via the NMOS transistor NT6, and the drain of the PMOS transistor PT1 and N
It is connected to the gates of MOS transistors NT8 and NT13. Then, the gate of the NMOS transistor NT6 is connected to the supply line of the reset signal RST,
The source of the OS transistor PT1 is connected to the supply line of the power supply voltage V _CC, the gate of the PMOS transistor PT1 is connected to the supply line of the signal Vref.

First storage node N1a of latch circuit Q1
Is connected to a connection point between the NMOS transistors NT5 and NT16, and the second storage node N1b is grounded via NMOS transistors NT8 to NT10 connected in series. The first storage node N2a of the latch circuit Q2 is connected to a connection point between the NMOS transistors NT7 and NT17, and the second storage node N2b is connected in series.
It is grounded via MOS transistors NT13 to NT15. Also, the NMOS transistors NT8 and NT9
NMOS transistor NT whose connection point is connected in series
11, grounded via NT12. The gate of the NMOS transistor NT9 is connected to the first storage node N2a of the latch circuit Q2.
0 is connected to the supply line of the latch signal φLTC2, the gate of the NMOS transistor NT11 is connected to the second storage node N2b, and the NMOS transistor N
The gate of T12 is connected to the supply line of the latch signal φLTC1, and the gates of the NMOS transistors NT14 and NT15 are connected to the supply line of the latch signal φLTC3. The gate of the NMOS transistor NT16 as a column gate is connected to the supply line of the signal Yi, and the gate of the NMOS transistor NT17 is connected to the signal Yi.
It is connected to the i + 1 supply line.

FIG. 17A shows a timing chart at the time of reading, and FIG. 17B shows a timing chart at the time of writing (program). FIG.
As can be seen from (b), the quaternary writing is performed in three steps, and the process proceeds to the next step when it is determined that all cells to be written in page units in each step are sufficiently written.

The read operation will be described. First, the reset signal RST and the signals PGM1 and PGM2 are set to a high level. As a result, the first storage nodes N1a and N2a of the latch circuits Q1 and Q2 are pulled to the ground level. As a result, the latch circuits Q1 and Q2 are cleared.
Next, reading is performed with the word line voltage set to 2.4V. If the threshold voltage Vth is higher than the word line voltage (2.4 V), the cell current does not flow, so that the bit line voltage holds the precharge voltage and high is sensed. On the other hand, if the threshold voltage Vth is lower than the word line voltage (2.4 V), the cell current flows to lower the bit line voltage and sense low. Then, the data is read out three times to generate 2-bit data and then output to the IO. Next, reading is performed at a word line voltage of 1.2 V, and finally reading is performed at a word line voltage of 0 V.

Specifically, when the cell data is "00",
Since no current flows in all word lines, the bus IO _{i + 1} ,
(1, 1) is output to IO _i . First, when reading with the word line voltage set to 2.4 V, the latch signal φLTC1 is set to a high level. At this time, since the cell current does not flow, the bit line is kept at a high level,
Since the S transistor NT8 is kept conductive and the latch circuit Q2 is cleared, the second storage node N2b of the latch circuit Q2 is kept at a high level.
OS transistor NT11 is kept conductive. Therefore, the NMOS transistors NT8, NT11, NT
12 is kept conductive, the second storage node Nb1 of the latch circuit Q1 is pulled to the ground level, and the first storage node N1a of the latch circuit Q1 transitions to the high level. Next, when reading with the word line voltage set to 1.2 V, the latch signal φLTC3 is set to the high level. At this time, since the cell current does not flow, the bit line is kept at a high level, so that the NMOS transistor NT13 is kept conductive, the second storage node N2b of the latch circuit Q2 is pulled to the ground level, and the latch circuit Q2 Transitions to the high level. Finally, when reading with the word line voltage set to 0 V, the latch signal φLTC1 is set to a high level. At this time, since the cell current does not flow, the bit line is kept at a high level and the NMOS transistor NT8 is kept in a conductive state.
NMOS because the second storage node N2b is low level
The transistor NT11 is turned off, and the first storage node N1a of the latch circuit Q1 holds the high level.

When the cell data is "01", the word line V
Current flows only in the case of WL00, and buses IO _{i + 1} , IO _i
Output (1, 0). First, when reading with the word line voltage set to 2.4 V, the latch signal φLTC1 is set to a high level. At this time, since the cell current does not flow, the bit line is kept at a low level, so that the NMOS transistor NT8 is kept off, and the latch circuit Q
One first storage node N1a holds the low level.
Next, when reading with the word line voltage set to 1.2 V, the latch signal φLTC3 is set to a high level. At this time, since the cell current does not flow, the bit line is kept at a high level, so that the NMOS transistor NT13 is kept conductive, the second storage node N2b of the latch circuit Q2 is pulled to the ground level, and the latch circuit Q2 Transitions to the high level. Finally, when reading with the word line voltage set to 0 V, the latch signal φLTC1 is set to a high level. At this time, since the cell current does not flow, the bit line is kept at a high level, so that the NMOS transistor NT8 is kept conductive. However, since the second storage node N2b of the latch circuit Q2 is at a low level, the NMOS transistor NT11 is kept at a low level. Becomes non-conductive, and the latch circuit Q
One first storage node N1a holds the low level.
Cell data is "10", "11" for each bus IO _i + 1, IO _i in the same manner in the case of (0,1), is read out (0,0).

Next, the write operation will be described. In the circuit of FIG. 16, first, writing is performed by the data stored in the latch circuit Q1, then writing is performed by the latch circuit Q2, and finally by the data of the latch circuit Q1 again. Write data is (Q2, Q1)
= (1, 0), the latch circuit Q1 inverts from "0" to "1" when writing is sufficient, but (Q2, Q1)
In the case of = (0,0), the latch circuit Q1 must be used as the write data in the third step, so that even if the write is sufficient in the first step, it is not inverted from "0" to "1" (cannot be performed). .

In each step, the end of the write is determined when all the latched data becomes "1". Write data (Q
In the cell of (2, Q1) = (0, 0), the inversion of the latch circuit Q1 in the first step does not occur, so that the end determination by the wired OR is not performed.

[0019]

As described above, in a conventional multi-valued circuit, writing is performed in a plurality of steps as shown in FIG. That is, in the conventional method, for example, in the case of four values, writing in three steps is performed. That is, first, writing of IOn + 1, n = (1, 0) is performed, and after it is determined that all the written cells in the page are sufficiently written, writing / determination of IOn + 1, n = (1, 0) is performed. IOn + 1, n = (0,
0) is written / determined, and the multi-level writing ends. Then, it is necessary to reset the write time / write voltage at the beginning of each step. At this time, some pages have fast writing cells and some have slow writing cells in the page. For this reason, the write time / write voltage at the time of resetting is determined by the fastest cell to write. Then, the total write time and the number of times of verification in each step depend on the slowest cell to be written.

Therefore, in the case of the conventional circuit, the number of times of verification increases, and the total writing time increases. Furthermore, DINOR can be used for NAND flash.
Since the rising voltage is used for the word line voltage at the time of writing even in the / AND type flash, it is necessary to discharge the decoder and charge the decoder before and after the verification, and this time takes several microseconds for each verification. ing.

Generally, the function of the write time of the flash memory and the threshold voltage Vth changes logarithmically with time as shown in FIG. 19 (FIG. 19 shows DINOR
Type). As a writing method, as shown in FIG. 20A, writing was performed with equal pulses, but verification is performed periodically in the latter half of the writing even though the threshold voltage Vth does not change much. However, the time required for verification has been a problem. Under such circumstances, a power application method as shown in FIG. 20B has been proposed. The power application method is a method in which the writing pulse width is set to a constant value, for example, 1.2 times, for each writing operation, and writing is performed. As a result, the writing time becomes longer as the writing progresses. As a result, the number of times of the verification and the time required for the verification are reduced, and the total writing time is reduced. FIG. 2 shows a method for obtaining the same effect.
There is an ISPP method as shown in FIG. This method is to increase the absolute value of the gate voltage at the time of writing as the writing proceeds.

However, even in the power application method and the ISPP method, when the step writing is performed as described above, the initial writing time / time when the next step is performed is calculated.
Since the write voltage is rate-determined by cells with fast write, and the write time of that step is rate-determined by cells with slow write, the number of times of verify and the number of charge / discharge of the decoder circuit at the time of verify increases, and the total write time increases. There's a problem.

In the conventional circuit described above, it is necessary to arrange two latch circuits Q1 and Q2 and a multi-valued write / read control circuit at an interval of two bit lines, and the layout is not easy. The layout area also increases. Further, in the case of developing 8-value and 16-value, it is presumed that the circuit configuration is further complicated and the layout area is significantly increased. Further, it is not possible to determine the end of writing in each step.

The present invention has been made in view of such circumstances, and has as its object to reduce the number of times of verification and the number of times of charging / discharging of a decoder, to shorten the total writing time, and to simplify the layout. It is an object of the present invention to provide a nonvolatile semiconductor memory device capable of reducing a layout area and performing a write end determination for each step.

[0025]

In order to achieve the above object, according to the present invention, the amount of charge stored in a charge storage section changes in accordance with the voltage applied to a word line and a bit line. A memory cell that changes threshold voltage and stores data of a value corresponding to the threshold voltage, and writes multi-valued data of three or more values into the memory cell in page units, and whether or not writing is sufficient after writing; A non-volatile semiconductor memory device that performs verification of the above and rewrites data if insufficient, and when writing, bit data of a predetermined logic level that requires a threshold voltage transition to n-bit write data In some cases, writing is performed, and as a result of the verification, the data for the cell, for which writing is sufficient, is sequentially converted into non-writing data in which the predetermined logic level does not exist, and the rewriting is performed. Having a write circuit to suppress.

Further, according to the present invention, the amount of charge stored in the charge storage portion changes according to the voltage applied to the word line and the bit line, and the threshold voltage changes according to the change. A memory cell for storing data of a value corresponding to a voltage, writing multi-valued data of three or more values into the memory cell in page units, and verifying whether or not writing is sufficient after writing; Is a non-volatile semiconductor memory device that performs rewriting, and requires a page buffer for storing n-bit write data, and a need to transition a threshold voltage to the n-bit write data stored in the page buffer during writing. A conversion circuit for converting bit data of a certain logic level to first data if there is such bit data, and converting to bit data if there is no bit data of the certain logic level; A latch circuit, latches the first or second data output from the conversion circuit, and outputs the data to a selected bit line when the latched data is the first data to perform writing. The write control circuit to be executed compares the read data and the corresponding write data stored in the page buffer at the time of verification to determine whether or not the write is sufficient. A determination circuit for converting the write data into non-write data in which the predetermined logic level does not exist and writing it back to the page buffer;

According to the present invention, in a nonvolatile semiconductor memory device having a multi-valued configuration and having a page write function, the threshold voltage Vt is not written for each multiplexed data.
Write is performed only on the cells that need to change h. In other words, writing is not performed for each step, and writing is performed if, for example, logic “0” is included in the write data to be multi-valued. Then, 2 ⁿ -1 verify operations are performed for each write operation, the results are compared with the write data, and the multi-valued data determined to be sufficient for the write operation is sequentially converted into data that is not to be written. By employing the above-described writing method, the number of times of verification can be reduced, and the total writing time can be reduced.

Further, according to the present invention, after writing is performed in page units, verify writing is performed again, and writing is performed in order from a lower threshold level to a higher threshold level, thereby providing a write verify threshold. Memory cells which do not reach the threshold voltage are eliminated, and the variation in the distribution of the write threshold voltage is suppressed.

[0029]

FIG. 1 is a block diagram showing an embodiment of a nonvolatile semiconductor memory device according to the present invention, and FIG.
2 is a circuit diagram showing a specific configuration example of a memory cell array and a write / read control circuit in FIG. The nonvolatile semiconductor memory device 10 includes memory cell arrays 11a and 11b,
Write / read control circuits 12a, 12b, input buffer 13
−0 to 13-3, output buffers 14-0 to 14-3, page buffer 15, AND gates 16a and 16b, determination circuits 17a and 17b, addition circuits 18a and 18b, and N
It is composed of MOS transistors 19a and 19b. The NMOS transistors 19a. The gate 19b is commonly connected to a signal WD supply line. Note that the signal WD is given as a pulse signal which takes a high level when transferring write data from the page buffer 15 to the write / read control circuits 12a and 12b.

The memory cell arrays 11a and 11b have the same configuration, and as shown in FIG. 2, each memory cell is composed of memory cell blocks A0 and A1 connected to common word lines WL0 to WL15. And
The memory cell block A0 is connected to the bit line BLR,
The memory cell block A1 is connected to the bit line BLL. The memory cell block A0 has a NAND string in which memory cell transistors MT0A to MT15A each composed of a nonvolatile semiconductor memory device having a floating gate are connected in series, and the drain of the memory cell transistor MT0A in the NAND string is a selection gate. SG1A
And the source of the memory cell transistor MT15A is connected to the reference potential line VGL via the selection gate SG2A. The memory cell block A1 includes a memory cell transistor MT0B formed of a nonvolatile semiconductor memory device having a floating gate.
To MT15B have a NAND string connected in series, and the memory cell transistors MT0B of this NAND string
Of the bit line BL via the select gate SG1B.
L, and the source of the memory cell transistor MT15B is connected to the reference potential line VGL via the selection gate SG2B.

The gates of the selection gates SG1A and SG1B are commonly connected to the selection signal supply line SSL, and the gates of the selection gates SG2A and SG2B are connected to the selection signal supply line G.
It is commonly connected to SL.

The write / read control circuits 12a and 12b
It is composed of MOS transistors NT21 to NT30, PMOS transistors PT21 and PT22, and latch circuits Q21 and Q22 which are formed by coupling inputs and outputs of an inverter.

Bit line BLR and bus line IO01BU
NMOS transistors NT21 and NT29 are connected in series between the bit line BLL and the bus line IO23.
BUS and NMOS transistors NT22 and NT3
0 are connected in series. NMOS transistor NT
Signal PGM2 takes a positive high voltage V _PP (for example, +8 V) level and a ground level at the time of writing, and a power supply voltage Vcc and a ground level at the time of reading.
1 supply line and the NMOS transistor NT
The gate 22 takes a positive high voltage V _PP level and the ground level at the time of writing, are connected to the supply line of the signal PGM22 taking power supply voltage Vcc and the ground level at the time of reading.

The node between the NMOS transistor NT21 and the bit line BLR is connected to the NMOS transistor NT2.
3 and is connected to the drain of the PMOS transistor PT21 and the NMOS transistor NT.
It is connected to 25 gates. Then, the gate of the NMOS transistor NT23 is connected to the supply line of the reset signal RST, the source of the PMOS transistor PT21 is connected to the supply line of the power supply voltage Vcc,
The gate of the S transistor PT21 is connected to the supply line of the signal Vref. Also, the NMOS transistor N
A connection point between T22 and the bit line BLL is grounded via an NMOS transistor NT24, and this connection point is connected to a PMOS
The drain of the transistor PT22 and the gate of the NMOS transistor NT27 are connected. And N
The gate of the MOS transistor NT24 outputs the reset signal R
ST, the PMOS transistor P
The source of T22 is connected to the supply line of the power supply voltage Vcc, and the gate of the PMOS transistor PT22 is connected to the signal Vre.
f is connected to the supply line.

First storage node N2 of latch circuit Q21
1a is connected to a connection point between the NMOS transistors NT21 and NT29, and the second storage node N21b is grounded via NMOS transistors NT25 and NT26 connected in series. The first storage node N22a of the latch circuit Q2 is connected to the NMOS transistors NT22 and NT30.
And the NMOS transistors NT27 and NT2 connected in series to the second storage node N22b.
8 is grounded. Note that these latch circuits Q
21 and Q22 operate on the high voltage _VPP system at the time of writing.

The NMOS transistors NT26, N
The gate of T28 is connected to the supply line of the latch signal φLTC, and the NMOS transistor N as a column gate
The gate of T29 is connected to the supply line of the signal Yi,
The gate of the MOS transistor NT30 is connected to the supply line for the signal Yi + 1.

The input buffer 13-0 has an input / output terminal IO
The write data input to 0 is input to the page buffer 15. Similarly, the input buffer 13-1 causes the write data input to the input / output terminal IO1 to be input to the page buffer 15, and the input buffer 13-2 stores the write data input to the input / output terminal IO2 to the page buffer 15. The input buffer 13-3 inputs the write data input to the input / output terminal IO3 to the page buffer 1
5 is input. The output buffer 14-0 outputs predetermined read data stored in the page buffer 15 from the input / output terminal IO0. Similarly, the output buffer 14-1
Outputs predetermined read data stored in the page buffer 15 from the input / output terminal IO1, and outputs
-2 outputs predetermined read data stored in the page buffer 15 from the input / output terminal IO2, and the output buffer 14-3 outputs predetermined read data stored in the page buffer 15 from the input / output terminal IO3. .

At the time of writing, the page buffer 15
The n-bit (for example, 4 bits) write data input via the input buffers 13-0 to 13-3 is stored, and the AND gates 16a and 16b are connected to the input / output lines IO _n N and IO _{n + 1} N. Output each, and at the time of verification after writing, the stored data is
The signal is supplied to one input terminal of the AND gates 16a and 16b via On + 1N (IO1N and IO3N in FIG. 1). Further, data read by the verify read after writing and input to the discriminating circuits 17a and 17b is stored via the input / output lines IOnN and IOn + 1N. At the time of reading, the addition circuits 18a and 18b convert the 2 ⁿ value to n.
Read data converted to bits is input / output line IO
0N, IO1N, IO2N, and IO3N,
The corresponding data is output to the output buffers 14-0 to 14-3, and the pre-read data stored in the addition circuits 18a and 18b is used as addition data via the input / output lines IO0N, IO1N, IO2N and IO3N. Supply.

At the time of writing, AND gates 16a and 16b receive write data stored in page buffer 15 via input / output lines IOnN and IOn + 1N, take a logical product of them, and write / read the result. The data is output to the control circuits 12a and 12b, respectively, and at the time of verification after writing, the n-bit write data stored in the page buffer 15 received via the input / output lines IO1N and IO3N and the input / output lines IO0N and IO2N.
Of the comparison result data of the discriminating circuits 17a and 17b received through the memory, and writes the result as a write / control circuit 12
a, 12b and discrimination circuits 17a, 17b, respectively. When writing, the write data is (0,0),
(0,1), (1,0) AND gate 16a, 1
The output of 6b goes low to write data. In the case of (1, 1), the output goes high and no data is written.

The discriminating circuits 17a and 17b have the same configuration, and compare the data read by the verify read after the write with the data of the same address stored in the page buffer to sufficiently write the data. It is determined whether or not it has been touched, and the result is output to the AND gate 16a, 1.
6b. Then, when the writing is sufficiently performed, the data is converted into non-writing data of (1, 1) having no bit data of logic “1”, and is written back to the page buffer 15 to prevent rewriting.

FIG. 3 is a circuit diagram showing a specific configuration example of the discriminating circuits 17a and 17b. The determination circuit 17a (17
3B shows, as shown in FIG. 3, D-type flip-flops FF171 and FF172 with a preset function, two-input AND gates AN171, AN172 and AN173, two-input AND gate ND171 and NMOS transistors NT171 and NT17.
2, NT173, NT174 and NT175.

The D input terminal of the flip-flop FF171 is connected to the input / output line IOn + 1N of the page buffer 15, the clock input terminal is connected to the input line of the clock signal VFCK, and the Q output terminal is the AND gate AN173.
And the inverted / Q output terminal is connected to one input terminal of AND gates AN171 and AN172. The D input terminal of the flip-flop FF172 is connected to the input / output line IOnN of the page buffer 15, the clock input terminal is connected to the input line of the clock signal VFCK, the Q output terminal is connected to the other input terminal of the AND gate AN172, The inverted / Q output terminal is connected to the other input terminals of the AND gates AN171 and AN173. Then, flip-flops FF171 and FF17
The second preset terminal is commonly connected to the output terminal of the NAND gate ND171. The output terminal of the AND gate AN171 is via the NMOS transistor NT171, and the output terminal of the AND gate AN172 is the NMOS transistor NT171.
Through 172, the output terminal of AND gate AN173 is NM
NAND gate ND via OS transistor NT173
171 is connected to the other input terminal. And NM
The gate of the OS transistor NT171 is connected to the supply line of the signal VF00, and the gate of the NMOS transistor NT172 is connected to the supply line of the signal VF01.
The gate of the S transistor NT173 is connected to the supply line of the signal VF10. Further, the input / output terminal IOn +
An NMOS transistor NT174 is connected between 1N and the Q output terminal of the flip-flop FF171, and an NMOS transistor NT175 is connected between the input / output terminal ION and the Q output terminal of the flip-flop FF172. Then, the NMOS transistors NT174 and NT175
Are commonly connected to a signal ST supply line. Note that the signal ST is given as a pulse signal that takes a high level in accordance with the column address at the time of Bay-Fiy reading after writing.

Each of the adders 18a and 18b has a similar configuration, and transfers the 2 ⁿ value read data read by the write / read control circuits 12a and 12b to the bus lines IOi and IOi.
The data is converted into n-bit data by adding the input 2 ⁿ value read data and the previous read data stored in the page buffer 15, and the input / output line is input to the page buffer 15. IO0N, I
Store (write back) via O1N.

FIG. 4 is a circuit diagram showing a specific configuration example of the adders 18a and 18b. The adder circuit 18a (18
b) shows an NMOS transistor and P
Transfer gates TM181, TM182, TM183, TM184 connecting sources and drains of MOS transistors
, Inverters IV181 and IV182, and latch circuits Q181 and Q182 formed by cross-connecting the inputs and outputs of the inverters.
NMOS transistors NT181 and NT182, exclusive OR gate EX181, and two-input NAND gate NA181
, NA182.

One input / output terminal of each of transfer gates TM181 and TM182 is connected to input / output line IOnN, and one input / output terminal of transfer gates TM183 and TM184 is connected to input / output line IOn + 1N. The other input / output terminal of the transfer gate TM181 is connected to the first storage node N181a of the latch circuit Q181, and the other input / output terminal of the transfer gate TM182 is connected to the output terminal of the exclusive OR gate EX181. The other input / output terminal of transfer gate TM183 is connected to first storage node N182a of latch circuit Q182, and the other input / output terminal of transfer gate TM184 is connected to the output terminal of NAND gate NA182. The gates of the PMOS transistors forming the transfer gates TM181 and TM183, and the gates of the NMOS transistors forming the transfer gates TM182 and TM184 are connected to a supply line for the signal Vst. The input terminal of the inverter IV181 is connected to the supply line of the signal Vst, and the output terminal is connected to the gates of the NMOS transistors forming the transfer gates TM181 and TM183 and the gates of the PMOS transistors forming the transfer gates TM182 and TM184.

First storage node N18 of latch circuit Q181
1a is grounded via the NMOS transistor NT181,
The first storage node N182a of the latch circuit Q182 is an NMOS
It is grounded via a transistor NT182. The gates of the NMOS transistors NT181 and NT182 are connected to a supply line for the signal RD11. The second storage node N181b of the latch circuit Q181 is connected to the inverter IV18.
The output terminal of the inverter 182 is connected to one input terminal of the exclusive OR gate EX181 and one input terminal of the NAND gate NA181. The second storage node N182b of the latch circuit Q182 is connected to one input terminal of the NAND gate NA182.
Exclusive OR gate EX181 and NAND gate NA18
The other input terminal of 1 is connected to bus lines IO01BUS and IO23BUS via an inverter IV11. The output terminal of the NAND gate NA181 is connected to the other input terminal of the NAND gate NA182.

In the adder circuit 18a, the signal RD11 is set to the high level only at the time of reading the first step, whereby the first storage nodes N181a and N182a of the latch circuits Q181 and Q182 are forcibly set to the ground level. And the second storage nodes N181b and N182b are held at a high level. Further, the signal Vst is supplied as a pulse signal which is held at a high level for a predetermined time in correspondence with the timing at which the column selection signals Y0 to Yn-1 are set to a high level at the time of reading of each step.

Next, the read and write operations of the above configuration will be described with reference to the timing chart of FIG. In FIG. 5, (a) is a timing chart during a read operation, and (b) is a timing chart during a verify read operation during a write operation.

First, the read operation will be described. First, the reset signal RST and the signals PGM21 and PGM22 are set to a high level. As a result, the NMOS transistors NT21 to NT24 become conductive, and the latch circuit Q
First storage nodes N21a and N22a of transistors 21 and Q22 are pulled to the ground level. As a result, the latch circuit Q2
1, Q22 are cleared. Next, the word line voltage is set to 2.
Reading is performed at 4V. If the threshold voltage Vth is higher than the word line voltage (2.4 V), the cell current does not flow, so that the bit line voltage holds the precharge voltage and high is sensed. On the other hand, if the threshold voltage Vth is lower than the word line voltage (2.4 V), the cell current flows to lower the bit line voltage and sense low. Then, when the reading is determined, the column addresses are sequentially changed, and the outputs of the latch circuits Q21 and Q22 are stored in the page buffer 15 via the adders 18a and 18b.

In terms of timing, while the column selection signal Yi is at the high level, the latch circuit Q21, Q22 outputs an inverted signal (N) obtained by inverting the read result by the inverter IV11.
In the case of an AND cell, inversion is necessary), but the page buffer 1
5, the read results up to the previous time are input to the adders 18a and 18b respectively when the signal Vst is at a low level.
Is added. In the case of three-step reading, at the time of the first reading, the signal RD11 is set to the high level, so that the reading result up to the previous time is regarded as "00" and the addition is performed. Then, the addition result is stored (written back) in the page buffer 15 while the signal Vst is set to the high level.

Next, reading is performed at a word line voltage of 1.2 V, and the result is added to the data of the page buffer 15 and stored in the page buffer 15 again. Finally, reading is performed at a word line voltage of 0 V, and the data is similarly added to the data in the page buffer 15 and stored in the page buffer 15 again.

When the cell data is "00", high (logic "1") is read to the latch circuits Q21 and Q22 all three times, and inverted signals (low level) are input to the adders 18a and 18b three times. Is done. Then, the data of the cell is determined to be “00” from the addition result. Cell data is "0"
In the case of "1", the inverted signals of the high level only at the first two times and the low level at the last one are added to the adders 18a and 18b.
And the cell data is determined to be “01” from the addition result. The other two cell data “10”, “11”
The same applies to the case of.

With the above operation, 2-bit data is stored in the page buffer. Thereafter, by sequentially changing the column address, high-speed serial reading can be performed. Note that in the above read operation, FIG.
The time required for storing the read data in the page buffer via the adder circuit is longer and the first access time is longer than in the case of the conventional multi-valued NAND shown in FIG.
There is no problem if the serial access speed is high to some extent.

Next, the write operation will be described. Here, the verify operation after writing will be mainly described.

First, the write data input from the input terminals IO0 to IO3 and passed through the input buffers 13-0 to 13-3 are temporarily stored in a page buffer, and the first data is stored in the write / read control circuits 12a and 12b. Latch circuit Q
21 and 22. At this time, the AND gate 16
a, 16b, when there is “0” in the write data IOn + 1, IOn, that is, when the write data is IOn +
When 1, IOn = (0, 0), (0, 1), (1, 0), a low (logic “0”) is set in the latch circuit, and data is written. The write data is IOn + 1,
When IOn = (1, 1), high (logic "1") is set in the latch circuit, and no data is written.

After writing, first, the word line voltage VWL0
A verify is performed at 0, and the read result is transferred to the discriminating circuits 17a and 17b, and compared with the write data. Here, if a cell current flows, a high (logic "1") appears in the latch circuit. Data of the same address is read from the page buffer 15 to the discriminating circuits 17a and 17b, and the signal VF00 is set to a high level. As a result, the NMOS transistor NT171 becomes conductive, and the decoded value is input to the NAND gate ND171. Here, the write data is IOn + 1, IOn =
In the case of (0,0), the decoded value of the write data “0”
"0" becomes high (logic "1") and the NAND gate ND17
Entered into 1.

When the writing is sufficient, the output of the latch circuit is at the high level, and the output of the NAND gate ND171 is at the low level. As a result, the judgment circuit 17a (17)
The flip-flops FF171 and FF172 of b) are preset. Then, this data is written back to the page buffer. Therefore, at the time of rewriting, the write data becomes IOn + 1, IOn = (1, 1). as a result,
At the time of subsequent rewriting, the write / read control circuits 12a, 12
High (logic “1”) is set in the latch circuit b,
No further writing is done.

On the other hand, when the writing is insufficient, the output of the latch circuit is at the low level, and the NAND gate ND
The output of 171 becomes high level, and the discrimination circuit 17a (17
The flip-flops FF171 and FF172 of b) are not preset. Then, this data is stored in the page buffer 15.
Is written back to Therefore, the write data at the time of rewriting is IOn + 1, IOn = (0, 0). As a result, writing is performed at the time of rewriting.

At the time of verifying with word line voltage VWL00, write data is IOn + 1, IOn = (0, 0)
In other cases, the decode value “00” of the write data is low (logic “0”). Therefore, the NAND gate ND
The output of 171 is always at the high level, and the write data is not preset. That is, there is no change in the write data.

Similarly, the word line voltages VWL01, VWL
The verification is also performed in WL10, and the determination circuit 17a (1
After the comparison in 7b), the rewrite data is stored in the page buffer 1
5 is stored. The write data is IOn + 1, I
When On = (0, 1), the level is IOn + 1, IOn = (1, 1) → IOn + 1, IO in the previous write.
Even if n = (1, 0), IOn + 1, IOn =
Since the level does not reach the level of (0, 1), the write data is left as it is, and writing is performed at the time of rewriting. Only when the write level becomes IOn + 1, IOn = (0, 1), flip-flops FF171 and FF172 become available.
Is preset, and the writing ends. in this way,
Since writing is continued in each cell until the level reaches the level corresponding to the write data, the power application method and the ISPP writing method can be applied to the writing timing. Writing is performed as described above.

As described above, according to the present embodiment, in a multi-level (four-level) NAND flash, the n-bit write data stored in the page buffer 15 has a predetermined logic level (logic "0"). And AND gates 16a and 16b, which convert low-level data if there is no bit data, and high-level data if there is no logical "0" bit data, and a latch circuit. The write / read control circuits 12a and 12b for latching the output high or low data and outputting the data to the selected bit line when the latch data is at a high level to perform writing, The read data is compared with the corresponding write data stored in the page buffer 15 to determine whether the write is sufficient. The determination circuit 17a, 17b which converts the write data into non-write data having no logic "0" and writes it back to the page buffer 15 when sufficient, and AND gates 16a, 16b are provided. , The number of verify operations and the number of charge / discharge operations of the decoder can be reduced, and the total write time can be reduced.

The write / read control circuits 12a, 12b
Has the same configuration as the conventional binary (“0” and “1”) circuit configuration, and instead has a page buffer 15. At the time of writing, the priority decoders 16 a and 16 b convert n bits → 2 ⁿ values. Then, writing is performed one value at a time, and at the time of reading, reading is performed one value at a time by changing the word line voltage, and the read results are added to adders (2 ⁿ value → n bit conversion) 18a and 18b. Since the data is stored in the page buffer 15 through the write / write operation, the write / write operation is performed for each bit line or each bit line pair.
The read control circuit may have a conventional configuration, and a conventional method can be used for the data conversion method. In the conventional circuit, a control circuit for converting n bits ← → 2 ⁿ , which had to be arranged for each bit line pair, may be provided for the IO in the page buffer 15 portion. There is no restriction on layout space. However, in the case of four values, "page buffer + write latch" is required as a data latch, and a latch 1.5 times as large as the circuit of FIG. 16 is required. However, considering that it is not necessary to provide an n-bit .fwdarw.2 ^n- value conversion circuit for each bit line, the increase in area is small compared to the conventional circuit. In addition, although the time until the first access of the data transfer from the page buffer to the write / read latch becomes long, there is no problem if the serial output is fast as the performance required for the multi-level flash memory.

A transistor (Tr) arranged at the pitch of the bit line pair of the conventional circuit (FIG. 16) and the circuit of FIG.
Comparing the numbers (excluding the transistors for the column decoder and the decoupling transistor), the conventional circuit has 23 Tr / bit line pairs, whereas the present circuit (FIG. 2) has 18 Tr / bit line pairs. As can be seen from the results, the present invention has an advantage that the layout is facilitated.

In the above-described embodiment, an example has been described in which a latch circuit is provided for each bit line in the write / read control circuit. For example, as shown in FIG. 6, one latch circuit is provided for each bit line pair. It is also possible to configure so as to provide Q21.

This write / read control circuit 12c has an NMO
It is composed of S transistors NT31 to NT39, a PMOS transistor PT31, and a latch circuit Q31 which connects inputs and outputs of the inverter.

The NMOS transistor NT31 is connected between the supply line and the bit line BLR, which become the high voltage V _PP at the time of writing and the current voltage Vcc at the time of reading. The gate takes the V _PP level and the ground level at the time of writing, and at the time of reading. It is connected to the supply line of the inhibit signal IHB1 having the ground level. NMOS transistor NT32
Is the high voltage V _PP during writing and the power supply voltage V during reading.
The gate is connected between the supply line of cc and the bit line BLL, and the gate is connected to the supply line of the inhibit signal IHB2 which takes the ground level at the time of writing and takes the ground level at the time of reading. The bit lines BLR and BLL are connected to NMOS transistors NT33 and NT34, respectively, and are connected between the NMOS transistors NT33 and NT34 and the bus line IO01BUS.
35 and NT39 are connected in series. The gate of the NMOS transistor NT33 is connected to a supply line for a signal Aj that takes the V _PP level and the ground level during writing, and takes the Vcc level and the ground level during reading.
The gate of the MOS transistor NT34 takes the V _PP level and the ground level at the time of writing complementarily with the signal Aj,
At the time of reading, a signal which takes Vcc level and ground level /
Aj is connected to the supply line.

NMOS transistors NT33, NT34
Is connected to the NMOS transistor NT35 with the NMOS transistor NT35.
Grounded via transistor NT36 and P
Drain of MOS transistor PT31 and NMO
It is connected to the gate of S transistor NT37. The gate of the NMOS transistor NT36 is connected to the supply line of the reset signal RST, the source of the PMOS transistor PT31 is connected to the supply line of the power supply voltage V _CC , and the gate of the PMOS transistor PT31 has the V _CC level and the ground level at the time of reading. It was taken, which is connected to the supply line of the signal Vref taking V _pp level at the time of writing.

First storage node N3 of latch circuit Q31
1a is connected to a connection point between the NMOS transistors NT35 and NT39, and the second storage node N31b is grounded via NMOS transistors NT37 and NT38 connected in series. And the NMOS transistor N
The gate of T38 is connected to the supply line of the latch signal φLTC, and the NMOS transistor N as a column gate is connected.
The gate of T39 is connected to the signal Y supply line.

The read and write operations in the nonvolatile semiconductor memory device having the write / read control circuit 12c are basically performed in the same manner as the above-described operations. The difference is that there is only one latch circuit Q31, so that the connection between the bit lines BLR and BLL and the latch circuit 31 is
The control is performed so as to be selectively performed by the transistors NT33 and NT34. The bit line side of the non-selection is holding the inhibit signal IHB1 or IHB2 V _PP level when writing is activated, the Vcc level at the time of reading.

As described above, by providing one latch circuit Q31 for each bit line pair, the number of transistors becomes 13 Tr / bit line pairs, and the number of transistors can be further reduced as compared with the circuit of FIG. There is an advantage that development into values, 16 values, and the like is further facilitated.

In this embodiment, the NAND flash memory has been described as an example. However, it goes without saying that the present invention can be applied to a DINOR flash memory in which bit lines are hierarchized. In this case, the connection between the bus line and the adder circuits 18a and 18b is established by the inverter IV shown in FIG.
A buffer is used instead of 11. That is, a configuration is adopted in which the read data output to the bus line is input to the adder circuit without inversion without being inverted. The other configuration and operation and effect are the same as those of the above-described NAND type.

Next, in the multi-valued nonvolatile semiconductor memory device, there are no memory cells that reach the write verify threshold value (Vth), and four page program forms capable of suppressing variations in the write Vth distribution will be described. This will be described with reference to FIG.

First page program form First, from a low write Vth level to a high write Vt level
A page program form written in order toward the h level will be described with reference to FIGS. In this mode, the lowest Vth level “11” is set to the erased state, and once “10”, “01”, “
00 ”(1st“ 10 ”Program, 1st“ 01 ”P
rogram, 1st "00" Program). Then, with respect to the write Vth level lower than the verify Vth in the first program, writing is performed in order from a lower write Vth level to a higher write Vth level. In particular"
Write in the order of “10”, “01” (2nd “10” Program,
2nd "01" Program). The second "10", "01"
Since part of the Vth distribution of “00” is lower than the verify Vth by writing, writing of “00” is also added at the end (2nd “00” Program).

By performing the second program after the above-described first program, as shown in FIG. 8, there are no memory cells that have not reached the write verify Vth, and the variation in the write Vth distribution can be suppressed.

Second Page Program Form Next, a second page program form will be described with reference to FIGS. 9 and 10. FIG. In this embodiment, the lowest V
The "11" of the th level is set to the erased state, and is temporarily written in the page program in the order of "00", "01", "10" (1st "00" Program, 1st "01" Program, 1st "10" P
rogram). For the write Vth level lower than the verify Vth in the first program, a lower write V
Writing is performed in order from the th level to the higher write Vth level. Specifically, writing is performed in the order of “01” and “00” (2nd “01” Program, 2nd “00” Program).

Also in the case of the second embodiment, as shown in FIG. 10, there is no memory cell which does not reach the write verify Vth, and the variation of the write Vth distribution can be suppressed.

Third Page Program Form Next, a third page program form will be described with reference to FIG. 11 and FIG. In this embodiment, the highest Vth level “00” is set to the erased state, and writing is performed in order from the lower write Vth level to the higher write Vth level in one page program. Specifically, writing is performed in the order of “11”, “10”, “01” (“11”
Program, "10" Program, "01" Program).

Also in the case of the third embodiment, as shown in FIG. 12, there is no memory cell which does not reach the write verify Vth, and the variation of the write Vth distribution can be suppressed.

Fourth Page Program Form Next, a third page program form will be described with reference to FIGS. In this embodiment, the highest Vth level “00” is set to the erased state, and writing is performed in order from the higher write Vth level to the lower write Vth level in one page program. Specifically, writing is performed in the order of “01”, “10”, “11” (“01”
Program, "10" Program, "11" Program). Write Vth lower than verify Vth in the first program
With respect to the level, writing is performed in order from a lower write Vth level to a higher write Vth level. Specifically, write in the order of “01” and “10” (2nd “01” Progr
am, 2nd "10" Program).

Also in the case of the fourth embodiment, as shown by the broken line in FIG. 14, there is no memory cell that does not reach the write verify Vth, and the variation in the write Vth distribution can be suppressed.

[0081]

As described above, according to the present invention,
The number of times of verification and the number of times of charging and discharging of the decoder can be reduced, and the total writing time can be shortened.
Further, since only a write / read control circuit including a latch circuit for one bit needs to be arranged for each bit line or each bit line pair, the layout is easy, and development into eight values, sixteen values, and the like is easy. It is. Further, the conventional binary method can be used as it is as the data conversion method, and the number of conversion circuits for converting n bits ← → 2n may be the number of IOs.

After writing in page units,
By performing the verify write again and writing the data in order from the lower threshold level to the higher threshold level, memory cells that do not reach the write verify threshold are eliminated, and the variation in the write threshold distribution can be suppressed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a nonvolatile semiconductor memory device according to the present invention.

FIG. 2 is a circuit diagram showing a specific configuration of a memory cell array and a write / read control circuit in FIG. 1;

FIG. 3 is a circuit diagram showing a specific configuration example of a determination circuit according to the present invention.

FIG. 4 is a circuit diagram showing a specific configuration example of an addition circuit according to the present invention.

FIGS. 5A and 5B are timing charts for explaining the operation of the nonvolatile semiconductor memory device according to the present invention, wherein FIG. 5A is a timing chart for explaining a read operation, and FIG. It is a timing chart for performing.

FIG. 6 is a circuit diagram showing another configuration example of the write / read control circuit according to the present invention.

FIG. 7 is a flowchart for explaining a first data program mode;

FIG. 8 is a diagram showing a relationship between a threshold voltage Vth level and data distribution in a first data programming mode.

FIG. 9 is a flowchart for explaining a second data program mode;

FIG. 10 is a diagram showing a relationship between a threshold voltage Vth level and data distribution in a second data programming mode.

FIG. 11 is a flowchart for explaining a third data program mode;

FIG. 12 is a diagram showing a relationship between a threshold voltage Vth level and data distribution in a third data programming mode.

FIG. 13 is a flowchart for explaining a fourth data program mode;

FIG. 14 is a diagram showing a relationship between a threshold voltage Vth level and data distribution in a fourth data programming mode.

FIG. 15 is a diagram showing the relationship between the threshold voltage Vth level and the distribution of data in the case where 4-bit data composed of 2 bits is recorded in one memory transistor in a NAND storage device.

FIG. 16 is a circuit diagram for describing a conventional write / read control circuit.

17A and 17B are timing charts for explaining the operation of the circuit of FIG. 16, wherein FIG. 17A is a timing chart for explaining a read operation, and FIG. 17B is a timing chart for explaining a write operation;

18A and 18B are diagrams for explaining the concept of the writing method in the conventional device and the device according to the present invention, wherein FIG. 18A is the concept of the writing method in the conventional device, and FIG. It is a figure showing the concept of.

FIG. 19 is a diagram for explaining a relationship between a writing time and a threshold voltage of a DINOR type flash memory.

FIG. 20 is a diagram for explaining a writing method.

[Explanation of symbols]

10 nonvolatile semiconductor memory device, 11a, 11b memory cell array, 12a, 12b, 12c write / read control circuit, 13-0 to 13-3 input buffer, 14-0
~ 14-3 ... output buffer, 15 ... page buffer, 1
6a, 16b: anand gate, 17a, 17b: discriminating circuit, 18a, 18b: adding circuit, 19a, 19b ... N
MOS transistor.

Claims (13)

[Claims] An amount of charge stored in a charge storage unit changes according to a voltage applied to a word line and a bit line, and a threshold voltage changes according to the change. It has a memory cell for storing value data, and writes multi-valued data of three or more values into the memory cell in page units, performs verification after programming to determine whether the programming is sufficient, and rewrites if insufficient. A non-volatile semiconductor memory device that performs writing when there is bit data of a predetermined logic level that requires a threshold voltage transition in n-bit write data at the time of writing, and as a result of verification, the write becomes sufficient. Non-volatile semiconductor memory having a write circuit for sequentially converting data for a cell into non-write data having no predetermined logic level to inhibit the rewrite Location. 2. The method according to claim 1, wherein the amount of charge stored in the charge storage unit changes according to the voltage applied to the word line and the bit line, and the threshold voltage changes according to the change. It has a memory cell for storing value data, and writes multi-valued data of three or more values into the memory cell in page units, performs verification after programming to determine whether the programming is sufficient, and rewrites if insufficient. A page buffer for storing n-bit write data; and a predetermined logic level at which a threshold voltage must be shifted to the n-bit write data stored in the page buffer during writing. A conversion circuit that converts the bit data into the first data if the bit data of the predetermined logic level exists, and converts the data into the second data if there is no bit data of the predetermined logic level. A write control circuit for latching the first or second data output from the conversion circuit and outputting the data to a selected bit line to write when the latched data is the first data At the time of verification, the read data is compared with the corresponding write data stored in the page buffer to determine whether or not the write is sufficient. A nonvolatile semiconductor memory device having a determination circuit for converting the data into non-write data having no predetermined logic level and writing the converted data back into the page buffer; 3. The nonvolatile semiconductor memory device according to claim 2, wherein said write control circuit is provided with one bit of said latch circuit corresponding to each bit line. 4. The nonvolatile semiconductor memory device according to claim 2, wherein said write control circuit includes one bit of said latch circuit corresponding to each bit line pair. 5. The amount of charge stored in a charge storage unit changes according to a voltage applied to a word line and a bit line, and the threshold voltage changes according to the change. It has a memory cell that stores value data and outputs data based on a word line voltage and a stored charge amount to a bit line at the time of reading. A non-volatile semiconductor memory device that verifies whether or not writing is sufficient after writing, and performs rewriting if insufficient, stores n-bit write data at the time of writing, and stores the stored data at the time of reading. The threshold voltage is shifted to the page buffer that outputs as read data and the n-bit write data stored in the page buffer during writing. A first conversion circuit that converts bit data of a predetermined logic level that needs to be converted into first data if there is bit data of the predetermined logic level, and converts the bit data into second data if there is no bit data of the predetermined logic level; Latching the first or second data output from the first conversion circuit, and when the latched data is the first data, outputting the data to a selected bit line to perform writing and reading. Sometimes, the word line voltage is sequentially changed, and the write data to the selected memory cell is output to the bit line, and the write / read control circuit sequentially outputs one value at a time. It is determined whether the writing is sufficient by comparing with the corresponding write data stored in the page buffer. A discrimination circuit that converts the data into non-write data having no level and writes the data back into the page buffer; and, upon reading, sequentially receives 2 ⁿ -value read data output from the write / read control circuit and converts the data into n-bit data. And a second conversion circuit for converting the data and storing the converted data in the page buffer. 6. The nonvolatile semiconductor memory device according to claim 5, wherein said write / read control circuit is provided with one bit of said latch circuit corresponding to each bit line. 7. The nonvolatile semiconductor memory device according to claim 5, wherein said write / read control circuit includes one bit of said latch circuit corresponding to each bit line pair. 8. The second conversion circuit, when inputting the first read data, adds the preset initial data and the input read data and stores the sum in the page buffer. 6. The nonvolatile semiconductor memory device according to claim 5, wherein at the time of inputting the read data, the previous read data stored in the page buffer and the input read data are added and stored in the page buffer. 9. The write / read control circuit reads data by sequentially changing a word line voltage, and sequentially transfers data to the second conversion circuit in accordance with a column address when data is determined in each read. When the first read data is input, the second conversion circuit adds the preset initial data and the input read data, stores the sum in the page buffer, and reads the second and subsequent read data. At the time of data input, the previous read data stored in the page buffer and the input read data are added and stored in the page buffer. The page buffer stores the data stored when all the data in the page is determined. 6. The non-volatile semiconductor memory device according to claim 5, wherein data is sequentially output as read data according to a change in a column address. 10. The nonvolatile semiconductor memory device according to claim 1, wherein verify writing is performed again after writing in page units. 11. The nonvolatile semiconductor memory device according to claim 10, wherein writing is performed in order from a lower threshold level to a higher threshold level. 12. The nonvolatile semiconductor memory device according to claim 11, wherein the lowest threshold level is set to an erased state. 13. The nonvolatile semiconductor memory device according to claim 11, wherein the highest threshold level is set to an erased state, and writing is performed in order from a lower threshold level to a higher threshold level.