KR20090020467A - Method of operating a non volatile memory device - Google Patents

Abstract

An operating method of a non-volatile memory device is provided to invert and latch a state in a sensing node while data are programmed and verified in a memory cell of a flash memory device having a multi-level cell. A bit line(BLe) is pre-charged according to a programming degree of a selected memory cell by inputting a positive voltage through a common source line of cell strings of memory cells. Data are stored in a first latch of a page buffer according to a voltage level of a sensing node(SO) which is changed according to a voltage level of a bit line. The data stored in the first latch are transmitted to a second latch through the sensing node.

Description

Method of operating a non volatile memory device

The present invention relates to an operation of a nonvolatile memory device, and more particularly, to a method of operating a nonvolatile memory device capable of inverting and storing data of a sensing node.

Well known NAND flash memory devices include memory cell arrays, row decoders, and page buffers. The memory cell array includes a plurality of word lines and columns defined along rows and a plurality of bit lines extending along columns and a plurality of cell strings corresponding to the bit lines, respectively.

One side of the memory cell array includes a row decoder connected to string selection lines, word lines, and a common source line, and a page buffer connected to a plurality of bit lines is located on the other side.

Recently, in order to further improve the density of such flash memories, studies on multiple bit cells capable of storing a plurality of data in one memory cell have been actively conducted. This type of memory cell is referred to as a multi level cell (hereinafter referred to as MLC). In contrast, a single bit memory cell is referred to as a single level cell (hereinafter referred to as SLC).

1A is a cell distribution diagram of an SLC memory device.

Referring to FIG. 1A, the SLC has two cell states 101, 102 of erase or program, have a distribution, and basically the cells of the erase state 101 move to the program cell state 102 according to the program operation ( S110). As shown in FIG. 1A, the SLC requires one program operation, and the verification operation may be completed by performing one verification on the verification voltage PV1.

1B is a cell distribution diagram of an MLC memory device.

Referring to FIG. 1B, a cell distribution diagram of an MLC capable of storing two bits of data is shown. Cell states 111 through 114 having data storage states of [11], [10], [00], and [01], respectively. ) Their distribution corresponds to the threshold voltage distributions of the MLC, respectively.

The program to each cell state first performs a Least Significant Bit (LSB) program to program [10] state 112 (S121), and the MSB (Most Significant Bit) program selects [10] state 112. Program to the state (S131), or [11] state 111 to the [01] state 114 (S132).

After the program, each verification is performed. In general, as the number of bits of data that can be stored increases, the cell distribution increases, thus increasing the number of verifications.

As mentioned above, SLC performs one-time verification for one pulse. However, in case of an MLC capable of storing two bits of data, as shown in FIG. In this way, a 3-bit MLC requires three verifications for a program pulse and a 4-bit MLC requires eight verifications.

The number of such program verifications increases as the number of bits that can be stored in the memory cell increases, thereby increasing the time required for program verification.

Accordingly, an object of the present invention is to provide a method of operating a nonvolatile memory device, which inverts and latches a state of a sensing node when programming and verifying data in a memory cell of a flash memory device having a multi-level cell. It is.

Method of operating a nonvolatile memory device according to another aspect of the present invention,

Inputting a positive voltage through a common source line of the cell strings of the memory cells to precharge the bit line according to a program degree of the selected memory cell; Storing data according to a voltage level of a sensing node changed according to the voltage level of the bit line, into a first latch of a page buffer; And transferring data stored in the first latch to the second latch through the sensing node.

The sensing node is changed to a low level when the memory cell is turned off with respect to a voltage applied to a word line to which the selected memory cell is connected.

The precharging of the bit line may include applying a first voltage to a word line to which the selected memory cell is connected, and applying a pass voltage to an unselected word line so that each bit line is connected to the selected memory cell. The voltage is changed according to the program state.

And storing data according to the voltage level of the sensing node in the first latch is characterized in that the second latch is in a disabled state and data opposite to a program state of the selected word line is stored in the first latch. do.

The transferring of data stored in the first latch to the second latch may include enabling the second latch, and then transferring the data stored in the first latch to the second latch through the sensing node to the selected memory. The data according to the program state of the cell is to be stored in the second latch.

Method of operating a nonvolatile memory device according to another aspect of the present invention,

Inputting a positive voltage through a common source line of the cell strings of the memory cells to precharge the bit line according to the program degree of the memory cell where the program is performed, and changing the bit line voltage according to the data state stored in the memory cell ; Storing data according to the voltage level of the bit line into a first latch of a page buffer; And after transferring the data stored in the first latch to the second latch, outputting a verification signal according to the data state transferred to the second latch.

When the memory cell is programmed, the sensing node is changed to a low level.

The precharging of the bit line may include: performing a program on multi-level cells of the memory device; Inputting a positive voltage to a common source line commonly connected to a cell string to which the multi-level cells are connected for program verification; And precharging each bit line by applying a first voltage to a selected word line among a plurality of word lines connected to the cell strings of the multi-level cells and applying a pass voltage to an unselected word line. It comprises the step of.

The sensing node connected to the precharged bit line may be in a precharge state at a high level.

The first and second latches of the page buffer may be initialized before the data of the sensing node is latched.

Storing data in the first latch according to the voltage level of the bit line may include enabling the second latch and storing data in the first latch as data having a logic level opposite to the voltage level of the bit line. It is characterized by.

Delivering the data stored in the first latch to the second latch, and enabling the second latch, characterized in that for transferring the data stored in the first latch to the second latch through the sensing node. .

As described above, in the method of operating a nonvolatile memory device according to the present invention, after inputting a power supply voltage through a common source line to precharge the bit line and then reading data, the sensing node is changed without changing the page buffer circuit. The data can be inverted and latched in the page buffer.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. It is provided for complete information.

2A is a block diagram illustrating a structure of an MLC memory device according to an embodiment of the present invention.

Referring to FIG. 2A, a multi level cell (MLC) memory device 200 according to an embodiment of the present invention may include a memory cell array 210 including MLCs and a data program in an MLC of the memory cell array 210. A page buffer unit 220 including a plurality of page buffers for performing verification and reading operations, a Y decoder unit 230 for selecting the plurality of page buffers by an input address, and the memory cell by an input address An X decoder 240 selecting a word line of the array 210 and a controller 250 for controlling the operation of the MLC memory device 200 are included.

The memory cell array 210 includes word lines and MLC arrays divided into bit lines, and the page buffer unit 220 is connected to a pair of bit lines of the bit lines of the memory cell array 210 to be connected to data. And one or more page buffer circuits to allow for programming, verifying, and reading of.

The Y decoder unit 230 and the X decoder unit 240 connect MLCs for program or read among the MLCs of the memory cell array 210 under the control of the controller 250.

The controller 250 performs voltage level control, operation signal control, and the like for the program, verify or read operation and the erase operation of the MLC memory device 200.

The memory cell array 210 includes a plurality of bit line pairs as follows.

FIG. 2B is a partial circuit diagram of the memory cell array of FIG. 2A.

Referring to FIG. 2B, a pair of bit lines of the memory cell array 210 includes an even bit line BLe and an odd bit line BLO, and a cell string is connected to each bit line.

The bit lines of the memory cell array 210 are connected to cell strings in which memory cells are connected in series. The cell strings are connected between a drain select transistor (DST) and a source select transistor (SST). A plurality of memory cells are connected in series.

The gates of the drain select transistors of the cell strings are connected in common by a drain select line (DSL), and the gates of the source select transistors are connected by a source select line (SSL).

The source lines of the source select transistors are connected to a common source line SL. The common source line is generally connected to a ground node, and the power supply voltage VCC is input during the verify operation for performing the program.

For example, when programming and verifying the memory cell C connected to the even bit line BLe, a set voltage is applied to the memory cell C selected for the program, and a pass voltage is applied to the remaining cells. do. The voltage applied to the selected memory cell is a voltage that can be turned on even when the memory cell is programmed to have the highest threshold voltage.

When the power supply voltage VCC is input to the common source line SL, the even bit line BLe is precharged according to a program degree of the selected memory cell, that is, a threshold voltage. If the threshold voltage of the selected memory cell is low, a high voltage will be precharged in the even bit line BLe, and if the threshold voltage of the selected memory cell is high, a low voltage will be precharged in the even bit line BLe. That is, the voltage level obtained by subtracting the threshold voltage of the selected memory cell from the power supply voltage VCC input through the common source line SL is precharged to the even bit line BLe.

In this case, the power supply voltage VCC is also input to the odd bit line BLO in order to prevent the odd bit line BLO from being affected by the odd bit line BLO.

As described above, when the power supply voltage VCC is input through the common source line SL to precharge the even bit line BLe, the precharge voltage of the even bit line BLe is inversely proportional to the threshold voltage of the memory cell. do.

Therefore, if the memory cell C is programmed to have a high threshold voltage, the voltage level transferred to the sensing node SO has a logic level of almost '0', and if the memory cell C is an erase cell, the sensing sensing node The voltage level delivered to SO will have a logic level of '1'. The change in the voltage level of the sensing node SO is opposite to that of the conventional page buffer circuit. Therefore, it is necessary to invert the value of the sensing node SO which is changed to the opposite level of the existing program verification and store it in the latch.

The above verification method is equally applied to reading data. Accordingly, even when data reading is performed, the data programmed in the memory cell can be read and output normally only by inverting and latching the value of the sensing node SO.

Accordingly, the method of inverting and latching the voltage level of the sensing node SO without changing a circuit in the following page buffer circuit is as follows.

FIG. 2C is a detailed circuit diagram of the page buffer circuit of FIG. 2A.

Referring to FIG. 2C, the page buffer circuit according to an embodiment of the present invention selects an even bit line Ble or an odd bit line BLO and senses a precharge voltage level of the selected bit line to sense the sensing node SO. First and second bit line selection units 221 for connecting to the first and second lines connected to the sensing node SO to temporarily store data to be programmed in the memory cell or to read and store data programmed in the memory cell. And a second latch unit 22 and 223 and a data inverting unit 224 connected to the sensing node SO to invert data read from the memory cell and transfer the inverted data to the second latch unit 223. And a first PMOS transistor P1 for precharging the sensing node SO. The first PMOS transistor P1 is operated by the precharge control signal PRECHb.

The bit line selector 221 includes first to fourth NMOS transistors N1 to N4.

The first latch unit 222 includes fifth to ninth NMOS transistors N5 to N9, first and second inverters IN1 and IN2, and a second PMOS transistor P2. The second latch unit 223 includes tenth to fourteenth NMOS transistors N10 to N14 and third to fifth inverters IN3 to IN5. The data inverting unit 224 includes the fifteenth to seventeenth NMOS transistors N15 to N17.

The first NMOS transistor N1 of the bit line selector 221 is connected between the even bit line BLe and the sensing node SO, and the bit line select signal BSLe is provided at a gate of the first NMOS transistor N1. Is input. The second NMOS transistor N2 is connected between the odd bit line BLo and the sensing node SO, and the bit line selection signal BSLo is input to the gate of the second NMOS transistor N2.

The third and fourth NMOS transistors N3 and N4 are connected between the even and odd bit lines BLe and BLo, and a power signal is connected to the contact nodes of the third NMOS transistor N3 and the fourth NMOS transistor N4. VIRPWR) is input. The discharge control signals DISCHe and DISCHo are input to the gates of the third and fourth NMOS transistors N3 and N4, respectively.

The fifth NMOS transistor N5 of the first latch unit 222 is connected between the sensing node SO and the node QB, and the first program control signal PGM is applied to the gate of the fifth NMOS transistor N5. Is entered.

The sixth and seventh NMOS transistors N6 and N7 are connected in series between the node QBb and the ground node. The sensing node SO is connected to the gate of the sixth NMOS transistor N6, and the control signal MLCH is input to the gate of the seventh NMOS transistor N7.

The eighth NMOS transistor N8 is connected between the node QB and the ground node, and the reset control signal MRST is input to the gate of the eighth NMOS transistor N8.

In addition, the first and second inverters IN1 and IN2 are connected between the node QBb and the node QB to form a first latch L1. The second PMOS transistor P2 outputs the power supply voltage as the verification signal nWDO according to the voltage level of the node QB.

The ninth NMOS transistor N9 is connected between the node QB and the node YA, and the data output control signal PBDO is input to the gate of the ninth NMOS transistor N9.

The tenth NMOS transistor N10 of the second latch unit 223 is connected between the sensing node SO and the node YA, and the control signal CELLIV is input to the gate of the tenth NMOS transistor N10.

The eleventh NMOS transistor N11 is connected between the sensing node SO and the node K, and the second program control signal DPGM is input to the gate of the eleventh NMOS transistor N11. The third inverter IN3 is connected between the node K and the node QAb and inverts the logic level of the node QAb to output to the node K.

The fourth and fifth inverters IN4 and IN5 are connected between the node QA and the node QAb and constitute the second latch L2. The twelfth NMOS transistor N12 is connected between the node QA and the ground node, and the setting control signal CSET is input to the gate of the twelfth NMOS transistor N12.

The thirteenth NMOS transistor N13 is connected between the node QA and the node YA, and the fourteenth NMOS transistor N14 is connected between the node QAb and the node YA. Data input control signals DI and nDI are respectively input to gates of the thirteenth and fourteenth NMOS transistors N13 and N14.

The fifteenth NMOS transistor N15 of the data inverting unit 224 is connected between the sensing node SO and the node QAb, and a control signal PDUMP is input to the gate of the fifteenth NMOS transistor N15.

The sixteenth and seventeenth NMOS transistors N16 and N17 are connected in series between a node QAb and the ground, a sensing node SO is connected to a gate of the sixteenth NMOS transistor N16, and a seventeenth NMOS transistor ( The control signal CLCH is input to the gate of N17.

A timing diagram of each control signal according to the program verifying operation according to the exemplary embodiment of the present invention having the above configuration is as follows.

3A is an operation timing diagram of a flash memory device according to an embodiment of the present invention, FIG. 3B is a sensing operation timing diagram of a program cell according to an embodiment of the present invention, and FIG. 3C is an erase cell according to an embodiment of the present invention. This is a sensing operation timing diagram.

A detailed operation will be described with reference to the timing diagrams of FIGS. 3A to 3C and FIGS. 2B and 2C as follows. In this case, the program verifying operation and the data reading operation of the nonvolatile memory device have a difference in voltage applied to the word line, but are similarly performed.

First, the even bit line BLe is selected to program the memory cell C.

And a control signal is applied as shown in Figure 3a for the program verification. First select the even bit line (BLe), apply a DSL, SSL signal for turning off the drain select transistor (DST) and the source select transistor (SST) of the cell string 211 for verification, and does not verify The pass voltage is applied to the unselected word line to turn on the cells.

In addition, the highest voltage among the verification voltages is applied to the selected word line for verification. That is, in the embodiment of the present invention, when operating for a 2-bit multi-level cell, a voltage set for verifying a state having the highest threshold voltage is applied.

In more detail, for multi-level cells with four threshold voltage distributions, for example [11], [10], [00], and [01], all cells have a threshold voltage lower than the voltage Vp when programmed. Suppose you have Therefore, the voltage Vp is applied to the first cell C0 selected according to the exemplary embodiment of the present invention. The reason why the voltage Vp is applied to the selected word line as described above is that if the voltage level applied to the selected word line is too low, the threshold voltage distribution is high. This is because the cells may not be turned on. In this case, it is difficult to procharge the bit line according to an embodiment of the present invention. Therefore, the cell having the highest threshold voltage distribution can be turned on.

Thereafter, the power supply voltage Vcc is input through the common source line SL according to the program verifying operation. The power supply voltage Vcc input to the common source line SL is precharged to the even bit line BLe according to the program state of the memory cell C.

That is, a voltage lowered from the power supply voltage Vcc by the threshold voltage of the memory cell C is precharged to the even bit line BLe.

The first NMOS transistor N1 of the page buffer unit 221 is turned on to connect the sensing node SO and the even bit line BLe. When the sensing node SO is connected to the even bit line BLe, the voltage level of the bit line transferred to the sensing node SO varies according to the program state of the memory cell C. FIG.

And the page buffer circuit is initialized. To this end, the reset control signal MRST and the setting control signal CSET are input at a high level to turn on the eighth NMOS transistor N8 and the twelfth NMOS transistor N12. When the eighth NMOS transistor N8 is turned on, the node QB is connected to the ground node to a low level. The second PMOS transistor P2 is turned on to output the verification signal nWDO. In addition, when the twelfth NMOS transistor N12 is turned on, the node QA is connected to the ground node and initialized to a low level. Node QAb is at a high level.

The sensing node SO is precharged to a high level by inputting the precharge control signal PRECHb to a low level to turn on the first PMOS transistor P1.

Thereafter, the bit line selection signal BSLe is applied to connect the even bit line BLe and the sensing node SO. If the memory cell C is programmed to have a high threshold voltage, the voltage level transferred to the sensing node SO has a logic level of '0', and if the memory cell C is an erase cell, the sensing sensing node ( The voltage level delivered to SO) will have a logic level of '1'.

If the memory cell C is a programmed cell, the operation of the page buffer is performed as follows according to the application of the control signal of FIG. 3B.

First, when the memory cell C is programmed, the sensing node SO has a logic level of almost '0'. Therefore, the sixteenth NMOS transistor N16 maintains a turn off state. Therefore, even when the control signal CLCH is input to the high level to read the sensing node, even when the seventeenth NMOS transistor N17 is turned on, the node QAb is maintained at the high level because the sixteenth NMOS transistor N16 is turned off. do.

When the second program control signal PDUMP is input at the high level, the high level state of the node QAb is input to the gate of the sixth NMOS transistor N6 through the sensing node SO. Therefore, the sixth NMOS transistor N6 is turned on.

Subsequently, when the control signal MLCH is input to the high level to turn on the seventh NMOS transistor N7, the node QBb is connected to the ground node to be at the low level, and the node QB is at the high level. When the node QB is at the high level, the second PMOS transistor P2 is turned off. Therefore, since the verification signal nWDO is not output, it can be determined that the program has been performed.

Next, when the memory cell C is an erased cell, the operation of the page buffer is performed as follows according to the application of the control signal of FIG. 3C.

First, when the memory cell C is an erased cell, the sensing node SO is at a high level. Therefore, the sixteenth NMOS transistor N16 is turned on. When the control signal CLCH is input at the high level, the seventeenth NMOS transistor N17 is also turned on.

Therefore, node QAb is connected to the ground node to a low level. When the second program control signal PDUMP is input at the high level, the fifteenth NMOS transistor N15 is turned on.

When the fifteenth NMOS transistor N15 is turned on, the low level of the node QAb is input to the gate of the sixth NMOS transistor N6. Therefore, the sixth NMOS transistor N6 maintains a turn off state.

Thereafter, when the control signal MLCH is input, the seventh NMOS transistor N7 is turned on. However, since the sixth NMOS transistor N6 is turned off, the node QBb maintains the high level initialized, and the node QB maintains the low level.

When the node QB is at the low level, since the second PMOS transistor P2 is turned on, the verification signal nWDO may be continuously output and may be determined to be an erase cell.

As described above, when the program verification of the memory cell is performed using the power supply voltage input through the common source line, the state of the sensing node SO may be inverted and latched. Therefore, the general sensing node level is inverted in a program verification process or a data readout method using a method of precharging a bitline through a common source line. Verification is possible.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

1A is a cell distribution diagram of an SLC memory device.

1B is a cell distribution diagram of an MLC memory device.

2A is a block diagram illustrating a structure of an MLC memory device according to an embodiment of the present invention.

FIG. 2B is a partial circuit diagram of the memory cell array of FIG. 2A.

FIG. 2C is a detailed circuit diagram of the page buffer circuit of FIG. 2A.

3A is an operation timing diagram of a flash memory device according to an embodiment of the present invention.

3B is a timing diagram illustrating a sensing operation of a program cell according to an exemplary embodiment of the present invention.

3C is a timing diagram of an erase cell sensing operation according to an exemplary embodiment of the present invention.

* Brief description of the main parts of the drawings *

200: flash memory device 210: memory cell array

220: page buffer unit 230: Y decoder

240: X decoder 250: voltage providing unit

260 control unit

Claims (12)

Inputting a positive voltage through a common source line of the cell strings of the memory cells to precharge the bit line according to a program degree of the selected memory cell; Storing data according to a voltage level of a sensing node changed according to the voltage level of the bit line, into a first latch of a page buffer; And Transferring data stored in the first latch to the second latch through the sensing node; Method of operating a nonvolatile memory device comprising a. The method of claim 1, And a sensing node is changed to a low level when the memory cell is turned off with respect to a voltage applied to a word line to which the selected memory cell is connected. The method of claim 1, The precharging of the bit line may include: A first voltage is applied to a word line to which the selected memory cell is connected, and a pass voltage is applied to an unselected word line so that each bit line is changed in voltage according to a program state of the selected memory cell. A method of operating a nonvolatile memory device. The method of claim 1, And storing data according to the voltage level of the sensing node in the first latch is characterized in that the second latch is in a disabled state and data opposite to a program state of the selected word line is stored in the first latch. A method of operating a nonvolatile memory device. The method of claim 1, The transferring of data stored in the first latch to the second latch may include enabling the second latch, and then transferring the data stored in the first latch to the second latch through the sensing node to the selected memory. And storing data according to a program state of a cell in the second latch. Inputting a positive voltage through a common source line of the cell strings of the memory cells to precharge the bit line according to the program degree of the memory cell where the program is performed, and changing the bit line voltage according to the data state stored in the memory cell ; Storing data according to the voltage level of the bit line into a first latch of a page buffer; And Outputting a verification signal according to the data state transferred to the second latch after transferring the data stored in the first latch to the second latch; Method of operating a nonvolatile memory device comprising a. The method of claim 6, When the memory cell is programmed, And the sensing node is changed to a low level. The method of claim 6, The precharging of the bit line may include: Performing a program on the multi-level cells of the memory device; Inputting a positive voltage to a common source line commonly connected to a cell string to which the multi-level cells are connected for program verification; And Precharging each bit line by applying a first voltage to a selected word line among a plurality of word lines cross-connected to cell strings of the multi-level cells, and applying a pass voltage to an unselected word line Operating method of a nonvolatile memory device comprising a. The method of claim 6, And a sensing node connected to the precharged bit line is in a precharge state at a high level. The method of claim 6, And first and second latches of the page buffer are initialized before the data of the sensing node is latched. The method of claim 6, Storing data in the first latch according to the voltage level of the bit line may include enabling the second latch and storing data in the first latch as data having a logic level opposite to the voltage level of the bit line. A method of operating a nonvolatile memory device, characterized in that. The method of claim 11, Delivering data stored in the first latch to the second latch enables the second latch and transfers the data stored in the first latch to the second latch through the sensing node. Method of operation of a nonvolatile memory device.

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