JPH11213579A - Reproducing device and reproducing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To write sure data in an address in which the data are to be wiritten by detecting an error being in ID data while using ID error checked data, updating the content of the data based on the ID data and previously reproduced ID data when the error is not present and holding them and by controlling the writing operation of the data to a memory. SOLUTION: The continuity of IDs is judged by a compared result from an AND circuit 227 when the newest ID held in registers 209, 211 and an ID predicted from the ID held in registers 219, 221 coicide. When the ID is detected and the ID coincides with the compared result between the IDs predicted in the registers 219, 221, switches 217A, B, switches 245 A, B and switches 251 A, B are respectively connected to fixed positions a, b, c, d. Then, the writing of data to the memory is controlled by holding the ID being in a catched state and a newest ID to be newly reproduced and, next, by comparing an ID to be newly reproduced with these held TDs.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a reproducing apparatus and method, and more particularly, to control of writing a reproducing signal to a memory.

[0002]

2. Description of the Related Art As a device of this type, a digital VTR for digitizing an image signal and recording / reproducing it on a magnetic tape has been known.

In such a digital VTR, a sync block or ID data is added to a predetermined amount of main data (audio data, image data) to form a sync block, and recording and reproduction are performed in sync block units. ing.

At this time, a parity code is added to each sync block as an error correction check code, and errors in the reproduced signal are corrected in sync block units.

The ID data added to each sync block is important information indicating the position of the sync block on the screen, and determines a write address for writing a reproduction signal to a memory based on the ID data. doing. Therefore, ID parity data for detecting and correcting an error in the ID data during reproduction is often added to the ID data.

At the time of reproduction, according to the error correction result of the ID parity data, if an uncorrectable error is included in the ID data, the address indicated by the ID data is determined to be incorrect, and the ID data of another sync block is used to determine that the address is incorrect. The address of the sync block can be predicted.
Then, the reproduced signal is written to the memory according to the predicted address, and the original data can be restored.

[0007]

However, depending on the error of the ID data, even if it is determined that there is no error as a result of checking the ID parity as described above, an error actually occurs. Erroneous correction may occur.

In this case, since there is no error as a result of the ID parity check, a reproduced signal is written to a memory address indicated by incorrect ID data.

As a result, the reproduced signal is written at an address different from the address to which the signal should be written, and the reproduced signal written at the wrong address is not corrected by the above-described error correction processing using the parity code. In such a case, there is a problem that a large noise is output.

An object of the present invention is to solve the above-mentioned problems.

Another object of the present invention is to detect even if the ID data is erroneous, and to surely store the reproduced data at the address to which the ID data should be written.

Another object of the present invention is to prevent the quality of a reproduced signal from being degraded due to an error.

[0013]

In order to solve the above problems and achieve the object, the present invention provides information data, ID data relating to the information data, and ID error check data for checking an error in the ID data. Playback means for playing back digital data consisting of:
A memory for storing the information data reproduced by the reproducing means;
ID error detecting means for detecting an error in the D data;
When the ID error detecting means determines that there is no error, the first holding means updates and holds the content with the ID data, and the ID error detecting means determines that there is no error. Second holding means for updating and holding the contents based on the ID data reproduced before the ID data, ID data reproduced by the reproducing means, and ID data stored in the first holding means.
A memory control unit that controls a write operation of the information data to the memory based on the D data and the ID data held in the second holding unit.

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings.

In this embodiment, a case where the present invention is applied to a digital VTR will be described.

FIG. 1 is a block diagram showing a configuration of a reproduction system of a digital VTR to which the present invention is applied.

In FIG. 1, a signal reproduced from a tape 101 by a head 103 is amplified by a reproduction amplifier 105 and output to an equalizer 107. Equalizer 1
07 is a partial response class 1 for the reproduced signal
(Hereinafter referred to as PR1) Equalization (integral equalization) processing is performed to compensate for the deterioration of the reproduction signal due to the magnetic recording / reproduction system, and the A / D converter 1
09 is output.

The A / D converter 109 is a clock generation circuit 1
The reproduction signal output from the equalizer 107 is sampled in accordance with the clock from 33, and is converted into a digital signal of a plurality of bits per sample. The reproduction signal output from the A / D converter 109 is output to the PR4 equalizer 111 and the clock generation circuit 133.

The clock generating circuit 133 has a PLL circuit, generates a clock phase-synchronized with the output signal of the A / D converter 109, and generates an A / D converter 109, a PR4 equalizer 111, a Viterbi decoder 117, and a synchronization / address. Output to the detection circuit 119.

The PR4 equalizer includes a delay circuit 113 for delaying the output of the A / D converter 109 by two clocks, and an adder 115 for obtaining a difference between the delay circuit 113 and the output of the A / D converter 109. The data is subjected to PR4 equalization processing and output to the Viterbi decoder 117. Since the signal output from the PR4 equalizer 111 has already been sampled by the A / D converter 109, the signal here becomes a ternary signal.

The Viterbi decoder 117 detects the original binary signal of 1 bit per sample from the signal output from the PR4 equalizer 111 by using the Viterbi algorithm, and outputs it to the memory control circuit 119. The memory control output circuit 119 detects the synchronization data from the reproduction signal from the Viterbi decoder 117 and checks the ID data as described later, and outputs the reproduction signal and the write address in the track memory 121.

The track memory 121 is capable of storing compressed and encoded reproduction signals for a plurality of frames (three frames in this embodiment), and stores the reproduction signals in accordance with a write address from the memory control circuit 119. E
The CC processor 123 accesses the track memory 121 and corrects an error in the reproduction signal written in the track memory 121. At this time, based on the flag information output from the ECC processor 123, the uncorrectable error data is interpolated using the data stored at the corresponding position in the previous or subsequent frame.

The reproduction signal corrected by the ECC processor 123 is read out in an order suitable for processing in the reproduction processing circuit 125. The reproduction processing circuit 125 decodes the reproduction signal read from the track memory 121 and performs a decoding process for a known block coding such as inverse DCT to expand the amount of the information.
Output to

The video memory 127 is a reproduction processing circuit 125
The output reproduction signal is stored and read out in an order suitable for display and output to the output circuit 129. The output circuit 129 converts the digital signal read from the memory video 127 into an analog signal, converts the digital signal into a signal in a format suitable for an output device such as an external monitor, and outputs the signal from a terminal 131.

The operation unit 137 has a recording / reproduction switch, a switch for instructing fast-forward / rewind, and the like, and outputs an instruction signal corresponding to each switch operation to the control unit 135. The control unit 135 controls the operation of each circuit in FIG. 1 and the mechanism 139 including a capstan / capstan motor, a head drum motor and the like in accordance with the reproduction mode instructed by the operation unit 137 to control the transport operation of the tape 101.

Next, the tape format in the digital VTR of the present embodiment will be described.

FIG. 2 is a diagram showing the state of signals recorded on the tape 101. Many helical tracks are formed on the tape 101, and image data and audio data for one frame are recorded on ten tracks. Also,
Each track is recorded in the direction in which the head 103 traces while transporting the tape 101 in the direction of arrow A, in the order of audio data, image data, and subcode data. Each data is composed of a plurality of sync blocks.

Next, the configuration of each sync block will be described.

FIG. 3 is a diagram showing the structure of each sync block. Each sync block is composed of 90 bytes of data, and 2 bytes of sync data, ID
The data is recorded in the order of 3 bytes of data, 77 bytes of main data such as image / audio / C2 parity, and 8 bytes of data parity.

Further, the ID data is composed of ID0, ID1 and ID parity (hereinafter, IDP) of 1 byte each. The sequence number, which is a value incremented for each frame of the image, is recorded in the upper 4 bits of ID0, and the track pair number is recorded in the lower 4 bits. Track pair number is 2 on the tape
One for each helical truck,
This is a value that is incremented in order within a plurality of tracks constituting one frame.

For example, in this embodiment, since one frame of the video signal is recorded on ten tracks, the track pair number is assigned a value that increments from 0 to 4.

A sync block number is recorded in 8 bits of ID1. In this embodiment, sync data block numbers 2 to 15 are assigned to audio data in one track, and sync block numbers 19 to 167 are assigned to image data. And these ID0, I
1-byte IDP is added to 2-byte data of D1. IDP is data for checking for an error in the reproduced ID0 and ID1.
It is possible to detect errors of up to 8 bits out of all 24 bits of 0, ID1, and IDP.

The next 77 bytes after the IDP are the main data, followed by 8 bytes of data parity for correcting and detecting an error in the main data.
With this 8-byte data parity, the main data +
An error of up to 4 bytes out of 85 bytes of data parity can be corrected.

FIG. 4 shows the format of image data for one track in the present embodiment.

The image data (main data) is composed of a Reed-Solomon product code. As shown in FIG. 4, the image data recorded on one track uses the C1 parity and the C2 parity, and the vertical direction (the C2 direction) and the C1 parity. Error correction coding is performed independently in the horizontal direction (C1 direction). Therefore, when all the data of a certain sync block is not written in the memory, the ECC processor performs error correction processing with the data of the sync block as an all error, and can perform correction by performing vertical and horizontal correction by C1 and C2. With the number of errors, it is possible to reproduce (correct) all the data of the sync block that has not been written.

However, if the ID data is erroneously detected as described above, the main data and the data parity of each sync block are written to the address where the data of the other sync block is to be written, while keeping the contents. Therefore, if there is no error in the main data, no error is detected in the correction result in the C1 direction, and the ECC
The processor cannot judge data writing due to erroneous detection of ID data. As a result, the data of the sync block is output as noise.

FIG. 5 shows an example of a memory control circuit 119 for actually detecting sync data and ID data from the reproduced data having such a configuration and writing a reproduced signal to the track memory 121. The operation will be described with reference to the state transition diagram of FIG.

FIG. 5 is a diagram showing an example of the memory control circuit 119.

In FIG. 5, the reproduced signal output from the Viterbi decoder 117 is output from an input terminal 301 to a sync data detection circuit 303 and a serial / parallel conversion circuit (hereinafter, an S / P conversion circuit) 307. The sync data detection circuit 303 detects sync data at the head of each sync block in the reproduction signal and having a predetermined pattern, and outputs a signal indicating this to the counter 305. The counter 305 counts the clock from the clock generation circuit 133, and counts 1 according to the output of the sync data detection circuit 303.
Various timing pulses are generated for each byte and each sync block, and output to the main part of the device.

The S / P conversion circuit 307 converts the input signal into a parallel signal in units of 8 bits according to a timing clock indicating one byte, and outputs the parallel signal to the registers 309 and 311, the ID parity check circuit 313 and the memory 335. The registers 309 and 311 are supplied with timing pulses from the counter 305, respectively. The register 309 holds ID0 and the register 311 holds ID1.

The ID parity check circuit 313 checks the error at the timing when the IDP is input from the S / P conversion circuit 307 by using the ID data held in the registers 309 and 311 and a total of 24 bits of the IDP. And supplies the result to the sequencer 315 and the switch 317 as 1-bit digital data. In this embodiment, as a result of the check by the ID parity check circuit 313, if there is no error (hereinafter, IDG), a signal of logic 1 is output.

Further, ID0 held in the register 309
Is connected to the register 319 via the terminal a 'of the switch 317A.
The output of the register 319 is output to the terminal a of the switch 317 and the latch 3
31. The ID1 held in the register 311 is output to the register 321 via the terminal a 'of the switch 317B and is also output to the comparison circuit 325. The output of the register 321 is added by an adder 329 to its content (the sync block number indicated by the ID1 data), output to the terminal a of the switch 317B, and output to the latch 333.

The switches 317A and 317B operate in conjunction with each other. When the IDG is output from the ID parity check circuit 313, the switch is connected to the terminal a '. Connected to.
Since the predicted value of the next ID determined from the currently obtained ID is led to the terminal a side of each switch, the registers 319 and 321 respectively predict from the previously reproduced ID with no error. The values of the sequence number, track pair number, and sync block number are held.

The outputs of the registers 319 and 321 are delayed by three sync blocks by the latches 331 and 333, respectively, and given as write addresses of the track memory 121. The reproduction data output from the S / P conversion circuit 307 is delayed by three sync blocks by the memory 335 and output to the track memory 121.

Here, the reason why the three sync blocks are delayed is that, as described later, even if the IDP inspection result is IDNG twice consecutively, no error occurs in two sync blocks before and after those sync blocks. This is because both sync blocks also check the continuity of the IDs, and the data and the address are delayed in order to secure the time necessary to confirm the continuity.

The comparison circuit 323 includes registers 309 and 3
The outputs of 19 are compared, and if the contents of these two data match, the logic 1 is output. If they do not match, 1-bit data of logic 0 is output to the AND circuit 327. Similarly, the comparison circuit 325 compares the outputs of the registers 311 and 321. When the contents of these two data match, the logic 1 is set, and when they do not match, the logic becomes 0.
The bit data is output to the AND circuit 327. The AND circuit 327 outputs logic 1 when both inputs are logic 1.

As a result, the output of the AND circuit 327 becomes
When the value of the latest ID data output from the registers 309 and 311 matches the value of the predicted ID obtained from the register 319 and the adder 329, the value becomes logic 1, and the comparison result is output to the sequencer 315. You.

The sequencer 315 makes a judgment using the IDP inspection result from the ID parity inspection circuit 313 and the comparison result from the AND circuit 327, and
1 is output.

The operation of the sequencer 315 will now be described with reference to the state transition diagram of FIG.

In this example, there are seven states (hereinafter referred to as states) from 0 to 6, and the ID from the ID parity check circuit 313 is
2 of the inspection result of P and the comparison result from AND circuit 327
Transition between each state by one input. As described above, in the case of IDNG, comparison cannot be performed. Therefore, the types of input are: (1) IDP is no error (IDNG); (2) IDP is no error; CPG) (3) There are three types: IDP has no error and the comparison result with the predicted ID does not match (hereinafter, CPNG).

The initial state is a state of 0, and IDNG
Is in this state as long as. When the IDG is detected, the state transits to the state 1. State 1 is a state waiting for a match with the next ID. The ID of the next sync block is detected, and the state transits to state 4, which is CPG. State 4 is a state in which the continuity of the ID has been confirmed. When the state transits from state 1 to state 4, the write enable signal is output after two sync block periods in accordance with the data and address delay and timing.

In this example, state 4 or more (state 4,
5 and 6) are capture (lock) states in which continuity of IDs is ensured. In these states, the track memory 121 is used.
The reproduction data is written to the.

The next sync block is detected in state 1, and if it is IDNG, the state transits to state 2. If the IDP inspection result is an error, it is not possible to check whether the IDs are continuous or not.
9, 321 are updated with the value of the ID predicted from the ID at the time of IDG in state 1, and prepare for comparison with the next detected ID.

In the state 2, the ID of the next sync block is detected. If the ID is the IDG and the CPG (the detected ID is the same as the predicted ID), the state transits to the state 4, and the data or address is delayed. After one sync block period, a write enable signal is output. If the ID of the next sync block is IDNG in state 2, the state transits to state 3. At this time, in order to prepare for the comparison of the next ID, the registers 319 and 321 further store values predicted from the state of state 2. Update with.

If the ID of the next sync block is CPG in state 3, the state transits to state 4 and immediately outputs a write enable signal to the track memory 121. In state 3, I of the next sync block
If D is IDNG, the process returns to state 0, which is the initial state.

If the state is IDG and CPNG in states 1 to 3, the continuity cannot be confirmed, so that the state transits to state 1 and waits for the next ID.

On the other hand, the next sync block is detected in state 4, and in the case of CPG, state 4 is maintained. In the case of IDNG, the state sequentially transitions to states 5 and 6. If IDNG continues three times, the state returns to state 0, and writing to the memory 121 is stopped.

If CPG is detected in state 5 or state 6, the state transits to state 4. If the state is CPNG in the states 4 to 6, the continuity of the ID is lost, and there is a possibility that an erroneous detection of the ID may have occurred. Until then, the writing of the reproduction data to the memory 121 is stopped.

In the case of transition from state 4 to state 1, writing is inhibited after three sync blocks have elapsed, writing is inhibited after two sync blocks from state 5, and one sync block after state 6. Thus, the time between the determined ID and the data output to the memory 121 can be matched.

In the example described above, the continuity of the ID is monitored to control the writing to the memory, so that it is possible to prevent data from being written to an erroneous address. It is possible to prevent the reproduction data from being written in the wrong position and deteriorating the image quality.

By the way, in the above-mentioned example, I
Since the continuity between the most recently obtained IDs in D is monitored, among a plurality of sync blocks that are continuously reproduced,
Even when only one ID of a certain sync block is erroneously detected alone, the continuity of the ID is immediately lost. For this reason, even if the ID of the sync block immediately after the erroneous detection ID is correctly detected, it is not possible to immediately return to the reproduction data write state, and the data write is prohibited until the continuity of the ID is confirmed again. Would. As a result, in many cases, writing to the memory is prohibited even though the data is correctly reproduced.

In the memory control circuit of the present embodiment described below,
This makes it possible to increase the rate at which correctly reproduced data is written as compared with the circuit of FIG.

Hereinafter, the memory control circuit 11 according to the present embodiment will be described.
9 will be described with reference to FIGS. 7 and 8.

In FIG. 7, the reproduction signal output from the Viterbi decoder 117 is output from the input terminal 201 to the sync data detection circuit 203 and the S / P conversion circuit 207. The sync data detection circuit 203 detects sync data having a predetermined pattern at the beginning of each sync block in the reproduction signal, and outputs a signal indicating this to the counter 205. The counter 205 counts the clock from the clock generation circuit 133, and
In response to the output of 3, various timing pulses of one byte and one sync block are generated and output to the main part of the apparatus.

The S / P conversion circuit 207 converts the input signal into a parallel signal in units of 8 bits according to a timing clock indicating one byte, and outputs the parallel signal to the registers 209 and 211, the ID parity check circuit 213, and the memory 271. The registers 209 and 211 are each supplied with a timing pulse from the counter 205, and the register 209 holds ID0 and the register 211 holds ID1.

The ID parity check circuit 213 checks for errors using the ID data held in the registers 209 and 211 and the IDP data of a total of 24 bits at the timing when the IDP is input from the S / P conversion circuit 207. And supplies the result to the sequencer 215 and the switch 231.

The ID0 held in the register 209 is output to the register 219 via the terminal a 'of the switch 217A, and the output of the register 219 is output to the terminal a of the switch 217A. Also, the I held in the register 211
D1 is connected to the register 2 via the terminal a 'of the switch 217B.
21, 1 is added to the content by the adder 229, and the result is output to the terminal a of the switch 217 </ b> B.

The switches 217A and 217B operate in conjunction with each other, and their connection is controlled by the sequencer 215 as described later. That is, the switches 217A and 217B are set to a '
When connected to the terminal side, the latest ID0 and ID1 held in the registers 209 and 211 are input, and when connected to the a terminal side, the sequence number, track pair number, and sync number predicted from the ID when no error was detected earlier. The value of the block number is entered.

The outputs of the registers 209 and 219 are output to the comparison circuit 223, and the register 211 and the adder 2
29 are output to the comparison circuit 225. Each comparison result of the comparison circuits 223 and 225 is output to the AND circuit 227, and the AND circuit 227 takes the AND of these and outputs the result to the sequencer 215. The comparison result output from the logical product circuit 227 indicates the latest reproduced ID in the register 2.
When the IDs predicted from 19 and 221 match, the logic 1 is set.

In this embodiment, the switches 217A and 217B are connected to the IDP in the write-protected state of states 0 to 3 as described later.
It is connected to the a 'terminal based on the IDG from the inspection circuit 213, but is connected to the a terminal in the write permission state of state 4 or higher except for a specific state transition.

Further, ID0 held in the register 209
Is output to the register 233 via the terminal b of the switch 231A, and the output of the register 233 is output to the terminal b 'of the switch 231A. The ID1 held in the register 211 is output to the register 235 via the terminal b of the switch 231B, and the content of the ID1 is added to 1 by the adder 243.
Are added and output to the terminal b ′ of the switch 231B.

The switches 231A and 231B operate in conjunction with each other, and the ID
When G is obtained, it is always connected to the terminal b. That is, the registers 233 and 235 always hold ID0 and ID1 when the latest IDG is obtained.
Is not obtained, the ID is updated with the ID predicted from the currently held ID.

The output of the register 233 is
09 together with the output of the register 211 and the output of the register 235 together with the output of the register 211.
39. The comparison circuits 237 and 239 store the latest ID stored in the registers 209 and 211, respectively.
And the prediction ID held in the registers 233 and 235, and outputs the result to the AND circuit 241. The AND circuit 241 calculates the logical product of the comparison results of the respective comparison circuits,
Output to the sequencer 215.

The outputs of the registers 233 and 235 are output from the switches 245A and 245B and the registers 263 and 26, respectively.
5 and is delayed by one sync block period by the registers 263 and 265. The outputs of the registers 263 and 265 are output to the switches 251A and 251B and the registers 267 and 269, respectively, and are delayed by one sync block period by the registers 267 and 269. Register 26
7, 269 are output to switches 257A and 257B.

The outputs of the registers 219 and 221 are supplied to the register 2 via switches 245A and 245B, respectively.
47 and 249, where it is delayed by one sync block period. The switches 245A and 245B are controlled by the sequencer 215 and are switched in conjunction with each other.
Connected to terminal side.

The outputs of the registers 247 and 249 are supplied to the registers 253 and 253 via switches 251A and 251B, respectively.
255, where it is delayed by one sync block period. Switches 251A and 251B are connected to sequencer 215
And are switched in conjunction with each other, and are normally connected to the d terminal side.

The outputs of the registers 253 and 255 are sent to the registers 2 through switches 257A and 257B, respectively.
59 and 261, where it is output as an address of the memory 121 after being delayed by one sync block period. The switches 257A and 257B are controlled by the sequencer 215 to switch in conjunction with each other, and are normally connected to the e terminal side.

The reproduction data output from the S / P conversion circuit 207 is output to the memory 121 after being delayed by three sync blocks by the memory 271.

Next, the operation of the memory control circuit of this embodiment will be described with reference to the state transition diagram of FIG.

In FIG. 8, states 0 to 3 are almost the same as those in FIG.

However, in the present embodiment, in states 1 to 3, the continuity of the ID is such that the latest ID held in the registers 209 and 211 coincides with the ID predicted from the ID held in the registers 219 and 221. AND circuit 2
The determination is made based on the comparison result output from the reference numeral 27. In addition, switches 217A, 2
Switch 17B.

When IDNG is detected in state 4, the state transits to state 5, and in state 5, the ID
The state transitions to state 6 when NG is detected, and returns to state 0 when IDNG is detected in state 6, as in the case of FIG.

In this embodiment, in the capture state of state 4 or more, the input of the sequencer is as follows: (1) IDP is error (IDNG); (2) IDP is no error (IDG);
9, 221, the comparison result with the ID predicted (hereinafter C
PAG) (3) IDP has no error and registers 233 and 235
(4) The IDP has no error, but the registers 219 and 22
There are four types in which the comparison results with the IDs predicted in Nos. 1 and 233 and 235 do not match (hereinafter, CPNG).

By the way, if the ID is detected in the state 4 and the CPAG is detected, the switches 217A, B, 245A, B, 251A, B and
57A and 57B are respectively connected to terminal positions a, c, d and e which are fixed positions.

In state 4, the next sync block is reproduced, and the result of comparison with the ID predicted by the registers 219 and 221 does not match (hereinafter, CPANG), and
In the case of CPBG, transition is made to state 7. Switch 217
A and B remain connected to the terminal a, and the switch 23
Since 1A and 1B are connected to the terminal b, the ID held in the registers 219 and 221 and the register 233,
The ID is different from the ID held in H.235.

In the state 7, the next sync block is reproduced. If the IDG is the CPAG, the registers 219 and 22 are used.
The ID predicted by 1 and the latest ID held in the registers 209 and 211 match again in one sync block, and the ID that became IDG one sync block before is a single false detection. Conceivable. Therefore, by connecting the switches 217A, B, 245A, B, 251A, B and 257A, B to the terminals a, c, d, e, respectively, the IDs held in the registers 219, 221 are made valid, and the state 4 Transitions to.

On the other hand, in state 7, CPA
If it is NG and CPBG, continuity is newly confirmed between the IDs of the two latest sync blocks.
17A, B, 245A, B and 251A, B are connected to the terminals a ', b', c ', respectively.
35 and the IDs held in the registers 263 and 265 are made valid, and the state transits to the state 4.

In the case of IDNG in state 7, since it is impossible to confirm the continuity of ID, each switch is set to a, b ', c,
Connect to the d and e terminal side, and transit to state 8.

Although the probability is very low, if the state 7 is CPNG, that is, if it is IDG and no continuity is found in any of the comparison results of the AND circuits 227 and 241, the switch 217A , B are connected to the a ′ terminal side, and the state transits to state 1.

When the state becomes CPAG in state 8, the ID which becomes IDG two sync blocks before is determined to be an erroneous detection, and each switch is connected to the terminals a, b, c, d and e. , State 4. Further, in the case of CPANG and CPBG in state 8, continuity can be seen with one IDNG interposed therebetween.
Connect to the c ′, d ′, e ′ terminal side, and transition to state 4. In the case of IDNG in state 8, the process returns to state 0.

Although the probability is very low, in the case of IDG and CPNG in state 8, the switches 217A and 217B are connected to the a 'terminal side to update the contents of the registers 209 and 211 with the latest ID, and the state 1 Transitions to.

In state 5, the next ID is CPAG.
If so, the process returns to the state 4, and in the case of CPANG and CPBG, the process transits to the state 9.

This state 9 is a case where the state changes from IDNG to CPBG from state 4 which is the capture state. In state 9, the next sync block is reproduced and CPAG
If so, it is determined that the ID of the sync block reproduced immediately before is erroneously detected, and each switch is set to a, b, c, d, e.
And the state transits to State 4.

In the state 9, if the CPBG is used, continuity is newly confirmed between the IDs of the two latest sync blocks, so that the switches are set to a ′, b, c ′, d ′,
The state transits to the state 4 as e ′. If it is IDNG in the state 9, the process returns to the state 0, and writing to the memory is prohibited.

In the case of CPNG in state 9, the switches 217A and 217B are connected to the a 'terminal side, the contents of the registers 219 and 221 are updated with the latest ID, and the state transits to state 1.

As described above, in this embodiment, both the ID in the captured state and the newly reproduced latest ID are held, and then the newly reproduced ID and the two IDs held are stored. We compare which has continuity. Since the writing of the memory is controlled in accordance with the result of the comparison, it is possible to write the reproduced data accurately at the address where the writing should be performed.

That is, in the examples shown in FIGS. 5 and 6, the contents of the registers 319 and 321 are updated by the IDG, and only the latest ID is compared with the ID predicted from the registers 319 and 321 to store the memory. I controlled writing. Therefore, when one ID is erroneously detected by itself, the subsequent operations of the comparison circuits 323 and 325 are dragged by the erroneous detection of the single ID, and the ID is again detected.
Continuity is confirmed, and it takes time to start memory writing.

On the other hand, in the present embodiment, the register 23 whose contents are updated with the latest ID based on the IDG
3, 235, in addition to the registers 219 and 221 that automatically update the contents with the ID predicted from the ID held immediately before even when the IDG is obtained. Memory writing is controlled according to the result of comparison between the predicted ID and the latest ID.

Therefore, even if the ID of a certain sync block among a plurality of sync blocks reproduced continuously is erroneously detected alone, the I before the erroneous detection is performed.
By comparing whether the ID predicted from D matches the latest ID, it is possible to write the reproduction data to the correct address where it should have been written without dragging the influence of erroneous detection of a single ID.

In this embodiment, the present invention is applied to a digital VT
The case where the present invention is applied to R has been described, but the present invention is also applicable to a device that records and reproduces information data together with ID data, and has the same effect.

[0101]

As described above, according to the present invention,
Based on the reproduced ID data, it is possible to reliably write the reproduced data to the address where it should be written.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a digital VTR as an embodiment of the present invention.

FIG. 2 is a diagram showing a recording format on a tape by the apparatus of FIG. 1;

FIG. 3 is a diagram showing a configuration of data handled by the apparatus of FIG. 1;

FIG. 4 is a diagram showing a configuration of data handled by the apparatus of FIG. 1;

FIG. 5 is a diagram illustrating a configuration example of a memory control circuit of the device in FIG. 1;

FIG. 6 is a diagram for explaining the operation of the circuit of FIG. 5;

FIG. 7 is a diagram showing a configuration example of a memory control circuit of the device in FIG. 1 as an embodiment of the present invention.

FIG. 8 is a diagram for explaining the operation of the circuit of FIG. 7;

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI G11B 20/18 572 G11B 20/18 572G 574 574H

Claims (15)

[Claims] 1. An information system comprising: information data;
A reproducing unit for reproducing digital data composed of D data and ID error check data for checking an error in the ID data from a recording medium; a memory for storing information data reproduced by the reproducing unit; ID error detecting means for detecting an error in the ID data using error check data, and when the ID error detecting means determines that there is no error, updating and holding the contents with the ID data. Holding means; second holding means for updating and holding the contents based on ID data reproduced before the ID data even when the ID error detecting means determines that there is no error; ID data reproduced by the reproducing means,
And a memory control means for controlling an operation of writing the information data to the memory based on the ID data held in the holding means and the ID data held in the second holding means. 2. The method according to claim 1, wherein the ID data includes position data indicating a position of the information signal, and the memory control unit controls the first data.
2. A write address of said information data in said memory is designated by selectively using ID data held by said holding means and said second holding means.
A playback device according to claim 1. 3. The method according to claim 1, wherein the memory control means compares the ID data reproduced by the reproduction means with first prediction data obtained based on the ID data stored in the first storage means. And second comparing means for comparing the ID data reproduced by the reproducing means with the second extraordinary data obtained based on the ID data held in the second holding means. 2. The reproducing apparatus according to claim 1, further comprising: controlling an operation of writing the information data to the memory based on a comparison result of the first comparison unit and a comparison result of the second comparison unit. 3. 4. The memory control means selectively uses the ID data held in the first holding means and the ID data held in the second holding means to store the information data in the memory. 4. The reproduction according to claim 3, further comprising an address designating unit for designating a write address, wherein the selecting operation of the address designating unit is controlled based on a comparison result of the first comparing unit and a comparison result of the second comparing unit. apparatus. 5. The digital data is recorded on a large number of tracks formed on the recording medium,
5. The reproducing apparatus according to claim 1, wherein the data includes track position information indicating a position of a track on which the information data is recorded. 6. The digital data includes a plurality of blocks each having synchronization data, the ID data, ID error check data, and a predetermined amount of the information data, and the ID data includes block number information indicating a number of the block. The playback device according to claim 1, further comprising: 7. Information data and an I related to the information data
A reproducing unit for reproducing digital data having D data from a recording medium; a memory for storing information data reproduced by the reproducing unit; and the memory reproduced before the latest ID data reproduced by the reproducing unit. First generating means for generating ID data to be reproduced next by the reproducing means based on the ID data; and reproducing the next ID data based on the latest ID data reproduced by the reproducing means. A second generating means for generating power ID data; an ID data reproduced by the reproducing means; an ID data generated by the first generating means; and an ID data generated by the second generating means. And a memory control means for controlling an operation of writing the information data to the memory by using the information processing apparatus. 8. The memory control means uses the ID data reproduced by the reproduction means and the ID data generated by the first generation means to determine the reliability of the ID data reproduced by the reproduction means. Determining the reliability of the ID data reproduced by the reproducing means using the first determining means for determining and the ID data reproduced by the reproducing means and the ID data generated by the second generating means; 8. The reproducing apparatus according to claim 7, further comprising a second discriminating means, wherein a writing operation of the information data to the memory is controlled according to a discrimination result of the first and second discriminating means. 9. Information data and an I related to the information data
A reproducing unit for reproducing the D data from the recording medium; a memory for storing information data reproduced by the reproducing unit; and a memory based on the ID data reproduced before the latest ID data reproduced by the reproducing unit. First generating means for generating ID data to be reproduced next by the reproducing means; and ID data to be reproduced next by the reproducing means based on the latest ID data reproduced by the reproducing means. A second generating unit that generates the first ID data that is generated by the first generating unit and the ID data that is reproduced by the reproducing unit;
Comparing the ID data generated by the second generating means with the ID data reproduced by the reproducing means.
And a memory control means for controlling the operation of writing the information data to the memory based on the outputs of the first and second comparison means. 10. A method of reproducing digital data having information data and ID data related to the information data from a recording medium and storing the reproduced information data in a memory, wherein the reproduced information data is reproduced before the latest ID data. The first ID data to be reproduced next is generated based on the ID data, and the second ID data to be reproduced next is generated based on the latest ID data.
A reproducing method for controlling a write operation of the information data to the memory by using data, the first ID data, and the second ID data in parallel. 11. A method for reproducing digital data having information data and ID data related to the information data from a recording medium and storing the reproduced information data in a memory, wherein the reproduced information data is reproduced before the latest ID data. The first ID data to be reproduced next is generated based on the ID data, and the second ID data to be reproduced next is generated based on the latest ID data.
A reproducing method for controlling a write operation of the information data to the memory based on a comparison result between data and the first ID data and a comparison result between the reproduced ID data and the second ID data. 12. An apparatus for reproducing, from a recording medium, digital data comprising a plurality of synchronous blocks each having synchronous data, ID data, and a predetermined amount of information data, the apparatus comprising: A reproduction apparatus for detecting the reliability of the ID data of the latest synchronous block using ID data of a synchronous block reproduced two or more times before the latest synchronous block. 13. Based on ID data of a synchronous block reproduced two or more times before the latest synchronous block, predicted ID data considered to be included in the latest synchronous block is generated and reproduced. The latest ID according to a comparison result between the latest ID data and the predicted ID data
13. The method according to claim 12, wherein the reliability of the data is detected.
A playback device according to claim 1. 14. A memory for storing reproduced information data, and memory control means for controlling a write operation of said information data to said memory in accordance with a result of detecting the reliability of said ID data. Claim 1
14. The playback device according to 2 or 13. 15. The reproducing apparatus according to claim 14, wherein the memory control means determines a write address of the information data in the memory according to a result of detecting the reliability of the ID data.