JPH11204797A - Thin film transistor, manufacture thereof and liq. crystal display using the thin film transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To expand a process margin in an impurity implanting step by forming a low-concn. impurity region between source drain region and channel region, and forming offset region below a gate electrode. SOLUTION: Two gate insulation films 14a, 14b are formed, a gate electrode 15 is formed, a pattern is selectively formed so as to leave an upper layer insulation film 14b only at a part for forming an LDD region 13b, and ions are implanted through the two gate insulation films 14a, 14b to form source and drain regions composed of diffusion layer regions 13c and low-concn. impurity region and LDD region 13b at the same time. Using the gate electrode 15 as a mask, and the upper gate insulation film 14b on the LDD region 13b is selectively etched while at the same time of the etching of the upper layer gate insulation film 14b, an offset region 13 is formed between the channel region 13a and the LDD region 13b below the gate electrode 15.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor used for a liquid crystal display, a method for manufacturing the same, and a liquid crystal display using the thin film transistor.

[0002]

2. Description of the Related Art In order to manufacture a transistor having good OFF current characteristics used for a liquid crystal display device, an LDD (L
ightly Doped Drain) structure. The LDD structure is to provide a low-concentration region around the diffusion layer, thereby relaxing the concentration gradient and relaxing the electric field at the source and drain.

FIGS. 13 to 18 are cross-sectional views showing steps of manufacturing a conventional thin film transistor having an LDD structure. The manufacturing steps will be described below. First, as shown in FIG. 13, an amorphous silicon thin film 12 is formed on a glass substrate 10 via a SiO ₂ 11 by a plasma CVD method. Next, FIG.
As shown in FIG. 4, the amorphous silicon thin film 12 is melted and crystallized by excimer laser light irradiation to form a polycrystalline silicon thin film 13. Thereafter, the polycrystalline silicon thin film 13 is processed into an island shape as shown in FIG. 14, a gate insulating film 14 made of a silicon oxide thin film is formed thereon as shown in FIG. The electrode 15 is formed. After the formation of the gate electrode 15, the gate electrode 15
Is used as a mask to perform a first impurity implantation by an ion implantation method to form a low-concentration impurity implantation region, that is, an LDD region 13b. 13a is a channel region. This first impurity implantation is performed by implanting phosphorus (P) ions, for example, with an accelerating voltage of 80.
It is preferable to implant at kV and a dose of 1 × 10 ¹³ / cm ² .

After the first impurity implantation, as shown in FIG. 16, a mask corresponding to the LDD region 13 near the channel region 13a is formed with the photoresist 16 and then the second impurity implantation is performed. High-concentration impurity-implanted region, that is, diffusion layer region 13
Form c. In this second impurity implantation, phosphorus (P) ions are implanted, for example, at an acceleration voltage of 80 kV and a dose of 1 × 10 ^15.
/ Cm ² is preferable.

After the second impurity implantation, the photoresist 1
6 is removed, and the implanted impurity is activated. Thereafter, as shown in FIG. 17, an interlayer insulating film 17 made of silicon oxide is formed. After the formation of the interlayer insulating film 17, contact holes are opened in the source and drain regions, and the source and drain electrodes 18 and 19 are formed as shown in FIG. 18 to complete the thin film transistor.

[0006]

SUMMARY OF THE INVENTION Such a conventional LD
In the thin film transistor having the D configuration, in order to apply the thin film transistor to an active matrix array used for a liquid crystal display device or the like, it is required to increase the margin of the manufacturing process while improving the performance and reliability.

SUMMARY OF THE INVENTION It is an object of the present invention to further improve the OFF current characteristic and reliability of a thin film transistor, and to increase a process margin of an impurity implantation step at the time of manufacturing the thin film transistor to improve a production yield.

[0008]

According to the present invention, there is provided a top gate type thin film transistor having a polycrystalline silicon thin film as an active layer on a glass substrate. It has a concentration impurity region and an offset region below the gate electrode.

As a result, good OFF current characteristics can be obtained, so that the margin of the step of implanting impurities necessary for forming the LDD structure can be expanded,
The production yield can be greatly improved. Also,
Since the offset region can be formed below the gate metal, the reliability of hot carrier injection generated during operation can be improved.

[0010]

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, there is provided a top gate type thin film transistor having a polycrystalline silicon thin film as an active layer on a glass substrate in a low concentration impurity region between a source / drain region and a channel region. And an offset region below the gate electrode.

As a result, in order to obtain good OFF current characteristics, the margin of the step of implanting impurities necessary for forming the LDD structure can be expanded, and the production yield can be greatly improved. Further, since the offset region can be formed below the gate metal, the reliability of hot carrier injection generated during operation can be improved.

According to a second aspect of the present invention, the total length of the offset regions in the channel direction of the thin film transistor is 0.0
The thickness is 4 μm or more and 0.6 μm or less. As a result, both the effect of reducing the OFF current and the effect of preventing the decrease of the ON current can be satisfactorily achieved.

According to a third aspect of the present invention, in manufacturing a top-gate thin film transistor having a polycrystalline silicon thin film as an active layer on a glass substrate, a gate electrode is formed by laminating two gate insulating films of different materials. By stacking, selectively patterning the upper gate insulating film, and implanting impurities through the gate insulating film having the two-layer structure,
After forming the source and drain regions and the low-impurity-concentration regions, and after the impurity implantation, the upper gate insulating film is selectively removed using the gate electrode as a mask, and the upper gate insulating film below the gate electrode is selectively removed. The offset region is formed under the gate electrode by etching.

Thus, the thin film transistor according to the first aspect can be manufactured.

According to a fourth aspect of the present invention, when the offset region is formed under the gate electrode by using tantalum oxide for the upper insulating film and etching the tantalum oxide using the gate electrode as a mask, carbon tetrafluoride is used. Ion etching using a mixed gas of oxygen and oxygen is performed, and the etching pressure is set to 200 mT
orr and not more than 600 mTorr.

Thus, the length of the formed offset region can be set to an appropriate range.

According to a fifth aspect of the present invention, there is provided a liquid crystal display device having an active matrix array substrate for a liquid crystal display device, and a counter substrate having a transparent conductive film formed on a color filter and a black matrix.
The liquid crystal display active matrix array substrate,
At least a thin film transistor for driving a pixel electrode uses the thin film transistor according to claim 1.

As a result, it is possible to obtain a liquid crystal display device having a thin-film transistor having good OFF current characteristics and preventing a decrease in ON current.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. (Embodiment 1) FIGS. 1 to 8 show Embodiment 1 of the present invention.
FIG. 4 is a cross-sectional view for describing a manufacturing process of the thin film transistor relating to FIG.

First, as shown in FIGS. 1 and 2, FIG.
3 and FIG. 14, a polycrystalline silicon thin film 13 is formed on the glass substrate 10. That is, this polycrystalline silicon thin film 13 is formed into an amorphous silicon thin film 12 having a thickness of, for example, 85 nm by a plasma CVD method, and is subjected to a heat treatment at 450 ° C. for 90 minutes in nitrogen to obtain a hydrogen concentration in the film 12. Is formed by melting and crystallizing by excimer laser light irradiation. At this time, for example, XeC having a wavelength of 308 nm is used as a light source of an excimer laser.
Using an excimer laser, energy density 300mJ
/ Cm ² can be crystallized. Thereafter, the polycrystalline silicon thin film 13 is processed into a thin film transistor shape.

Next, as shown in FIG.
A lower gate insulating film 14a made of a silicon oxide thin film is formed to a thickness of, for example, 100 nm by using the
The upper gate insulating film 14b made of Ox is
m. Then, after the two-layered gate insulating films 14a and 14b are formed as described above, the gate electrode 15 is formed. 13a is a channel region. After the gate electrode 15 is formed, as shown in FIG. 4, the upper gate insulating film 14b is formed only in the portion where the LDD region 13b is to be formed.
Is selectively formed so as to leave a pattern. Then, FIG.
As shown in the figure, through the two gate insulating films 14a and 14b, for example, an acceleration voltage of 70 kV and an injection amount of 2 × 10 ¹⁵ /
implanting phosphorus (P) ions at cm ^2, diffusion layer regions 13c
And a low-concentration impurity region, that is, an LDD region 13b.

Thereafter, as shown in FIG.
5 is used as a mask to selectively etch upper gate insulating film 14b on LDD region 13b. For example, etching is performed by reactive ion etching using a mixed gas of carbon tetrafluoride (CF ₄ ) and oxygen, and the pressure is 300.
It is preferable to set mTorr and the overetch amount to 50%. At this time, simultaneously with etching the upper gate insulating film 14b, the offset region 31 between the channel region 13a and the LDD region 13b under the gate electrode 15 is formed.
To form

The length of the offset region 31 under the gate electrode 15 can be controlled by the etching pressure and the over-etching time.
%, The relationship between the etching pressure and the penetration amount, that is, the offset region length (one side) is as shown in FIG. Under the condition of the above etching pressure of 300 mTorr, an offset region 31 of 0.06 μm on one side is formed below the gate electrode 15.

Thereafter, an interlayer insulating film 17 made of silicon oxide shown in FIG. 7 is formed, and after contact holes are opened, source and drain wirings 18 and 19 made of Al are formed as shown in FIG. Thus, a thin film transistor is completed.

FIG. 10 shows the electrical characteristics of the thin film transistor manufactured by such a manufacturing method. That is, the ON current does not decrease and the OFF current decreases as compared with the LDD structure alone. This effect appears when the length of the offset region 31 below the gate electrode 15 is 0.02 μm or more on one side. If the length is 0.3 μm or more, the ON current is significantly reduced due to the influence of the offset region 31. Therefore, the offset region 31 under the gate electrode 15 is 0.02 μm on one side.
It is particularly preferable to set the pressure at the time of dry etching to 200 mTorr to 600 mT.
orr is appropriate.

In addition, by using the above-described manufacturing method, in order to obtain a good OFF current characteristic as shown in FIG. 11, the margin of the step of implanting impurities necessary for forming the LDD structure can be increased. it can. For this reason, the production yield can be greatly improved.

(Embodiment 2) FIG. 12 is a schematic sectional view of a liquid crystal display device using an active matrix array substrate 33 in which thin film transistors 32 manufactured according to the present invention are arranged in pixels. This display device has an active matrix array substrate 33 in which a thin film transistor 32 is formed on a glass substrate 10, and has a counter substrate 34 in which a transparent conductive film 21 is formed on a color filter layer 23 and a black matrix 24. At the time of manufacturing this liquid crystal display device, the alignment film 25 is applied to the active matrix array substrate 33 and the opposing substrate 34, and a rubbing process is performed. Then, both substrates are laminated and the liquid crystal 26 is injected. Finally, both substrates 33 and 34
A polarizing plate 27 is attached to the surface of the liquid crystal display device to complete a liquid crystal display device. In this liquid crystal display device, the liquid crystal is charged by driving the pixel electrode 20 using the thin film transistor 32 as a switching element, and an image is displayed.

In the above description, a pixel driving thin film transistor having an LDD structure and having an offset region below a gate electrode has been described. May also be used. This is particularly effective in improving reliability.

[0029]

As described above, according to the present invention, in a top gate type thin film transistor having a polycrystalline silicon thin film as an active layer on a glass substrate, a low concentration impurity region is provided between a source / drain region and a channel region. And an offset region below the gate electrode, so that good OFF current characteristics can be obtained,
Therefore, the margin of the step of implanting the impurities necessary for forming the LDD structure can be increased, and the production yield can be greatly improved. Further, since the offset region can be formed below the gate metal, the reliability of hot carrier injection generated during operation can be improved.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view for describing a manufacturing process of a thin film transistor according to Embodiment 1 of the present invention.

FIG. 2 is a cross-sectional view for explaining the next stage of FIG.

FIG. 3 is a cross-sectional view for explaining the next stage of FIG. 2;

FIG. 4 is a cross-sectional view for explaining the next stage of FIG. 3;

FIG. 5 is a cross-sectional view for explaining the next stage of FIG.

FIG. 6 is a cross-sectional view for explaining the next stage of FIG. 5;

FIG. 7 is a cross-sectional view for explaining the next stage of FIG. 6;

FIG. 8 is a cross-sectional view for explaining the next stage of FIG. 7;

FIG. 9 is a diagram showing a relationship between an etching pressure and a penetration amount below a gate electrode.

FIG. 10 is a diagram showing current-voltage characteristics of a thin film transistor.

FIG. 11 is a diagram showing a relationship between LDD resistivity and OFF current.

FIG. 12 is a sectional view of a liquid crystal display device according to the present invention.

FIG. 13 is a cross-sectional view for explaining a manufacturing process of a conventional thin film transistor.

FIG. 14 is a cross-sectional view for explaining the next stage of FIG.

FIG. 15 is a cross-sectional view for explaining the next stage of FIG.

FIG. 16 is a cross-sectional view for explaining the next step of FIG.

FIG. 17 is a cross-sectional view for explaining the next stage of FIG. 16;

FIG. 18 is a cross-sectional view for explaining the next step of FIG.

[Explanation of symbols]

 Reference Signs List 10 glass substrate 13a channel region 13b LDD region 13c diffusion layer region 15 gate electrode 31 offset region

Claims (5)

[Claims] 1. A top gate type thin film transistor having a polycrystalline silicon thin film as an active layer on a glass substrate, having a low-concentration impurity region between a source / drain region and a channel region, and an offset below a gate electrode. A thin film transistor having a region. 2. The thin film transistor according to claim 1, wherein the total length of the offset regions in the channel direction of the thin film transistor is 0.04 μm or more and 0.6 μm or less. 3. When manufacturing a top-gate thin film transistor having a polycrystalline silicon thin film as an active layer on a glass substrate, two gate insulating films of different materials are stacked, a gate electrode is stacked, and an upper gate insulating film is formed. By selectively patterning the film and injecting impurities through the gate insulating film having the two-layer structure, source and drain regions and a low-concentration impurity region are formed. After the impurities are implanted, using the gate electrode as a mask, A method of manufacturing a thin film transistor, wherein an offset region is formed under the gate electrode by selectively removing the upper gate insulating film and selectively etching the upper gate insulating film under the gate electrode. 4. When a tantalum oxide is used for an upper insulating film and the tantalum oxide is etched using a gate electrode as a mask to form an offset region below the gate electrode, a mixed gas of carbon tetrafluoride and oxygen is used. The reactive ion etching was performed, and the etching pressure was set to 200 mTorr or more and 600
4. The method according to claim 3, wherein the pressure is not more than mTorr. 5. A liquid crystal display device comprising an active matrix array substrate for a liquid crystal display device and a counter substrate having a transparent conductive film formed on a color filter and a black matrix, wherein the active matrix array substrate for a liquid crystal display is A liquid crystal display device comprising the thin film transistor according to claim 1 as a thin film transistor for driving at least a pixel electrode.