JPH11195725A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH11195725A JPH11195725A JP36075897A JP36075897A JPH11195725A JP H11195725 A JPH11195725 A JP H11195725A JP 36075897 A JP36075897 A JP 36075897A JP 36075897 A JP36075897 A JP 36075897A JP H11195725 A JPH11195725 A JP H11195725A
- Authority
- JP
- Japan
- Prior art keywords
- electrode terminal
- substrate
- semiconductor chip
- external electrode
- terminal block
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1301—Thyristor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Wire Bonding (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置および
その製造方法に関し、特に、例えばセラミック基板上の
銅回路上に複数個の半導体チップを実装してなる大電力
半導体装置およびその製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a high-power semiconductor device having a plurality of semiconductor chips mounted on a copper circuit on a ceramic substrate and a method of manufacturing the same. It is.
【０００２】[0002]
【従来の技術】従来の大電力半導体装置、例えば、ＩＧ
ＢＴ、ＩＥＧＴ（ＩｎｊｅｃｔｉｏｎＥｎｈａｎｓｅｄ
Ｇａｔｅ Ｔｒａｎｓｉｓｔｏｒ）などの大電力トラ
ンジスタモジュールは、セラミック基板上に銅回路を直
接形成したＤＢＣ基板上に、複数個の半導体チップが実
装され、パッケージ内に収納する構造となっている。こ
のようなモジュールにおいては、各半導体チップの電極
端子はＤＢＣ基板上に銅回路の一部として形成される電
極端子台にワイヤボンデイングにより接続される。この
端子台はパッケージ外部に導出される外部電極端子と接
続されるが、この間は大電力トランジスタモジュールに
おいては大電流が流れるため、板状の導体を半田付けに
より接続したり、複数本のワイヤを並列にボンディング
して電流容量を大きくしている。2. Description of the Related Art Conventional high power semiconductor devices such as IG
BT, IEGT (Injection Enhanced)
A high power transistor module such as a Gate Transistor has a structure in which a plurality of semiconductor chips are mounted on a DBC substrate in which a copper circuit is directly formed on a ceramic substrate and housed in a package. In such a module, the electrode terminals of each semiconductor chip are connected by wire bonding to an electrode terminal block formed as a part of a copper circuit on the DBC substrate. This terminal block is connected to external electrode terminals led out of the package.During this time, a large current flows in a high-power transistor module, so that a plate-like conductor is connected by soldering or a plurality of wires are connected. The current capacity is increased by bonding in parallel.
【０００３】[0003]
【発明が解決しようとする課題】このような従来の大電
力半導体装置における電極端子台と外部電極端子との接
続方法として、板状の導体を半田付けにより接続する方
法は接合のために高熱が必要であり、装置自身に高い熱
が加えられること、半田と導体との熱膨張率の差によ
り、熱サイクルに対する信頼性に乏しいこと、半田材と
して一般的である鉛化合物はその毒性があるなど、多く
の問題がある。そしてこれらの問題は大電流になるほど
影響が大きくなり、特に、電気自動車のように、過酷な
自然環境下で用いられる場合には熱サイクルに対する信
頼性は極めて重要である。As a method for connecting an electrode terminal block and an external electrode terminal in such a conventional high-power semiconductor device, a method of connecting a plate-shaped conductor by soldering requires high heat for joining. Necessary, high heat is applied to the device itself, reliability of thermal cycle is poor due to difference in thermal expansion coefficient between solder and conductor, lead compound which is common as solder material has toxicity, etc. There are many problems. These problems become more significant as the current increases, and particularly when used in a harsh natural environment such as an electric vehicle, the reliability of the thermal cycle is extremely important.
【０００４】他方、ワイヤボンデイングにより接続する
方法は、断面積の大きなワイヤの接続が困難であるた
め、大電流用の配線のためには多数のワイヤを並列にボ
ンディングする。しかしワイヤボンデイングにおいて
は、一般に、ワイヤ径の少なくも１．５倍の接合面積が
必要となるため、全体としては大きな接合面積が必要と
なり、半導体装置の小形化を阻害する大きな要因となっ
ていた。On the other hand, in the connection method by wire bonding, it is difficult to connect a wire having a large cross-sectional area. Therefore, a large number of wires are bonded in parallel for wiring for a large current. However, in wire bonding, generally, a bonding area of at least 1.5 times the wire diameter is required. Therefore, a large bonding area is required as a whole, which has been a major factor that hinders miniaturization of a semiconductor device. .
【０００５】したがって本発明はこのような従来装置の
欠点を除去し、高い信頼性と省スペースを併せ持つ半導
体装置およびその製造方法を提供することを目的とする
ものである。SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a semiconductor device having high reliability and space saving, and a method of manufacturing the same, which eliminates such disadvantages of the conventional device.
【０００６】[0006]
【課題を解決するための手段】本発明の半導体装置は、
基板上に固着された半導体チップと、この半導体チップ
の電極端子が電気的に接続されるように前記基板上に形
成された電極端子台と、この電極端子台に超音波接合に
よりその一端が接続され、少なくともこの一端部が板状
の外部電極端子と、この外部電極端子の一部、前記基
板、この基板上に固着された半導体チップおよび電極端
子台を収納するパッケージとを備えたことを特徴とする
ものである。According to the present invention, there is provided a semiconductor device comprising:
A semiconductor chip fixed on a substrate, an electrode terminal block formed on the substrate so that electrode terminals of the semiconductor chip are electrically connected, and one end connected to the electrode terminal block by ultrasonic bonding At least one end of the package includes a plate-shaped external electrode terminal, and a package for accommodating a part of the external electrode terminal, the substrate, a semiconductor chip fixed on the substrate, and an electrode terminal block. It is assumed that.
【０００７】また、本発明の半導体装置においては、前
記基板はセラミック基板であり、前記半導体チップは電
力用半導体チップであり、前記電極端子台は前記セラミ
ック基板上に形成された銅回路の一部であり、また、前
記外部電極端子の少なくとも前記内部電極端子に接続さ
れる部分は銅または銅合金であることを特徴とするもの
である。In the semiconductor device of the present invention, the substrate is a ceramic substrate, the semiconductor chip is a power semiconductor chip, and the electrode terminal block is a part of a copper circuit formed on the ceramic substrate. Further, at least a portion of the external electrode terminal connected to the internal electrode terminal is made of copper or a copper alloy.
【０００８】さらに、本発明の半導体装置においては、
前記外部電極端子の少なくとも前記内部電極端子に接続
される部分はピッカース硬度が約８０以下の金属からな
ることを特徴とするものである。Further, in the semiconductor device of the present invention,
At least a portion of the external electrode terminal connected to the internal electrode terminal is made of a metal having a Pickers hardness of about 80 or less.
【０００９】次に、本発明の半導体装置の製造方法は、
基板上に半導体チップを固着する工程と、この半導体チ
ップの電極端子を前記基板上に固着された電極端子台に
電気的に接続する工程と、この電極端子台に少なくとも
その一端が板状の外部電極端子を超音波接合により接続
する工程と、この外部電極端子の一部、前記基板、この
基板上に配置された半導体チップおよび内部電極端子を
パッケージ内に収納する工程とを備えたことを特徴とす
るものである。Next, a method of manufacturing a semiconductor device according to the present invention
A step of fixing a semiconductor chip on a substrate, a step of electrically connecting electrode terminals of the semiconductor chip to an electrode terminal block fixed on the substrate, and at least one end of the electrode terminal block having a plate-like external shape. A step of connecting the electrode terminals by ultrasonic bonding, and a step of housing a part of the external electrode terminals, the substrate, the semiconductor chip disposed on the substrate, and the internal electrode terminals in a package. It is assumed that.
【００１０】[0010]
【発明の実施の形態】以下、本発明の一実施形態につい
て、図１乃至図３を参照して説明する。図１は本発明の
半導体装置として、大電力トランジスタモジュールの構
造を示す一部切欠斜視図であり、図２は図１に示した半
導体装置の要部を拡大して示す斜視図、図３は図１に示
した半導体装置内部の素子配置を示す平面図である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a partially cutaway perspective view showing a structure of a high power transistor module as a semiconductor device of the present invention, FIG. 2 is an enlarged perspective view showing a main part of the semiconductor device shown in FIG. 1, and FIG. FIG. 2 is a plan view illustrating an element arrangement inside the semiconductor device illustrated in FIG. 1.
【００１１】図示のトランジスタモジュールは、セラミ
ック基板上に銅回路を直接形成したＤＢＣ基板１１上
に、複数個の半導体チップ１２が実装され、樹脂ケース
１３内に収納されている。各半導体チップ１２の電極端
子はＤＢＣ基板１１上に銅回路の一部として形成される
電極端子台１４に複数本のボンデイングワイヤ１５によ
り接続される。この端子台１４は樹脂ケース１３の外部
に導出される外部電極端子１６と接続される。この外部
電極端子１６は大電力トランジスタモジュールにおいて
は大電流が流れるため、板状の導体、例えば銅板をプレ
ス加工等により、所定の形状に加工される。すなわち、
この外部電極端子１６は図２に示されるように、端子台
１４に接合されるほぼＬ字状に曲折された接合端部１６
−１と、この接合端部から樹脂ケース１３内の周辺部に
ほぼ水平に延長され、周辺部においてほぼ垂直方向に曲
折されて樹脂ケース１３の外部上面に導出される本体部
１６−２および樹脂ケース１３の上面において再びほぼ
水平方向に曲折形成される接続端部１６−３とにより構
成されている。この外部電極端子１６は、また、本体部
１６−２からほぼＴ字状に分岐され、それぞれの端部に
接合端部１６−１が形成されている。なお、図２におい
ては、一方の接合端部１６−１が接合される端子台は省
略されているが、図３の平面図に示すように、隣接する
半導体チップ１２の端子台１４に接合される。なお、外
部電極端子１６の形状は図３に示すように、樹脂ケース
１３内で配置された位置により、種々の形状に形成され
る。例えば、樹脂ケース１３の上辺に沿って配置された
外部電極端子１６の形状は、Ｔ字状の分岐を有する本体
部１６−２が２個合体されて共通の接続端部１６−３に
連結される形状、あるいは外部電極端子１６´で示すよ
うに、本体部１６´−２が３分岐され、これらの各分岐
部先端に接合端部１６´−１がそれぞれ形成されてい
る。また、樹脂ケース１３の下辺に沿って配置された外
部電極端子１６´´´の形状はＴ字状の分岐はなく、接
合端部は一方のみ、すなわち、Ｌ字状にに形成されてい
る。In the illustrated transistor module, a plurality of semiconductor chips 12 are mounted on a DBC substrate 11 in which a copper circuit is directly formed on a ceramic substrate, and housed in a resin case 13. The electrode terminals of each semiconductor chip 12 are connected by a plurality of bonding wires 15 to an electrode terminal block 14 formed as a part of a copper circuit on the DBC substrate 11. The terminal block 14 is connected to an external electrode terminal 16 led out of the resin case 13. Since a large current flows in the high power transistor module, the external electrode terminal 16 is processed into a predetermined shape by pressing a plate-shaped conductor, for example, a copper plate. That is,
As shown in FIG. 2, the external electrode terminal 16 is connected to the terminal block 14 and has a substantially L-shaped bent end portion 16.
-1 and a main body 16-2 and a resin extending substantially horizontally to a peripheral portion in the resin case 13 from the joined end portion, bent substantially vertically in the peripheral portion, and led out to the outer upper surface of the resin case 13. A connection end 16-3 is formed on the upper surface of the case 13 in a substantially horizontal direction again. The external electrode terminal 16 is also branched in a substantially T-shape from the main body 16-2, and a joining end 16-1 is formed at each end. In FIG. 2, the terminal block to which one of the bonding ends 16-1 is bonded is omitted, but as shown in the plan view of FIG. 3, the terminal block is bonded to the terminal block 14 of the adjacent semiconductor chip 12. You. In addition, as shown in FIG. 3, the shape of the external electrode terminal 16 is formed in various shapes depending on the position arranged in the resin case 13. For example, the shape of the external electrode terminals 16 arranged along the upper side of the resin case 13 is such that two main portions 16-2 having T-shaped branches are united and connected to a common connection end portion 16-3. As shown by the external electrode terminal 16 ', the main body 16'-2 has three branches, and a junction end 16'-1 is formed at the tip of each branch. In addition, the external electrode terminals 16 ′ ″ arranged along the lower side of the resin case 13 do not have a T-shaped branch, and have only one joint end, that is, an L-shape.
【００１２】外部電極端子１６、（１６´、１６´´
´）の接合端部１６−１は端子台１４に超音波ボンディ
ングにより接合される。表１乃至表３は外部電極端子１
６の接合端部１６−１と端子台１４との超音波ボンディ
ングによる接合についての実験結果を示すものである。The external electrode terminals 16, (16 ', 16'')
The joining end 16-1 of (1) is joined to the terminal block 14 by ultrasonic bonding. Tables 1 to 3 show external electrode terminals 1
6 shows an experimental result of bonding by ultrasonic bonding between the bonding end portion 16-1 and the terminal block 14.
【００１３】[0013]
【表１】 [Table 1]
【００１４】[0014]
【表２】 [Table 2]
【００１５】[0015]
【表３】 [Table 3]
【００１６】表１は接合端部１６−１の材料あるいは硬
度を異ならせ超音波ボンディング装置の動作条件を同一
条件で接合した結果を示している。すなわち、材料とし
てはＣｕ（銅）で硬度をはビッカース硬度（Ｈｖ）で５
０、８０、１２０、のもの、４２アロイ（ニッケル鉄合
金）およびリン青銅を用い、超音波ボンディング装置の
動作条件として、加重を０．１５メガパスカル（ＭＰ
ａ）、超音波の周波数を４０ｋＨｚ、振幅を２０μｍ、
パワーを３００ｗとした。なお、表中の上向きの矢印は
「同上」の条件であることを意味している。この実験結
果は、満足すべき接合力で接合されたかどうかを「接合
可否」で示しているが、４２アロイが他の材料に比較し
てやや不満足という結果となった。また、接合の結果、
端子台１４を構成するセラミック基板に損傷を生ずるか
否かを「セラミックダメージ」の欄に示しているが、ビ
ッカース硬度１２０のＣｕ、４２アロイの場合損傷が生
じ、ビッカース硬度８０のＣｕについても若干の損傷が
生じた。Table 1 shows the results of bonding under the same operating conditions of the ultrasonic bonding apparatus by changing the material or hardness of the bonding end 16-1. That is, the material is Cu (copper) and the hardness is 5 in Vickers hardness (Hv).
Using an alloy of 0, 80, 120, 42 alloy (nickel iron alloy) and phosphor bronze, a weight of 0.15 megapascal (MP
a), the ultrasonic frequency is 40 kHz, the amplitude is 20 μm,
The power was set to 300 w. Note that the upward arrow in the table means that the condition is “same as above”. The results of this experiment indicate whether or not the joint was performed with a satisfactory joining force by “Jointability”, but the 42 alloy was slightly unsatisfactory as compared with other materials. Also, as a result of joining,
Whether or not the ceramic substrate constituting the terminal block 14 is damaged is shown in the column of "Ceramic Damage". However, in the case of Cu with a Vickers hardness of 120 and 42 alloy, damage occurs, and the Cu with a Vickers hardness of 80 is slightly damaged. Damage occurred.
【００１７】表２は同一の接合端部１６−１材料、すな
わち、ビッカース硬度５０のＣｕについて、超音波ボン
ディング装置の動作条件を変化させた場合の実験結果を
示すものである。この実験結果は、表１の場合と同様な
評価基準で示されているが、「接合可否」および「セラ
ミックダメージ」の両者を満足させるためには、超音波
ボンディング装置の動作条件を選定する必要があること
を示している。Table 2 shows the experimental results when the operating conditions of the ultrasonic bonding apparatus were changed for the same material at the bonding end 16-1, that is, Cu having a Vickers hardness of 50. The results of this experiment are shown by the same evaluation criteria as in Table 1, but it is necessary to select the operating conditions of the ultrasonic bonding apparatus in order to satisfy both “whether or not” and “ceramic damage”. It indicates that there is.
【００１８】表３は本発明の超音波ボンディングにより
接合された外部電極端子１６の接合端部１６−１と端子
台１４との接合部の熱サイクル試験の結果を、従来のは
んだ接合の場合と比較して示すものである。すなわち、
接合端部１６−１として幅２．５ｍｍ、厚さ０．８ｍｍ
のＣｕ板を用いて超音波ボンディングにより接合すると
ともに、比較品として同じ寸法のＣｕ板をＰｂ系のはん
だを用いて接合し、これらに対して−４０℃〜１２５℃
の熱サイクル試験を実施した。この結果は表３中に示さ
れるように、はんだ接合の場合には、３００サイクルで
はんだ部にクラックが確認され、強度劣化を生じたが、
本発明の超音波接合部には５００サイクルでもこのよう
な現象は確認されなかった。Table 3 shows the results of a heat cycle test of the joint between the terminal end 14 and the joint end 16-1 of the external electrode terminal 16 joined by the ultrasonic bonding according to the present invention. These are shown in comparison. That is,
2.5 mm wide and 0.8 mm thick as the joining end 16-1
And a Cu plate of the same size as a comparative product by using Pb-based solder, and -40 ° C. to 125 ° C.
Was subjected to a heat cycle test. As shown in Table 3, in the case of the solder joint, the crack was confirmed in the solder part in 300 cycles and the strength was deteriorated.
Such a phenomenon was not confirmed in the ultrasonic bonding portion of the present invention even after 500 cycles.
【００１９】さらに、本発明においては、超音波接合部
の省スペース効果を確認するため、上記幅２．５ｍｍ、
厚さ０．８ｍｍのＣｕ板と同等の電流容量、例えば１５
０Ａの電流を流すために、従来行われていた５００μｍ
の径のアルミワイヤ８本により、外部電極端子１６と端
子台１４との接続を行った。そして両者の接合に必要な
面積を比較したところ、本発明の場合はワイヤボンディ
ングの場合に比較して約１１％の省スペースとなること
が確認された。Further, in the present invention, in order to confirm the space saving effect of the ultrasonic bonding portion, the width 2.5 mm,
Current capacity equivalent to a 0.8 mm thick Cu plate, for example, 15
500 μm conventionally used for flowing a current of 0 A
The external electrode terminal 16 and the terminal block 14 were connected by eight aluminum wires having a diameter of. When the area required for joining the two was compared, it was confirmed that the space saving of about 11% was achieved in the case of the present invention as compared with the case of wire bonding.
【００２０】以上本発明の実施形態について説明した
が、本発明は上記の実施形態に限定されるものではな
く、本発明の請求項に示される技術思想の範囲内で種々
の変形が容易に考えられる。例えば、外部電極端子１６
は全体が板状である必要はなく、少なくも端子台１４に
接触する接合端部１６−１が板状であればよい。また、
その材料や硬度も上記実施形態に限定されるものではな
い。Although the embodiment of the present invention has been described above, the present invention is not limited to the above embodiment, and various modifications can be easily made within the scope of the technical idea shown in the claims of the present invention. Can be For example, the external electrode terminal 16
Does not need to be in the form of a plate as a whole, and it is sufficient if at least the joining end portion 16-1 that contacts the terminal block 14 is in the form of a plate. Also,
The material and hardness are not limited to the above embodiment.
【００２１】さらに、本発明の超音波接合方法は図示の
ような大電力トランジスタに限られず、電流容量の大き
なサイリスタあるいはダイオード等、いわゆる大電力半
導体装置における導体の接合に適用することができる。Further, the ultrasonic bonding method of the present invention is not limited to a high-power transistor as shown in the figure, but can be applied to a so-called high-power semiconductor device such as a thyristor or a diode having a large current capacity.
【００２２】[0022]
【発明の効果】本発明によれば、高い信頼性と省スペー
スを併せ持つ半導体装置およびその製造方法を得ること
ができ、特に、本発明は電気自動車用の大電力半導体装
置のような大電流を要し、厳しい自然環境下で使用され
る装置に適用した場合、顕著な効果が得られる。According to the present invention, it is possible to obtain a semiconductor device having both high reliability and space saving and a method of manufacturing the same. In particular, the present invention provides a semiconductor device having a large electric current such as a high power semiconductor device for an electric vehicle. In short, when applied to a device used in a severe natural environment, a remarkable effect can be obtained.
【図１】本発明の一実施形態である大電力半導体装置の
一部切欠斜視図である。FIG. 1 is a partially cutaway perspective view of a high power semiconductor device according to an embodiment of the present invention.
【図２】図１の装置の要部を拡大して示す斜視図であ
る。FIG. 2 is an enlarged perspective view showing a main part of the apparatus shown in FIG. 1;
【図３】図１に示した半導体装置内部の素子配置を示す
平面図である。FIG. 3 is a plan view showing an element arrangement inside the semiconductor device shown in FIG. 1;
１１ ＤＢＣ基板 １２ 半導体チップ １３ 樹脂ケース １４ 端子台 １５ ボンデイングワイヤ １６ 外部電極端子 １６−１ 接合端部 １６−２ 本体部 １６−３ 接続端部 DESCRIPTION OF SYMBOLS 11 DBC board 12 Semiconductor chip 13 Resin case 14 Terminal block 15 Bonding wire 16 External electrode terminal 16-1 Joining end 16-2 Body 16-3 Connection end
───────────────────────────────────────────────────── フロントページの続き (72)発明者 木本 晶紀 兵庫県姫路市余部区上余部50番地 株式会 社東芝姫路半導体工場内 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Akinori Kimoto Inside the Toshiba Himeji Semiconductor Factory
Claims (6)
の半導体チップの電極端子が電気的に接続されるように
前記基板上に形成された電極端子台と、この電極端子台
に超音波接合によりその一端が接続され、少なくともこ
の一端部が板状の外部電極端子と、この外部電極端子の
一部、前記基板、この基板上に固着された半導体チップ
および電極端子台を収納するパッケージとを備えたこと
を特徴とする半導体装置。1. A semiconductor chip fixed on a substrate, an electrode terminal block formed on the substrate so that electrode terminals of the semiconductor chip are electrically connected, and ultrasonic bonding to the electrode terminal block. At least one end of which is connected to a plate-like external electrode terminal, a part of the external electrode terminal, the substrate, a semiconductor chip fixed on the substrate, and a package containing the electrode terminal block. A semiconductor device, comprising:
半導体チップは電力用半導体チップであり、前記電極端
子台は前記セラミック基板上に形成された銅回路の一部
であり、また、前記外部電極端子の少なくとも前記内部
電極端子に接続される部分は銅または銅合金であること
を特徴とする請求項１記載の半導体装置。2. The method according to claim 1, wherein the substrate is a ceramic substrate, the semiconductor chip is a power semiconductor chip, the electrode terminal block is a part of a copper circuit formed on the ceramic substrate, and the external electrode 2. The semiconductor device according to claim 1, wherein at least a portion of the terminal connected to the internal electrode terminal is made of copper or a copper alloy.
電極端子に接続される部分はピッカース硬度が約８０以
下の金属からなることを特徴とする請求項１記載の半導
体装置。3. The semiconductor device according to claim 1, wherein at least a portion of said external electrode terminal connected to said internal electrode terminal is made of a metal having a Pickers hardness of about 80 or less.
と、この半導体チップの電極端子を前記基板上に固着さ
れた電極端子台に電気的に接続する工程と、この電極端
子台に少なくともその一端が板状の外部電極端子を超音
波接合により接続する工程と、この外部電極端子の一
部、前記基板、この基板上に配置された半導体チップお
よび内部電極端子をパッケージ内に収納する工程とを備
えたことを特徴とする半導体装置の製造方法。4. A step of fixing a semiconductor chip on a substrate, a step of electrically connecting electrode terminals of the semiconductor chip to an electrode terminal block fixed on the substrate, and at least one end of the electrode terminal block. The step of connecting the plate-shaped external electrode terminals by ultrasonic bonding, and the step of housing a part of the external electrode terminals, the substrate, a semiconductor chip disposed on the substrate and the internal electrode terminals in a package. A method for manufacturing a semiconductor device, comprising:
半導体チップは電力用半導体チップであり、前記電極端
子台は前記セラミック基板上に形成された銅回路の一部
であり、また、前記外部電極端子の少なくとも前記内部
電極端子に接続される部分は銅または銅合金であること
を特徴とする請求項４記載の半導体装置の製造方法。5. The substrate is a ceramic substrate, the semiconductor chip is a power semiconductor chip, the electrode terminal block is a part of a copper circuit formed on the ceramic substrate, and the external electrode 5. The method according to claim 4, wherein at least a portion of the terminal connected to the internal electrode terminal is made of copper or a copper alloy.
電極端子に接続される部分はピッカース硬度が約８０以
下の金属からなることを特徴とする請求項４記載の半導
体装置の製造方法。6. The method according to claim 4, wherein at least a portion of the external electrode terminal connected to the internal electrode terminal is made of a metal having a Pickers hardness of about 80 or less.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP36075897A JP3524360B2 (en) | 1997-12-26 | 1997-12-26 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP36075897A JP3524360B2 (en) | 1997-12-26 | 1997-12-26 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH11195725A true JPH11195725A (en) | 1999-07-21 |
| JP3524360B2 JP3524360B2 (en) | 2004-05-10 |
Family
ID=18470797
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP36075897A Expired - Lifetime JP3524360B2 (en) | 1997-12-26 | 1997-12-26 | Semiconductor device and manufacturing method thereof |
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| Country | Link |
|---|---|
| JP (1) | JP3524360B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7446406B2 (en) | 2005-03-30 | 2008-11-04 | Toyota Jidosha Kabushiki Kaisha | Circuit device and manufacturing method thereof |
| JP2011159780A (en) * | 2010-02-01 | 2011-08-18 | Fuji Electric Co Ltd | Semiconductor device and method of manufacturing the same |
| WO2025009318A1 (en) * | 2023-07-05 | 2025-01-09 | 株式会社デンソー | Semiconductor device |
-
1997
- 1997-12-26 JP JP36075897A patent/JP3524360B2/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7446406B2 (en) | 2005-03-30 | 2008-11-04 | Toyota Jidosha Kabushiki Kaisha | Circuit device and manufacturing method thereof |
| JP2011159780A (en) * | 2010-02-01 | 2011-08-18 | Fuji Electric Co Ltd | Semiconductor device and method of manufacturing the same |
| US8860220B2 (en) | 2010-02-01 | 2014-10-14 | Fuji Electric Co., Ltd. | Semiconductor device and method for manufacturing the same |
| WO2025009318A1 (en) * | 2023-07-05 | 2025-01-09 | 株式会社デンソー | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3524360B2 (en) | 2004-05-10 |
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