JPH11176922A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device, where voids are prevented from being caused in a groove, and a parasitic capacitance formed between a wiring or a semiconductor film and a substrate is reduced by a method, wherein a polycrystalline semiconductor film and an insulating film are provided inside a groove formed for element isolation on the surface of a semiconductor substrate. SOLUTION: A groove 104 used for element isolation is cut in the surfaces of N-type epitaxial layers 103a and 103b so as to reach to a P-type silicon substrate 101, an oxide film 106 is formed on the side and base of the groove 104 through thermal oxidation, a polysilicon film 107 is embedded in the lower part of the groove 104, and a CVD oxide film 108 is embedded in the upper part of the groove 104. With this setup, a void-like cavities are prevented from being generated in the groove 104, a parasitic capacitance formed between a wiring over the groove 4 and the P-type silicon substrate 101 can be reduced further than the case, where only a polysilicon film is filled into the groove 104.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to element isolation of a semiconductor integrated circuit device, and more particularly to element isolation of a semiconductor integrated circuit device in which a bipolar transistor and a MOS transistor are formed on the same semiconductor substrate.

[0002]

2. Description of the Related Art Hitherto, in a bipolar integrated circuit or a Bi-CMOS integrated circuit in which a bipolar transistor and a MOS transistor are integrated on the same substrate, a groove is dug in the substrate in order to separate elements between the bipolar transistors. The structure has reduced the parasitic capacitance between the collector substrates of the bipolar transistors. One example of such a conventional semiconductor integrated circuit device is disclosed in JP-A-63-60 / 1988.
No. 553 is proposed.

Hereinafter, an example of this conventional semiconductor integrated circuit device will be described with reference to the drawings. FIG. 5 (a),
FIG. 1B is a cross-sectional view of a first conventional semiconductor integrated circuit device. As shown in FIG. 5A, the P-type silicon substrate 4
The N-type epitaxial layer 403 is formed on the N-type buried layer 402 formed on the surface of No. 01. A groove 404 that penetrates the N-type buried layer 402 from the surface of the N-type epitaxial layer 403 and reaches the P-type silicon substrate 401 is dug. Further, a polysilicon film 406 is embedded via an oxide film 405 on the surface of the groove 404.

A first N-type island region 407 comprising an N-type buried layer 402 and an N-type epitaxial layer 403, and a second N-type island region 408 comprising an N-type buried layer 402 and an N-type epitaxial layer 403 are provided. Are separated by a groove 404.

In FIG. 5B, a polysilicon film 40 is formed.
6 is formed on the surface of the groove 404 filled with
A COS film 409 is formed. Next, JP-A-4-4
An example of a conventional semiconductor integrated circuit device proposed in Japanese Patent No. 4261 will be described. FIGS. 6A to 6C are cross-sectional views in the order of steps of a second conventional example of a semiconductor integrated circuit device. In the step shown in FIG. 6A, the P-type silicon substrate 5
After the N-type buried layer 502 is formed on the surface of
A type epitaxial layer 503 is grown.

Thereafter, a groove 504 is dug by dry etching using a resist opened in a predetermined region as a mask. The groove 504 is formed in the N-type epitaxial layer 503.
It penetrates the N-type buried layer 502 from the surface and reaches the P-type silicon substrate 501. After removing the resist, an oxide film 505 is formed on the surface of the N-type epitaxial layer 503 and the groove 504 by thermal oxidation.

Next, in the step shown in FIG.
After growing a CVD oxide film 506 filling the entire surface, a resist 508 for planarization is applied on the entire surface. In the step shown in FIG. 6C, the surfaces of the resist 508 and the CVD oxide film 506 are removed by etching, and the CV
A groove 504 buried with the D oxide film 506 is formed.

[0008]

However, in the first conventional semiconductor integrated circuit device as described above, FIG.
As shown in (a), the parasitic capacitance between the wiring on the oxide film 405 on the surface of the N-type epitaxial layer 403 and the semiconductor film and the P-type silicon substrate 401 increases due to the interposition of the polysilicon film 406 and the like. There is a problem that the characteristics of the integrated circuit deteriorate.

As shown in FIG. 5B, the surface of the trench 404 filled with the polysilicon film 406 is
When the S film 409 is formed, the polysilicon film 406
Longitudinal bird's beak 410 is formed along oxide film 405 at the boundary between groove and trench 404, and there is a problem in that the yield of semiconductor integrated circuits decreases due to crystal defects caused by stress.

The conventional example shown in FIG. 6 solves the above-mentioned problem. However, as shown in FIGS. 6B and 6C, a CVD oxide film buried in the groove 504 is used. 5
Since the coverage at the time of growth of the semiconductor layer 06 is worse than that of the polysilicon film, there is a problem that when the aspect ratio of the groove 504 is large, a void 507 serving as a cavity is generated. When voids are generated in this way, the manufacturing yield decreases,
The reliability is degraded due to a change in element characteristics or the like.

The present invention has been made to solve the above-mentioned problem, and has a polycrystalline semiconductor film and an insulating film in a trench for element isolation formed on the surface of a semiconductor substrate, thereby generating voids in the trench. It is an object of the present invention to provide a semiconductor integrated circuit device which can prevent the occurrence of a parasitic capacitance and reduce a parasitic capacitance between a wiring or a semiconductor film and a substrate.

[0012]

According to a first aspect of the present invention, there is provided a semiconductor integrated circuit device having a groove for element isolation formed on a surface of a semiconductor substrate, and a groove below the groove. Is characterized in that a polycrystalline semiconductor film is filled, and an upper part of the trench is filled with an insulating film.

According to the semiconductor integrated circuit device as described above, it is possible to prevent the occurrence of void-like cavities in the trench and reduce the parasitic capacitance between the conductive film on the trench and the semiconductor substrate. In the first semiconductor integrated circuit device, it is preferable that the depth of the groove is about 3 to 5 μm and the depth of the insulating film is about 0.3 to 1 μm.

Next, a second semiconductor integrated circuit device according to the present invention includes a first groove and a second groove for element isolation formed on the surface of a semiconductor substrate, The depth is shallower than the depth of the first groove, wherein the first groove is filled with a polycrystalline semiconductor film, and the second groove is filled with an insulating film.

According to the semiconductor integrated circuit device as described above, it is possible to prevent the generation of void-like cavities in the first groove, and the parasitic capacitance between the conductive film on the second groove and the semiconductor substrate. Can be reduced.

In the second semiconductor integrated circuit device, a plurality of bipolar transistors and a plurality of MOS transistors are formed on the surface of the semiconductor substrate, and the first groove is formed between the bipolar transistor and an element adjacent thereto. The second trench is formed for isolation and the MOS
It is preferably formed for element isolation between transistors.

Preferably, a polycrystalline semiconductor film is filled in a lower part of the first groove, and an insulating film is filled in an upper part of the first groove. According to the semiconductor integrated circuit device as described above, it is possible to prevent the generation of void-like cavities in the first groove, and to reduce the parasitic capacitance between the conductive film on the first groove and the semiconductor substrate and the second capacitance. The parasitic capacitance between the conductive film on the groove and the semiconductor substrate can be reduced.

Preferably, the depth of the first groove is about 3 to 5 μm, and the depth of the second groove is about 0.3 to 1 μm. In the first and second semiconductor integrated circuit devices, it is preferable that the polycrystalline semiconductor film is a polysilicon film and the insulating film is a CVD oxide film.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the semiconductor integrated circuit device of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a sectional view of a semiconductor integrated circuit device according to Embodiment 1 of the present invention. The P-type silicon substrate 101 has an impurity boron of 1 × 10 ¹⁵ cm ^−3.
This is a silicon substrate having a degree of plane orientation of (100). The surface concentration of the N-type buried layers 102a and 102b is 1 ×
The diffusion layer is made of arsenic or antimony and has a junction depth of about 10 ¹⁹ cm ^-3 and a junction depth of about 1 μm. Further, the N-type epitaxial layers 103a and 103b are epitaxial layers having a thickness of about 1 μm into which impurities of phosphorus or arsenic are introduced at about 1 × 10 ¹⁶ cm ⁻³ .

The groove 104 is a groove for element isolation.
From the surface of the N-type epitaxial layers 103a and 103b, P
It is dug to reach the mold silicon substrate 101.
The groove width is about 1 μm, and the groove depth is about 3 to 5 μm. A P-type channel stopper layer 105 is formed in the P-type silicon substrate 101 in contact with the bottom surface of the groove 104, and the impurity concentration of boron in the portion in contact with the bottom surface of the groove 104 is about 1 × 10 ¹⁷ cm ⁻³ . The diffusion depth is about 1 μm. The thickness of the oxide film 106 formed by thermally oxidizing the side and bottom surfaces of the groove 104 is about 100 nm.

The lower portion of about 3 to 4 μm from the bottom of the groove 104 is filled with a polysilicon film 107, and the upper part of the groove 104 of about 0.3 to 1 μm is filled with a CVD oxide film 108. The polysilicon film grown by low pressure CVD has a good groove filling rate during the growth, and the CVD oxide film 1
By setting the aspect ratio of the depth of the upper portion of the groove 104 filled in at 08 to the width of the groove 104 to about 1 or less, generation of a void-like cavity can be prevented. By digging the groove 104 to a depth of about 5 μm, the depth of the groove 104 in the P-type silicon substrate 101 of about 1 × 10 ¹⁵ cm ⁻³ is 3 μm.
m. Further, the impurity concentration is 1 × 10 ¹⁷ cm ^−3.
Since the P-type channel stopper layer 105 is formed to a degree, the first N-type island region 10 separated by the groove 104 is formed.
9 and the second N-type island region 110,
It becomes 10V or more.

The upper portion of the groove 104 has a thickness of 0.3 to 1 μm.
Since the trench 104 is filled with only the polysilicon film, the parasitic capacitance between the wiring (not shown) on the trench 104 and the P-type silicon substrate 101 is buried with the CVD oxide film 108 of about m. Can be reduced.

FIGS. 2 (a) to 2 (c), 3 (a) to 3 (c)
4A to 4C are cross-sectional views in the order of steps of the semiconductor integrated circuit device according to the first embodiment of the present invention. First, in the step shown in FIG. 2A, arsenic or antimony is implanted at a dose of about 1 × 10 ¹⁵ cm ^{−2 over the} entire surface of a P-type silicon substrate 201 in which boron is introduced and the plane orientation is (100). Energy 40 Ke
Ion implantation is performed at about V. Then, at about 1150 ° C, 3
Heat treatment for about 0 minutes, surface concentration of 1 × 10 ¹⁹ cm ^-2
An N-type buried layer 202 having a junction depth of about 1 μm is formed.

Next, on the surface of the P-type silicon substrate 201,
The thickness is about 1 μm and the impurity of phosphorus or arsenic is 1 × 1
The N-type epitaxial layer 203 introduced at about 0 ¹⁶ cm ^-3 is grown. The N-type epitaxial layer 203 is formed by using a mixed gas of dichlorosilane and arsine when the impurity is arsenic at a temperature of 1050 ° C. and a pressure of 80 × 133.32.
It grows at about 2 Pa.

Next, in the step shown in FIG. 2 (b), a resist pattern (not shown) having an element isolation region opened by photolithography is used as a mask in a mixed gas of chlorine, hydrogen bromide and oxygen. Type epitaxial layer 203a,
203b, N-type buried layers 202a and 202b, and P
Mold silicon substrate 201 is anisotropically etched. By this etching, a groove 205 having a width of about 1 μm and a depth of about 3 to 5 μm is formed so as to reach the P-type silicon substrate 201.

Next, using the resist pattern used when the trench 205 was selectively etched as a mask, boron was implanted at a dose of about 1 × 10 ¹³ cm ⁻² and an implantation energy of 40K.
Ion implantation is performed at about eV, and the P-type channel stopper layer 20 is formed.
6 is formed in the P-type silicon substrate 201 in contact with the bottom of the groove 205. Thereafter, the resist is removed by plasma ashing in an oxygen gas atmosphere.

Further, at 900 ° C., 30 ° C. in an oxygen atmosphere.
The oxide film 20 is formed on the side and bottom surfaces of the trench 205 and on the surfaces of the N-type epitaxial layers 203a and 203b by oxidation for about one minute.
4, 207 are formed. Due to this heat treatment for oxidation, the P-type channel stopper layer 206 has an impurity concentration at a portion in contact with the bottom of the groove 205 of about 1 × 10 ¹⁷ cm ⁻³ and a diffusion depth of about 1 μm.

Next, in the step shown in FIG. 2C, the polysilicon film 20 is formed by a low pressure CVD method using silane gas.
8 with a thickness of about 1 μm and an N-type epitaxial layer 203.
a, 203b are grown on the entire surface of the oxide film 207 on the surface.
By setting the thickness of the polysilicon film 208 when it is grown to be substantially the same as the width of the trench 205 (about 1 μm in the present embodiment), the trench 205 is sufficiently buried and, at the same time, the polysilicon film 208 after growth is grown. The surface can be sufficiently flattened, and a good filling shape can be obtained.

Next, in the step shown in FIG. 3A, on the oxide film 207 on the surface of the N-type epitaxial layers 203a and 203b by dry etching in a mixed gas of sulfur fluoride and chlorofluorocarbon. Polysilicon film 20
8 is removed, and the polysilicon film 208 of about 1 μm in the upper portion of the portion buried in the trench 205 is removed, so that the lower portion of the trench 205 having a depth of about 3 to 5 μm is removed.
A polysilicon film 209 filling about 4 μm is formed.

Next, in the step shown in FIG. 3B, the oxide film 2 on the surface of the N-type epitaxial layers 203a and 203b is formed.
07 in a mixed gas of TEOS and oxygen at a temperature of about 700 ° C. under reduced pressure CVD to a thickness of 0.3 to 1 μm.
A m-thick CVD oxide film 210 is grown. Then, C
A resist 211 is applied with a thickness of about 2 μm on the entire surface of the VD oxide film 210 in order to flatten the CVD oxide film 210.

Next, in the step shown in FIG. 3C, the oxide film on the surface of the N-type epitaxial layers 203a and 203b is formed following the resist 211 by dry etching in a mixed gas of chlorofluorocarbon, argon and oxygen. CV on 207
By removing the D oxide film 210, a CVD oxide film 212 filling the upper portion of the groove 205 is formed.

Since only about 0.3 to 1 μm above the groove 205 is filled with the CVD oxide film 212, the aspect ratio of the depth of the upper part of the groove 205 filled with the CVD oxide film 212 to the width of the groove 205 is about 1. Since the following can be achieved, the generation of void-like cavities can be prevented, and a reduction in manufacturing yield and a reduction in reliability can be prevented. Also,
Wiring (not shown) on groove 205 and P-type silicon substrate 20
1 can be reduced as compared with the case where the trench 205 is filled only with the polysilicon film.

(Embodiment 2) Next, Embodiment 2 of the present invention will be described with reference to the drawings. FIG. 4 is a sectional view of a semiconductor integrated circuit device according to Embodiment 2 of the present invention. As in the first embodiment, the N-type buried layers 311a to 311c on the surface of the P-type silicon substrate 301 have a surface concentration of 1 ×
Junction depth of about 10 ¹⁹ cm ^-3 is diffused layer about 1 [mu] m. The N-type epitaxial layer 312 contains 1 × 10
^This is an epitaxial layer having a thickness of about 1 μm introduced at about ¹⁶ cm ⁻³ . Groove 3 for bipolar transistor isolation
05a and 305b have a width of about 1 μm and a depth of about 3 to 5 μm, and are dug so as to reach the P-type silicon substrate 301 from the surface of the N-type epitaxial layer 312.

On the other hand, a trench 307 for isolation within a bipolar transistor and a trench 3 for isolation between MOS transistors are provided.
06a and 306b have a width of about 1 μm and a depth of 0.3 to 1 μm
And is dug in the N-type epitaxial layer 312. Groove 305 for bipolar transistor isolation
In the P-type silicon substrate 301 in contact with the bottom surfaces of the a and 305b, trenches 305 for separating bipolar transistors are provided.
a, the impurity concentration of the portion in contact with the bottom surface of 305b is 1 × 1
P-type channel stopper layers 308a and 308b having a diffusion depth of about 1 μm and about 0 ¹⁷ cm ⁻³ are formed.

The grooves 305a and 305b, the groove 307,
Then, the side and bottom surfaces of the grooves 306a and 306b are thermally oxidized to form oxide films 321a to 321e, and their thickness is about 100 nm.

Groove 3 for bipolar transistor isolation
In portions 05a and 305b, polysilicon films 322a and 322b are buried in lower portions of about 3 to 4 μm from the bottom of each groove, respectively. Further, a portion having a depth of about 0.3 to 1 μm above the trenches 305a and 305b, a trench 307 for isolation within a bipolar transistor, and trenches 306a and 306b for isolation between MOS transistors are respectively C
VD oxide films 323a to 323e are embedded.

For this reason, as in the first embodiment, the decompression CV
The polysilicon film grown in D has a good groove filling rate when grown, and the CVD oxide films 323a to 323e.
Ratio of each groove depth to fill each groove width to 1
By setting the degree to be equal to or less than the degree, it is possible to prevent generation of void-like cavities. Each groove has a thickness of 0.3-1μ.
Since about m m of CVD oxide films 323a to 323e are buried, the parasitic capacitance between the wiring (not shown) on each groove and the P-type silicon substrate 301 is also reduced when each groove is filled with only the polysilicon film. Can be reduced.

Here, regions separated by trenches 305a and 305b for bipolar transistor separation include:
An NPN transistor 302 is formed. This NP
The N transistor 302 includes a base layer 335, oxide films 336a and 336b on the surface, an emitter layer 355 formed in the base layer 335, an emitter electrode opening 341 formed on the emitter layer 355, and polysilicon on the emitter electrode opening 341. , An external base layer 353, and a collector contact layer 351.

Since the grooves 305a and 305b are formed so as to reach the P-type silicon substrate 301, the NPN transistor 302 is completely separated from the periphery as an N-type island region. Further, the NPN transistor 302 is formed by the trench 307 for separating the inside of the bipolar transistor.
The base layer 335 and the collector contact layer 351 are separated from each other. This separation is to suppress the operation of the parasitic element near the surface and the leakage of the channel property.
The groove 307 is formed only on the surface of the N-type epitaxial layer 312.

The first and second regions separated by the trenches 306a and 306b for separating the MOS transistors have the first
PchMOS transistor 303 and second PchM
An OS transistor 304 is formed.

First PchMOS transistor 303
Are an N-type well layer 331a, a Pch threshold control injection layer 333a, a gate oxide film 337a, and a gate oxide film 337.
a gate electrode 34 made of polysilicon formed on
3a, a PchS / D layer 354a.

Also, the second PchMOS transistor 3
04 denotes an N-type well layer 331b, a Pch threshold control injection layer 333b, a gate oxide film 337b, and a gate oxide film 3
A gate electrode 343b made of polysilicon and a PchS / D layer 354b are formed on 37b. Further, a groove 306 for separating between MOS transistors is used.
a and 306b are also formed only on the surface of the N-type epitaxial layer 312.

As described above, according to the present embodiment, it is possible to prevent the production yield and the reliability from being lowered by preventing the occurrence of void-like cavities in the trenches for element isolation, and to further prevent the wiring between the wiring board and the substrate. And a Bi-CMOS integrated circuit device having two types of element isolation trenches for isolating between bipolar transistors and for isolating between MOS transistors, which can reduce the parasitic capacitance of the device.

[0045]

As described above, according to the semiconductor integrated circuit device of the present invention, by providing the polycrystalline semiconductor film and the insulating film in the trench for element isolation formed on the surface of the semiconductor substrate, Can be prevented, and the parasitic capacitance between the wiring and the semiconductor film and the substrate can be reduced.

Further, the semiconductor device has a first groove and a second groove formed on the surface of the semiconductor substrate for element isolation, and the depth of the second groove is smaller than the depth of the first groove. The trenches are filled with a polycrystalline semiconductor film, and the second trenches are filled with an insulating film to prevent voids in the trenches and to prevent parasitic wiring between the wiring and the semiconductor film and the substrate. A semiconductor integrated circuit device including a plurality of bipolar transistors and a plurality of MOS transistors whose capacity can be reduced can be obtained.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor integrated circuit device according to a first embodiment of the present invention;

FIG. 2 is a sectional view of a semiconductor integrated circuit device according to Embodiment 1 of the present invention in the order of steps.

FIG. 3 is a sectional view of the semiconductor integrated circuit device according to the first embodiment of the present invention in the order of steps;

FIG. 4 is a sectional view of a semiconductor integrated circuit device according to a second embodiment of the present invention;

FIG. 5 is a sectional view of an example of a conventional semiconductor integrated circuit device.

FIG. 6 is a sectional view in the order of steps of an example of a conventional semiconductor integrated circuit device.

[Explanation of symbols]

101 P-type silicon substrate 102a, 102b N-type buried layer 103a, 103b N-type epitaxial layer 104 groove 105 P-type channel stopper layer 106 oxide film 107 polysilicon film 108 CVD oxide film 109 first N-type island region 110 second N-type island region 201 P-type silicon substrate 202, 202a, 202b N-type buried layer 203, 203a, 203b N-type epitaxial layer 204, 207 Oxide film 205 Groove 206 P-type channel stopper layer 208, 209 Polysilicon film 210, 212 CVD Oxide film 211 Resist 213 First N-type island region 214 Second N-type island region 301 P-type silicon substrate 302 NPN transistor 303 First PchMOS transistor 304 Second PchMOS transistor 311a, 311b, 11c N-type buried layer 312 N-type epitaxial layer 305a, 305b Groove for bipolar transistor isolation 307 Groove for bipolar transistor isolation 306a, 306b Groove for MOS transistor isolation 308a, 308b P-type channel stopper layer 321a, 321b , 321c, 321d, 321e
Oxide films 322a, 322b Polysilicon films 323a, 323b, 323c, 323d, 323e
CVD oxide film 331a, 331b N-type well layer 333a, 333b Pch threshold value control injection layer 335 Base layer 336a, 336b Oxide film 337a, 337b Gate oxide film 355 Emitter layer 341 Emitter electrode opening 342 Emitter electrode 343a, 343b Gate electrode 353 External Base layer 354a, 354b PchS / D layer 351 Collector contact layer

Claims (7)

[Claims] 1. A semiconductor device comprising: a trench for element isolation formed on a surface of a semiconductor substrate; a lower portion of the trench being filled with a polycrystalline semiconductor film, and an upper portion of the trench being filled with an insulating film. A semiconductor integrated circuit device characterized by the above-mentioned. 2. The semiconductor integrated circuit device according to claim 1, wherein the depth of the groove is about 3 to 5 μm, and the depth of the insulating film is about 0.3 to 1 μm. 3. A semiconductor device comprising: a first groove and a second groove for element isolation formed on a surface of a semiconductor substrate, wherein a depth of the second groove is smaller than a depth of the first groove; 2. The semiconductor integrated circuit device according to claim 1, wherein the first groove is filled with a polycrystalline semiconductor film, and the second groove is filled with an insulating film. 4. A plurality of bipolar transistors and a plurality of MOS transistors are formed on a surface of a semiconductor substrate, the first trench is formed for separating the bipolar transistor from an element adjacent thereto, and the second trench is formed. 4. The semiconductor integrated circuit device according to claim 3, wherein said groove is formed for element isolation between said MOS transistors. 5. The semiconductor integrated circuit device according to claim 3, wherein a lower portion of said first trench is filled with a polycrystalline semiconductor film, and an upper portion of said first trench is filled with an insulating film. 6. The semiconductor integrated circuit according to claim 3, wherein the depth of the first groove is about 3 to 5 μm, and the depth of the second groove is about 0.3 to 1 μm. Circuit device 7. The semiconductor integrated circuit device according to claim 1, wherein said polycrystalline semiconductor film is a polysilicon film, and said insulating film is a CVD oxide film.