JPH0427704B2 - - Google Patents
Info
- Publication number
- JPH0427704B2 JPH0427704B2 JP58195969A JP19596983A JPH0427704B2 JP H0427704 B2 JPH0427704 B2 JP H0427704B2 JP 58195969 A JP58195969 A JP 58195969A JP 19596983 A JP19596983 A JP 19596983A JP H0427704 B2 JPH0427704 B2 JP H0427704B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- groove
- polycrystalline
- trench
- polycrystalline silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 29
- 239000000758 substrate Substances 0.000 claims description 12
- 239000004065 semiconductor Substances 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 2
- 238000000034 method Methods 0.000 description 13
- 229910004298 SiO 2 Inorganic materials 0.000 description 9
- 238000005530 etching Methods 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 238000002048 anodisation reaction Methods 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000005546 reactive sputtering Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/763—Polycrystalline semiconductor regions
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は半導体集積回路、詳しくは、Siをエツ
チングして形成した溝に絶縁物を介して多結晶Si
を埋込んでアイソレーシヨンを行なつた半導体装
置の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to semiconductor integrated circuits, and more particularly, to semiconductor integrated circuits, in which polycrystalline silicon is injected into grooves formed by etching Si through an insulator.
The present invention relates to a method of manufacturing a semiconductor device in which isolation is performed by embedding a semiconductor device.
半導体基板表面に形成した溝により、半導体素
子のアイソレーシヨンを行う溝アイソレーシヨン
構造が知られている。この場合多くは、溝の上か
ら多結晶Si等を堆積して溝を充填する。このとき
溝が完全には充填されずに溝内に空洞が形成され
やすい等の欠点があつた。
2. Description of the Related Art Groove isolation structures are known in which semiconductor elements are isolated by grooves formed on the surface of a semiconductor substrate. In many cases, the grooves are filled by depositing polycrystalline Si or the like from above the grooves. At this time, there were drawbacks such as the grooves not being completely filled and cavities being likely to be formed within the grooves.
溝内に多結晶シリコンを充填する１方法につい
て、本願発明者等は本願の先願である特願昭54−
43020号公報において開示している。以下要点を
簡単に説明する。 Regarding one method of filling polycrystalline silicon into the groove, the inventors of the present application have disclosed a method of filling polycrystalline silicon into the trench in Japanese Patent Application No.
It is disclosed in Publication No. 43020. The main points will be briefly explained below.
はじめにシリコン基板上に形成した絶縁膜をマ
スクにしてシリコン基板をエツチングし、溝を形
成する。つぎに溝内のシリコンを若干エツチング
して上記絶縁膜のひさしを作る。 First, the silicon substrate is etched using an insulating film formed on the silicon substrate as a mask to form a groove. Next, the silicon in the groove is slightly etched to form the eaves of the insulating film.
つぎに多結晶シリコンを上から堆積し、溝底と
溝外の多結晶シリコンを段切れさせて堆積する。 Next, polycrystalline silicon is deposited from above, and the polycrystalline silicon at the bottom of the groove and outside the groove is separated and deposited.
つぎに溝底がウエハ内で切れ目なくつながつて
いることを利用し、溝底の多結晶シリコンの表面
に陽極酸化等の選択的な処理を行う。これにより
溝外の多結晶シリコンを除去する。 Next, taking advantage of the fact that the groove bottoms are seamlessly connected within the wafer, selective treatment such as anodization is performed on the polycrystalline silicon surface at the groove bottom. This removes polycrystalline silicon outside the groove.
つぎに溝底の多結晶シリコンを種にして多結晶
シリコンを選択成長させ、溝を充填する。 Next, using the polycrystalline silicon at the bottom of the trench as a seed, polycrystalline silicon is selectively grown to fill the trench.
以上紹介した選択成長による溝充填方法は、溝
底からの選択成長によつて充填物質を形成するた
め、溝内が確実に充填されやすい利点がある。し
かし、多結晶シリコンを基板表面より上まで埋込
もうとすると、多結晶シリコンが絶縁膜のひさし
につかえ、ひさしの直下に空洞が発生することが
あるという欠点があつた。 The trench filling method using selective growth introduced above has the advantage that the inside of the trench is easily filled because the filling material is formed by selective growth from the bottom of the trench. However, when attempting to bury polycrystalline silicon above the surface of the substrate, the polycrystalline silicon gets stuck in the eaves of the insulating film, resulting in the formation of a cavity directly under the eaves.
従つて、絶縁膜を除去した後、空洞のあつた個
所に落ちこみが生じることがあるという欠点があ
つた。 Therefore, after removing the insulating film, there is a drawback that depressions may be formed in the areas where the cavities were.
本発明は、溝上部のSiを逆テーパ状にエツチン
グすることによつて、Si3N4膜のひさしを不要に
すると共に、溝端部の多結晶Siの落込みを防ぎ、
トランジスタを形成する後の工程に適した形状を
提供することが出来る。
The present invention eliminates the need for the Si 3 N 4 film eaves by etching the Si at the top of the groove in a reverse taper shape, and prevents the polycrystalline Si at the edge of the groove from falling.
It is possible to provide a shape suitable for the subsequent process of forming a transistor.
以下、本発明をバイポーラ集積回路の製造に適
用した実施例を用いて詳細に説明する。
Hereinafter, the present invention will be explained in detail using an example in which the present invention is applied to manufacturing a bipolar integrated circuit.
コレクタ埋込層２を設けた面方位（100）のSi
基板１の上にトランジスタの能動部分となるSiエ
ピタキシヤル層３を形成し、その表面を熱酸化し
てSiO2膜４を形成した。SiO2膜４を通常のホト
エツチング法でパターニングした後、SiO2膜４
をマスクにして、反応性スパツタ法でSiをエツチ
ングし垂直な溝５を形成した（第１図）。次にア
ルカリ系の異方性エツチング液を用いてSiをエツ
チングし逆テーパ形状の溝を形成した（第２図）。 (100) Si with collector buried layer 2
A Si epitaxial layer 3 serving as an active part of a transistor was formed on a substrate 1, and its surface was thermally oxidized to form an SiO 2 film 4. After patterning the SiO 2 film 4 using a normal photoetching method, the SiO 2 film 4 is
Using this as a mask, the Si was etched using a reactive sputtering method to form vertical grooves 5 (Fig. 1). Next, the Si was etched using an alkaline anisotropic etching solution to form a reversely tapered groove (Figure 2).
次にチヤネル発生防止の目的で埋込層２と反対
の電導性を持つ不純物をイオン打込み法で溝の底
面に導入した。N2中でアニールした後、SiO2膜
４を除去し、酸化してSiO2膜６を形成しさらに
Si3N4膜７を形成した。多結晶Si膜を蒸着もしく
はスパツタリングによつて上記溝の底面および上
記基板の表面上に形成した。この後、陽極酸化法
によつて、上記多結晶Si膜のうち、上記基板の表
面上に形成された部分を除去し、第３図に示した
ように、上記溝の底部に形成された部分８を残し
た。上記溝底部の多結晶シリコン膜８を種に用い
て、多結晶Si９を選択的に成長させ、上記溝内を
充填した。多結晶Si９を基板表面より上に成長し
ても、端部１０での落込みは発生しなかつた。多
結晶Si９の表面を酸化した後、能動層表面のSi3
N4膜７を除去し、再び全面にSi3N4膜を形成して
表面を安定化し、能動層３にトランジスタを形成
した。溝より上部の多結晶Siを酸化したのでSi層
１〜３に加わる圧力は小さく結晶欠陥はほとんど
発生しなかつた。また、端部１０でSi層３の形状
が逆テーパになつているため、この端部を用いて
ベース領域やエミツタ領域の窓開けをセルフアラ
イメントで行なつてもエミツタ領域の形状異常
（落ち込み）が起こりにくく、Walled−emitter
構造のトランジスタを製作するのに好都合であ
る。このため、溝分離方式とWalled−emitter構
造を組合せることによつてアイソプレーナ方式の
LSIに比べて約２倍の集積度が得られた。 Next, for the purpose of preventing channel generation, an impurity having conductivity opposite to that of the buried layer 2 was introduced into the bottom surface of the trench by ion implantation. After annealing in N2 , the SiO2 film 4 is removed, oxidized to form a SiO2 film 6, and further
A Si 3 N 4 film 7 was formed. A polycrystalline Si film was formed on the bottom of the groove and the surface of the substrate by vapor deposition or sputtering. Thereafter, the portion of the polycrystalline Si film formed on the surface of the substrate is removed by anodization, and the portion formed at the bottom of the groove is removed as shown in FIG. 8 left. Using the polycrystalline silicon film 8 at the bottom of the trench as a seed, polycrystalline Si 9 was selectively grown to fill the inside of the trench. Even when the polycrystalline Si 9 was grown above the substrate surface, no depression occurred at the end 10. After oxidizing the surface of polycrystalline Si9, Si3 on the active layer surface
The N 4 film 7 was removed, a Si 3 N 4 film was again formed on the entire surface to stabilize the surface, and a transistor was formed in the active layer 3. Since the polycrystalline Si above the grooves was oxidized, the pressure applied to Si layers 1 to 3 was small and almost no crystal defects were generated. In addition, since the shape of the Si layer 3 is reversely tapered at the end 10, even if the base region and emitter region are opened using self-alignment using this end, the shape of the emitter region will be abnormal (depression). Walled-emitter
This is advantageous for manufacturing transistors with this structure. Therefore, by combining the groove separation method and the walled-emitter structure, the isoplanar method
The degree of integration was approximately twice that of LSI.
本実施例においては、面方位（100）のSi基板
を用いているが、Siのエツチングに他の方方（例
えばマイクロ波プラズマ法）を用いて、第４図の
ような断面形状を得れば、どの面方位の基板を用
いても本発明の実施は可能である。 In this example, a Si substrate with a (100) plane orientation is used, but it is also possible to obtain the cross-sectional shape shown in Figure 4 by etching the Si using another method (for example, microwave plasma method). For example, the present invention can be implemented using a substrate of any plane orientation.
アイソプレーナ方式の長所の１つは、選択酸化
後の平面寸法がSiN膜の加工寸法によつて決定さ
れるので、絶対値の変動はあつてもチツプ内の寸
法ばらつきが小さいことである。これに対して、
Siをエツチングして形成した溝に多結晶Siを埋込
む方式では、埋込後の平面寸法が多結晶Siの厚さ
の影響を受ける欠点がある。しかし、本発明を用
いると、第５図（第３図の部分拡大図）に示すよ
うに、多結晶Si９の厚さの影響を受けないように
出来る。すなわち、表面と溝の内面に形成した
SiO2膜７を合せた膜厚をｔとし、エピタキシヤ
ル成長層の表面と同じ高さの多結晶Si表面１１よ
り（π／２）ｔだけ高い表面を１２、表面１１よ
りｔだけ低い表面を１３とすると、多結晶Siの厚
さが表面１２と表面１３の間にあれば、多結晶Si
９をマスクにしてSi3N4膜７およびSiO2６をエツ
チングしても開口部の平面寸法は変化しない。以
上の見積では第５図において、溝の上端部を被覆
しているSi3N4膜の曲率半径を、おおよそｔとみ
なす。このときSi3N4膜の曲率円に沿つて、水平
から垂直まで回り込む円周距離は、おおよそ
（π／２）ｔである。このため粗い目安として、
溝の中央部で（π／２）ｔの成長をすれば、溝の
上端部でほぼ真上まで回り込んで成長するとみな
している。
One of the advantages of the isoplanar method is that the planar dimensions after selective oxidation are determined by the processed dimensions of the SiN film, so even if the absolute value varies, the variation in dimensions within the chip is small. On the contrary,
The method of embedding polycrystalline Si into a groove formed by etching Si has the disadvantage that the planar dimensions after embedding are affected by the thickness of the polycrystalline Si. However, by using the present invention, as shown in FIG. 5 (a partially enlarged view of FIG. 3), it is possible to avoid being influenced by the thickness of polycrystalline Si 9. In other words, the surface and inner surface of the groove are
The combined film thickness of the SiO 2 film 7 is t, the surface 12 is higher by (π/2)t than the polycrystalline Si surface 11 which is at the same height as the surface of the epitaxial growth layer, and the surface is lower by t than the surface 11. 13, if the thickness of polycrystalline Si is between surface 12 and surface 13, polycrystalline Si
Even if the Si 3 N 4 film 7 and the SiO 2 6 are etched using the mask 9 as a mask, the planar dimensions of the opening do not change. In the above estimation, the radius of curvature of the Si 3 N 4 film covering the upper end of the groove in FIG. 5 is assumed to be approximately t. At this time, the circumferential distance from horizontal to vertical along the circle of curvature of the Si 3 N 4 film is approximately (π/2)t. For this reason, as a rough guide,
It is assumed that if growth of (π/2)t occurs at the center of the groove, the growth will wrap around to almost directly above the upper end of the groove.
一方、積極的に選択酸化法を用いて平面寸法の
ばらつきを押えることも可能である。そのために
はSiをエツチングするマスクとして第１図の
SiO2膜４の代わりに、第６図のようにSi3N4膜１
５およびSiO2膜１４を用い、Siエツチング後に
選択酸化を行なつて、第３図のSiO2膜６の代わ
りに、第７図のSiO2膜１６を形成すればよい。
残つたSi3N4膜１５はリン酸で除去し再び全面に
Si3N4膜を形成すれば第３図と同様の構成とな
る。 On the other hand, it is also possible to actively use a selective oxidation method to suppress variations in planar dimensions. For this purpose, the mask shown in Figure 1 is used as a mask for etching Si.
Instead of SiO 2 film 4, Si 3 N 4 film 1 is used as shown in Figure 6.
5 and the SiO 2 film 14, selective oxidation may be performed after Si etching to form the SiO 2 film 16 shown in FIG. 7 in place of the SiO 2 film 6 shown in FIG. 3.
The remaining Si 3 N 4 film 15 is removed with phosphoric acid and the entire surface is covered again.
If a Si 3 N 4 film is formed, a structure similar to that shown in FIG. 3 will be obtained.
第１図、第２図、第３図は本発明の半導体集積
回路装置の実施例の製造方法を工程順に示す断面
図、第４図は本発明の他の実施例を示す断面図、
第５図は第３図の部分拡大図、第６図、第７図は
本発明の半導体集積回路装置の他の実施例を示す
断面図である。
１……Si基板、２……コレクタ埋込層、３……
Siエピタキシヤル層、４……SiO膜、５……溝、
６……SiO膜、７……SiN膜、８，９……多結晶
Si。
1, 2, and 3 are cross-sectional views showing a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention in order of steps, and FIG. 4 is a cross-sectional view showing another embodiment of the present invention.
FIG. 5 is a partially enlarged view of FIG. 3, and FIGS. 6 and 7 are cross-sectional views showing other embodiments of the semiconductor integrated circuit device of the present invention. 1... Si substrate, 2... Collector buried layer, 3...
Si epitaxial layer, 4... SiO film, 5... groove,
6...SiO film, 7...SiN film, 8,9...polycrystalline
Si.
Claims (1)
近の内径が上端付近より深い部分の内径よりも小
さく形成されてなる溝を形成する工程と、 該溝の内側に絶縁膜を被着する工程と、 該絶縁膜の内側の上記溝の底部に多結晶シリコ
ン層を形成する工程と、 上記溝の底部の上記多結晶シリコン層を種にし
て多結晶シリコンを選択成長させて上記溝を充填
する工程とを含んでなることを特徴とする半導体
装置の製造方法。[Claims] 1. A step of forming a groove that is dug downward from the surface of a silicon substrate and has an inner diameter near the upper end smaller than an inner diameter of a deeper part than near the upper end, and forming an insulating film inside the groove. a step of depositing a polycrystalline silicon layer at the bottom of the trench inside the insulating film; and a step of selectively growing polycrystalline silicon using the polycrystalline silicon layer at the bottom of the trench as a seed. 1. A method of manufacturing a semiconductor device, comprising the step of filling a trench.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19596983A JPS59145538A (en) | 1983-10-21 | 1983-10-21 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19596983A JPS59145538A (en) | 1983-10-21 | 1983-10-21 | Semiconductor integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59145538A JPS59145538A (en) | 1984-08-21 |
| JPH0427704B2 true JPH0427704B2 (en) | 1992-05-12 |
Family
ID=16350000
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19596983A Granted JPS59145538A (en) | 1983-10-21 | 1983-10-21 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59145538A (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6909151B2 (en) | 2003-06-27 | 2005-06-21 | Intel Corporation | Nonplanar device with stress incorporation layer and method of fabrication |
| US7348284B2 (en) | 2004-08-10 | 2008-03-25 | Intel Corporation | Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow |
| US7422946B2 (en) | 2004-09-29 | 2008-09-09 | Intel Corporation | Independently accessed double-gate and tri-gate transistors in same process flow |
| US20060086977A1 (en) | 2004-10-25 | 2006-04-27 | Uday Shah | Nonplanar device with thinned lower body portion and method of fabrication |
| US7518196B2 (en) | 2005-02-23 | 2009-04-14 | Intel Corporation | Field effect transistor with narrow bandgap source and drain regions and method of fabrication |
| US7858481B2 (en) | 2005-06-15 | 2010-12-28 | Intel Corporation | Method for fabricating transistor with thinned channel |
| US7547637B2 (en) * | 2005-06-21 | 2009-06-16 | Intel Corporation | Methods for patterning a semiconductor film |
| US8362566B2 (en) | 2008-06-23 | 2013-01-29 | Intel Corporation | Stress in trigate devices using complimentary gate fill materials |
| JP2012151491A (en) * | 2012-03-22 | 2012-08-09 | Renesas Electronics Corp | Semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53129589A (en) * | 1977-04-18 | 1978-11-11 | Fujitsu Ltd | Integrated circuit unit |
| JPS54154283A (en) * | 1978-05-25 | 1979-12-05 | Ibm | Lateral transistor structure |
-
1983
- 1983-10-21 JP JP19596983A patent/JPS59145538A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53129589A (en) * | 1977-04-18 | 1978-11-11 | Fujitsu Ltd | Integrated circuit unit |
| JPS54154283A (en) * | 1978-05-25 | 1979-12-05 | Ibm | Lateral transistor structure |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59145538A (en) | 1984-08-21 |
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