JPH11175198A5 - - Google Patents

Info

Publication number
JPH11175198A5
JPH11175198A5 JP1998147743A JP14774398A JPH11175198A5 JP H11175198 A5 JPH11175198 A5 JP H11175198A5 JP 1998147743 A JP1998147743 A JP 1998147743A JP 14774398 A JP14774398 A JP 14774398A JP H11175198 A5 JPH11175198 A5 JP H11175198A5
Authority
JP
Japan
Prior art keywords
clock
network
reset signal
signal
power
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1998147743A
Other languages
English (en)
Japanese (ja)
Other versions
JP4129314B2 (ja
JPH11175198A (ja
Filing date
Publication date
Priority claimed from US08/961,190 external-priority patent/US5938728A/en
Application filed filed Critical
Publication of JPH11175198A publication Critical patent/JPH11175198A/ja
Publication of JPH11175198A5 publication Critical patent/JPH11175198A5/ja
Application granted granted Critical
Publication of JP4129314B2 publication Critical patent/JP4129314B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

JP14774398A 1997-10-30 1998-05-28 ネットワークインタフェース、ネットワークインタフェースを初期化するための装置およびネットワークインタフェース内に構成情報をロードする方法 Expired - Fee Related JP4129314B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/961190 1997-10-30
US08/961,190 US5938728A (en) 1997-10-30 1997-10-30 Apparatus and method for selectively controlling clocking and resetting of a network interface

Publications (3)

Publication Number Publication Date
JPH11175198A JPH11175198A (ja) 1999-07-02
JPH11175198A5 true JPH11175198A5 (https=) 2005-09-29
JP4129314B2 JP4129314B2 (ja) 2008-08-06

Family

ID=25504180

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14774398A Expired - Fee Related JP4129314B2 (ja) 1997-10-30 1998-05-28 ネットワークインタフェース、ネットワークインタフェースを初期化するための装置およびネットワークインタフェース内に構成情報をロードする方法

Country Status (3)

Country Link
US (1) US5938728A (https=)
JP (1) JP4129314B2 (https=)
GB (1) GB2330963B (https=)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6393548B1 (en) * 1997-02-14 2002-05-21 Advanced Micro Devices, Inc. Variable 16 or 32 bit PCI interface which supports steering and swapping of data
US6662234B2 (en) 1998-03-26 2003-12-09 National Semiconductor Corporation Transmitting data from a host computer in a reduced power state by an isolation block that disconnects the media access control layer from the physical layer
US6697954B1 (en) * 1999-01-08 2004-02-24 Compaq Computer Corporation Method/apparatus for preserving state of an event during powerup reset sequence based on state of an event signal immediately prior to the reset
US6311284B1 (en) * 1999-03-15 2001-10-30 Advanced Micro Devices, Inc. Using an independent clock to coordinate access to registers by a peripheral device and a host system
US7213061B1 (en) 1999-04-29 2007-05-01 Amx Llc Internet control system and method
US6636912B2 (en) * 1999-10-07 2003-10-21 Intel Corporation Method and apparatus for mode selection in a computer system
US7257079B1 (en) 1999-12-23 2007-08-14 Intel Corporation Physical layer and data link interface with adaptive speed
US6795881B1 (en) 1999-12-23 2004-09-21 Intel Corporation Physical layer and data link interface with ethernet pre-negotiation
US6718417B1 (en) * 1999-12-23 2004-04-06 Intel Corporation Physical layer and data link interface with flexible bus width
US6782001B1 (en) 1999-12-23 2004-08-24 Intel Corporation Physical layer and data link interface with reset/sync sharing
JPWO2001048615A1 (ja) * 1999-12-27 2004-01-08 富士ゼロックス株式会社 プリンタ装置及び制御方法並びにプリンタ制御プログラムを格納したコンピュータ可読の記憶媒体
US20040109468A1 (en) * 2000-10-02 2004-06-10 Shakuntala Anjanaiah Apparatus and method for input clock signal detection in an asynchronous transfer mode interface unit
US6665795B1 (en) * 2000-10-06 2003-12-16 Intel Corporation Resetting a programmable processor
US20040059905A1 (en) * 2002-09-19 2004-03-25 Soulier George R. Method and apparatus for short-power cycle detection
US20040107375A1 (en) * 2002-12-02 2004-06-03 Edward Anglada System and method for switching clock sources
US8881233B2 (en) * 2005-05-23 2014-11-04 Microsoft Corporation Resource management via periodic distributed time
EP1934720B1 (en) * 2005-09-07 2018-02-14 Open Invention Network LLC Method and computer program for device configuration
US7979616B2 (en) * 2007-06-22 2011-07-12 International Business Machines Corporation System and method for providing a configurable command sequence for a memory interface device
US7624244B2 (en) * 2007-06-22 2009-11-24 International Business Machines Corporation System for providing a slow command decode over an untrained high-speed interface
US9547609B2 (en) * 2013-10-25 2017-01-17 Avago Technologies General Ip (Singapore) Pte. Ltd. Data interface for point-to-point communications between devices
CN114201440B (zh) * 2021-12-14 2024-06-07 上海微阱电子科技有限公司 时钟检测方法、电路、串口通信系统、介质和设备
CN119847617B (zh) * 2024-12-31 2025-10-28 研祥智慧物联科技有限公司 网口设备的控制方法、控制装置及网口设备

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5446403A (en) * 1994-02-04 1995-08-29 Zenith Data Systems Corporation Power on reset signal circuit with clock inhibit and delayed reset
US5513358A (en) * 1994-02-04 1996-04-30 Motorola, Inc. Method and apparatus for power-up state initialization in a data processing system
EP0787392B1 (en) * 1994-10-20 2002-06-05 Advanced Micro Devices, Inc. System and method for remote wake-up
KR970010634B1 (ko) * 1994-10-25 1997-06-28 삼성전자 주식회사 네트워크 하이버네이션 시스템
KR0156802B1 (ko) * 1995-11-07 1998-11-16 김광호 네트워크 하이버네이션 시스템 및 그 제어 방법

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